Ph n 1.

I2C
T ng quan
I2C (Inter-Intergrated Circuit, c l eye-two-see ho c eye-squared-see) l chu n giao ti p 2 dy (cn g i l Two-wired Serial interface) do Philips a ra. M c tiu l t o k t n i n gi n gi a cc IC v i cc IC khc ho c v i cc thi t b ngo i vi. Chu n I2C c h tr b i nhi u nh s n xu t IC v tr thnh chu n cng nghi p trong giao ti p i u khi n.

Ho t ng
Ch ho t ng
Giao ti p I2C c cc ch ho t ng l: o 1 Master v 1 Slave o 1 Master v nhi u Slave o nhi u Master v nhi u Slave y ch c p n ch c b n nh t l Master - Slave. I2C s d ng 2 ng n i d ng c c mng h l SDA - Serial Data v SCL - Serial Clock, do c n c n i v i i n tr ko ln. i n p s d ng th ng l +5V ho c +3.3V. SDA l chn truy n d li u v theo 2 h ng, trong khi , SCL l chn truy n xung clock v ch theo 1 h ng.

Khi Master truy n data cho Slave

Khi Master nh n data t Slave

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Trong k t n i I2C th Master gi vai tr i u khi n v gi nh p cho ton h th ng b ng xung clock trn chn SCL. Trong khi Slave hon ton th ng v c i u khi n b i Master (chu n khng c n ch nh ). Master c th truy n d li u cho Slave ho c nh n d li u t Slave. Tuy nhin, cc Slave khng th tr c ti p lm vi c v i nhau m ch c th thng qua Master.

a ch
M i thi t b tham gia vo giao ti p I2C c m t a ch duy nh t, bao g m 7 bits. a ch ny do nh s n xu t quy nh (m t s IC c th i u ch nh c a ch c a mnh b ng cch thay i cc bit a ch th p). IC STA015 c s d ng trong ti ny c a ch quy nh l 1000011b. Master s s d ng a ch ny giao ti p v i Slave mong mu n trn bus I2C. M t s a ch c bi t khng c s d ng: a ch R/W Ch thch 0000-000 0 General Call 0000-000 1 START byte 0000-001 x 0000-010 x 0000-011 x 0000-1xx x 1111-1xx x 1111-0xx x a ch slave 10 bits

V n t c truy n:
Standard mode 100 kHz Fast mode 400 kHz High-Speed mode 3.4 MHz

Truy n d li u

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Cc b c truy n d li u c b n c th tm t t nh sau:
- g i bit START (S) - g i a ch slave mu n giao ti p (ADDR) - g i bit READ(R)-1 ho c WRITE(W)-0 - ch / g i bit ACK - g i/nh n byte d li u (DATA) - ch / g i bit ACK - quay l i b c 5 n u mu n g i/nh n nhi u byte ho c g i bit STOP (P)

Truy n d li u t Master n Slave

Master g i chu i S - ADDR - W vo bus I2C v ch tn hi u ACK. N u c m t Slave c a ch ng v i chu i ADDR th n s pht tn hi u ACK. Khi Master s g i byte DATA v ch ACK, c l p i l p l i cho n khi truy n xong. Cu i cng Master g i P d ng ho c S b t u l i qu trnh truy n.

Truy n d li u t Slave n Master

Master g i chu i S - ADDR - R vo bus I2C v ch tn hi u ACK. N u c m t Slave c a ch ng v i chu i ADDR th n s pht tn hi u ACK v g i ti p byte DATA u tin. Sau khi nh n c byte DATA, Master g i l i ACK v byte DATA ti p theo l i c Slave g i. Khi khng mu n nh n thm d li u, Master g i tn hi u NACK v P / S. Tn hi u START v STOP ch c th c t o ra t Master. Ngay khi nh n c tn hi u ny, Slave s t reset m c gi tr logic c a mnh. i u ny cho php Master kh i ng l i ton b k t n i b t c khi no.

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START l p (Sr)
Ngay sau khi hon thnh vi c g i/nh n d li u v i m t Slave, Master c th ngay l p t c kh i t o m t k t n i m i n m t Slave khc m khng c n ph i qua giai o n STOP. V d : S-ADDR-(R/W)-ACK-DATA-ACK-Sr-ADDR-(R/W)-ACK-DATA-ACK-P ng d ng ch y u c a Sr l trong k t n i I2C v i nhi u Master, khi m m t Master d hon thnh vi c truy n d li u nhng khng mu n tr l i quy n ki m sot bus cho Master khc. Trong k t n i I2C m t Master th vi c ny l khng c n thi t.

nh d ng d li u truy n
M i block truy n bao g m 8 bits theo quy t c MSB-first, bit c tr ng s cao c truy n i tr c. Block kh i t o bao g m a ch 7 bits v 1 bit R/W. M i block c i km theo sau b i 1 tn hi u ACK.

Vi c thay i m c tn hi u trn SDA c th c hi n khi SCL m c cao s trng v i tn hi u START v STOP).

m c th p (n u

Bit ACK / NACK

Sau khi nh n c 8 bit DATA thnh cng, thi t b nh n s gi SDA m c th p trong xung clock k ti p t o tn hi u ACK nh m bo hi u cho bn g i. Vi c g i/nh n tn hi u l i ti p t c ho c d ng l i ty theo Master. N u vi c nh n d li u c l i, bn nh n s gi SDA m c cao trong xung clock k ti p nh m t o tn hi u NACK. Khi , c 2 tr ng h p: - Slave ang g i cho Master: Master s t o tn hi u STOP ho c reSTART. - Master ang g i cho Slave: thng th ng, Master s t o NACK sau khi nh n c byte DATA cu i cng, n bo hi u cho Slave bi t vi c truy n d li u k t thc.

M t s lu :
- Khi m t Slave c n th i gian thu th p d li u, x l ng t ho c v.v, n c th gi ng SCL m c th p. Master khi s ph i ch cho n khi SCL c gi i phng ti p t c.

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- S l ng thi t b g n k t vo bus I2C khng ch ph thu c vo s l ng a ch c th cung c p m cn bao g m c i n dung c a ton bus. M c i n dung t i a cho php l 400 pF.

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Ph n 2. L p trnh I2C v i ATmega8

T ng quan
M t s c i m
o o o o o Two-wire Serial Interface - TWI h tr c ch Master v Slave s d ng nh thi t b g i ho c nh n s d ng a ch 7 bits t c c th t 400kHz (Fast Mode)

Module TWI trong ATmega8

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Bit Rate Generator Unit

- ho t ng ch Master - ch a Bit Rate Register (TWBR) - i u khi n chu k c a chn SCL - cng th c SCL _ frequence = CPU _ clock _ frequence 16 + 2(TWBR ) * 4TWPS

Bus Interface Unit

- Data and Address Shift Register (TWDR), k t h p (N)ACK - START/STOP controller t o / pht hi n cc tn hi u START / reSTART / STOP - Arbitration detection (dng trong ch Multi-Master)

Address Match Unit

- Address Register (TWAR) ch a a ch - Address Comparator ki m tra a ch 7 bit nh n c c trng v i a ch trong TWAR hay khng

Control Unit
- TWI Control Register (TWCR) thi t l p cho ho t ng c a b TWI - khi c m t s ki n x y ra, c TWI Interrupt Flag (TWINT) c b t v TWI Status Register (TWSR) c c p nh t - khi TWINT Flag c b t, SCL s c gi m c th p chng trnh hon thnh cng vi c tr c khi vi c truy n / nh n d li u ti p t c (coi l i ph n trn)

***TWINT Flag c b t trong nh ng tr ng h p sau: - sau khi g i START / reSTART - sau khi g i SLA+R/W - sau khi g i 1 byte a ch - sau khi m t quy n ki m sot bus I2C - sau khi c Master g i b ng a ch ho c general call - sau khi nh n 1 byte d li u - sau khi nh n c STOP / reSTART - khi c l i trn ng truy n gy ra i u ki n START/STOP khng h p l

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Cc thanh ghi

Xc nh h s chia cho b Bit Rate Generator.

Bit 7 - TWINT: TWINT Interrupt Flag C TWINT c b t b ng ph n c ng. Khi c TWINT c b t, SCL s c gi m c th p. C TWINT ph i c xa b ng cch ghi gi tr 1 vo n. Lu , c khng c xa t ng b ng ph n c ng khi th c hi n hm ng t. Khi c TWINT c xa, cc ho t ng c a TWI c ti p t c, do ph i hon thnh cng vi c v i cc thanh ghi TWAR, TWSR, TWDR tr c khi xa c . Bit 6 - TWEA: TWI Enable Acknowledge Bit Khi c set gi tr 1, tn hi u ACK s c sinh ra khi g p cc i u ki n sau: - c Master g i t i b ng a ch c a mnh - nh n c General Call khi bit TWGCE c b t - nh n c 1 byte d li u khi lm Receiver Khi c set gi tr 0, thi t b coi nh c cch ly kh i k t n i I2C. Bit 5 - TWSTA: TWI START Condition Bit Set gi tr 1 cho TWSTA t o tn hi u START trn I2C bus. Ph i c xa b ng ph n m m sau khi tn hi u START c chuy n i. Bit 4 - TWSTO: TWI STOP Condition Bit ch Master, ghi gi tr 1 vo TWSTO s t o tn hi u STOP, sau bit s c xa t ng b ng ph n c ng. ch Slave, bit ny c dng gi i quy t l i. Khi ghi gi tr 1 vo n, thi t b coi nh c tch kh i I2C bus v s khng b g i t i b ng a ch , n cng gi i phng chn SCL v SDA. Bit 3 - TWWC: TWI Write Collision Flag

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Bit 2 - TWEN: TWI Enable Bit Set TWEN gi tr 1 cho php TWI, ng th i qu n l chn SCL v SDA. Ng c l i, set TWEN gi tr 0 s c m TWI, m i ho t ng TWI d ang di n ra cng b ngng l i. Bit 0 - TWIE: TWI Interrupr Enable Set gi tr 1 cho php ng t TWI. (Xem thm I-bit trong thanh ghi SREG).

Bit 7..3 - TWS: TWI Status Th hi n tr ng thi c a k t n i I2C. Bit 1..0 - TWPS: TWI Prescaler Bits Xem Bit Rate Generator Unit.

Bit 7..0 - TWD: TWI Data Register ch truy n, TWDR ch a byte d li u s c truy n k ti p. nh n, TWDR ch a byte d li u nh n c cu i cng.

ch

Bit 7..1 - TWA: TWI Address C n thi t l p a ch khi ho t ng trong ch Slave ho c Master v i k t n i Multi-Master. Bit 0 - TWGCE: TWI General Call Enable Set gi tr TWGCE ln 1 cho php General Call.

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S d ng module TWI trong AVR

K t n i TWI trong AVR theo nh d ng byte v d a trn ng t. Ng t c sinh ra sau m i s ki n trong TWI. D nhin, ng t ph i c cho php b i bit TWIE trong TWCR v bit Global Interrupt Enable. Khi ng t c sinh ra, TWSR s ch a gi tr tng ng v i tr ng thi c a TWI bus. Chng trnh c th quy t nh kh i TWI s ho t ng th no xung TWI-clock ti p theo b ng cch tc ng vo TWCR v TWDR.

Code v d
o n code v d v cch th c Master truy n 1 byte d li u cho Slave trong k t n i TWI:

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B ng gi tr c a TWI Status Register v i ch Master Transmitter.

B ng gi tr c a TWI Status Register v i ch Master Receiver.

***Ch Slave Transmitter/Receiver tham kh o thm trong Datasheet Atmega8 ***Ngu n tham kh o:
http://en.wikipedia.org/ http://atmel.com/

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