Interrupts

Temas Selectos de Electrnica

Definition
Exceptions that will stop CPU's current task in order to attend the interrupting event. Exceptions are events that require processing outside the normal flow of instruction execution.

Interrupt Types
Maskable(I, X*):
HW interrupts

Non-Maskable:
SW interrupts

Security Exceptions:
Reset Watchdog Illegal OPcode Each exception has an associated 16-bit vector, which points to the memory location where the routine that handles the exception is located.

CPU Interrupt Recognition Steps

IRQ request Finish current instruction (latency may vary due to CISC architecture) Acknowledge interrupt source Disable global Interrupts Save context Execute ISR (Interrupt Service Routine) Retrieve context Enable Global interrupts Execute next instruction

Interrupt Block Diagram

What if 2 interrupt happens at the same time?

Interrupt Priority
A hardware priority hierarchy determines which reset or interrupt is serviced first when simultaneous requests are made. Six sources are non-maskable. The remaining sources are maskable, and the device integration module typically can change the relative priorities of maskable interrupts

Priority decoder
The priority decoder evaluates all interrupts pending and determines their validity and priority. When the CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt request. There are 2 decoding configurations:
Daisy chain Parallel priority

Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request by the CPU is shown in Table 4-1.

 The I Maskable interrupt sources have default priorities that follow the address order of the interrupt vectors. The higher the vector address, the higher the priority of the interrupt. Typically, a device integration module incorporates logic that can give any one maskable source priority over other maskable sources.

Exception processing Flow

(refer to CPU chapter)