EXPERIENT NO.

8
OBJECTIVE: Implementation of Decade Counter using Verilog
//JK-flipflop module-1
module J_K_FF(reset, clk, J, K, Q);
input reset,clk,J,K
output Q;
reg tt=1'b0;
always@(negedge clk or posedge reset)
begin

if (reset)

tt<=#2 1'b0;
else if (J==1'b0 && K==1'b0)
tt<=#2 tt;
else if (J==1'b0 && K==1'b1)
tt<=#2 1'b0;
else if (J==1'b1 && K==1'b0)
tt<=#2 1'b1;
else if (J==1'b1 && K==1'b1)
tt<=#2 ~tt;
end
assign Q=tt;
endmodule
//Decade Counter module-2
module J_K_FF1(reset, clk, J, K, Q);
inout

reset;

input

clk, J, K;

output [3:0] Q;
reg

[3:0] t=4'b0000;

wire

reset;

J_K_FF FF0 (reset, clk, 1, 1,t[0]);

J_K_FF FF1 (reset, t[0], 1, 1,t[1]);
J_K_FF FF2 (reset, t[1], 1, 1,t[2]);

J_K_FF FF3 (reset, t[2], 1, 1,t[3]);

and (reset,t[3],~t[2],t[1],~t[0]);
always@(negedge clk or posedge reset)
begin

if (reset==1'b1)

#5

reset=1'b0;

end
assign Q=t;
endmodule

TEST BENCH CODING

module J_K_FF1_tb_v;
reg clk;reg reset;
// Outputs
wire [3:0] Q;
J_K_FF1 uut (.reset(reset),.clk(clk),.J(J),.K(K),.Q(Q));
always
begin
clk<=1'b1;
#5

clk<=1'b0;

#5

clk<=1'b1;

end
end
begin reset<=0; #100reset<=1;
#20
#100;
end
initial
#250
$finish;
endmodule

reset<=0;