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    Coe 141 Assignment 1

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    Rex Tan
    This document outlines 4 assignment problems for a digital circuits course. Problem 1 asks to find the range of values for CL that results in minimum delay for a 2-stage CMOS inverter buffer. Problem 2 asks to design a static CMOS XOR gate with equal input capacitance and pull-up/down strength as a 2:1 inverter. Problem 3 asks a similar question for a CMOS gate performing AB + C logic. Problem 4 asks to size gates in a 256x256 memory decoder for minimum delay.

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    Coe 141 Assignment 1

    Uploaded by

    Rex Tan
    8 views1 page
    This document outlines 4 assignment problems for a digital circuits course. Problem 1 asks to find the range of values for CL that results in minimum delay for a 2-stage CMOS inverter buffer. Problem 2 asks to design a static CMOS XOR gate with equal input capacitance and pull-up/down strength as a 2:1 inverter. Problem 3 asks a similar question for a CMOS gate performing AB + C logic. Problem 4 asks to size gates in a 256x256 memory decoder for minimum delay.

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    This document outlines 4 assignment problems for a digital circuits course. Problem 1 asks to find the range of values for CL that results in minimum delay for a 2-stage CMOS inverter buffer. Problem 2 asks to design a static CMOS XOR gate with equal input capacitance and pull-up/down strength as a 2:1 inverter. Problem 3 asks a similar question for a CMOS gate performing AB + C logic. Problem 4 asks to size gates in a 256x256 memory decoder for minimum delay.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    8 views1 page

    Coe 141 Assignment 1

    Uploaded by

    Rex Tan
    This document outlines 4 assignment problems for a digital circuits course. Problem 1 asks to find the range of values for CL that results in minimum delay for a 2-stage CMOS inverter buffer. Problem 2 asks to design a static CMOS XOR gate with equal input capacitance and pull-up/down strength as a 2:1 inverter. Problem 3 asks a similar question for a CMOS gate performing AB + C logic. Problem 4 asks to size gates in a 256x256 memory decoder for minimum delay.

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    Download as PDF, TXT or read online from Scribd
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    CoE 141 Assignment 1

    WFUM 2nd Semester SY 2010 - 2011 Due: 5pm Friday, January 14, 2011 (Rm 201) 1. Find the range of values for CL such that a 2-stage CMOS inverter buer will result in the smallest delay. Assume that the receiving circuit can handle any logic inversions that occur.

    CL

    Figure 1: Figure for problem 1. 2. Design a single complex static CMOS gate that implements the XOR logic operation F = A B. Size the transistors such that all the inputs have the same input capacitance, and also has the same pull-up and pull-down strength as a 2:1 inverter. (Hint: treat the complementary inputs also as a dierent input variable) 3. Design a single complex static CMOS gate that performs the logic operation F = AB + C. Size the transistors such that all the inputs have the same input capacitance, and also has the same pull-up and pull-down strength as a 2:1 inverter. 4. Path Optimization: (a) Size the dierent gates in the 256256-bit memory decoder (discussed in class) shown below, for minimum delay, using CL = 256Ccell and Cin = 4Ccell . (b) What is this minimum delay?
    3X 15X

    Cin

    b c d e f CL

    Figure 2: Figure for problem 4.

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