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Cratif....

Where ideas begin!

THE TEAM
Mohit Arora : 10116031 Piyush Gupta: 10116035 Prince Jain : 10116038 G. Sandeep : 10116017 Manda Sridhar: 10116024 Nand Kishor : 10116034 ECE A ECE A ECE B ECE A ECE A ECE A

What is Cratif all about??


A Reduced Instruction Set Computer (RISC) Processor. Implemented using VHDL Simulation will be done using XILINX ISE 13.2 software. A Development Board, FPGAs will be used for the implementation.

Cratif continues

A Sample of Instruction Set Detailed analysis later (from slide 15)

SPECIALITY OF RISC SYSTEMS


The key elements of RISC systems shared by most designs are: A simple instruction set. A large number of general purpose registers. Optimizing the instruction pipeline.

REVIEW OF INSTRUCTION CHARACTERISTICS:WHY WERE THOSE CHOSEN


Operations Performed Operands used Execution Sequencing MOST IMPORTANT: The use of a large register file. Why is it preferred over Cache Memory?

CHARACTERISTICS OF RISC
Only one Machine Cycle per instruction. Most operations are Register to Register. Use of simple addressing modes. Use of simple Instruction Formats.

Introduction
Alpha AXP- a 64-bit RISC ISA. Developed by- DEC in 1985. Designed to replace the 32-bit VAX CISC. It has no 32- bit version.

INSTRUCTION FORMAT

INSTRUCTION SET
Control Instruction

- Conditional Branch - Unconditional Branch - Jump Integer Arithmetic Instruction Logic and Shift Instruction

LAYOUT OF A PROCESSOR
Program Counter Registers System Buses Control Unit Arithmetic Logic Unit

INSTRUCTION SET

INSTRUCTION SET(Contd..)

REGISTERS
Points of Consideration: -Size of Registers -Number of Registers Making of a Register File Program Counter as a Register and its connection with the Control Unit.

Data Path

Control Unit

Execute Cycle

Very high speed integrated circuit Hardware Description Language.

Introduction
Already studied: Library definition Entity Architecture, Process Signal Component declaration

To be studiedPackage Function Declaration

Field Programmable Gate Array

Spartan 3-E

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