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محاكاة و نمذجة - ج 1 ع
محاكاة و نمذجة - ج 1 ع
محاكاة و نمذجة - ج 1 ع
:
-
.
(_)
( ; ).
.
: .
.
) (buffer, in, out, inout
.port
Begin
.
port .
:
A
B
E
D
VHDL
.
.Bit
.
:
Entity [ entity_name ] is
;Port (interface_Signal_declaration
;] End [entity_name
:
-
:full adder
X
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
Sum
0
1
1
0
1
0
0
1
Cout
0
0
0
1
0
1
1
1
( X Y ) Cin
. ) ( 3
.Sum=
S1
S2
S3
Cin
F.A
A0
F.A
B0
A1
F.A
B1
A2
Cout
F.A
B2
A3
B3
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