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HW 1
HW 1
HW 1
Ling Adder
1. 4-bit Ling Adder Verilog Code
//***** 4-bit ling adder *******
module ling4(s,cout,i1,i2,h0);
output [3:0] s;
//summation
output cout;
//carryout
input [3:0] i1;
//input1
input [3:0] i2;
//input2
input h0;
//
wire [3:0] t;
wire [3:0] g;
wire [4:1] h;
assign g[3:0]=i1[3:0] & i2[3:0];
//carry generation
assign t[3:0]=i1[3:0] | i2[3:0];
// ti = i1 + i2
assign h[1]=g[0] | (h0&t[0]);
//calculate each stage carryout
assign h[2]=g[1] | g[0] | (t[0]&h0));
assign h[3]=g[2] | g[1] | (g[0]&t[1]) | (t[0]&t[1]&h0);
assign h[4]=g[3] | g[2] | (g[1]&t[2]) | (g[0]&t[1]&t[2]) | (t[0]&t[1]&t[2]&h0);
assign cout=h[4] & t[3];
//real carryout
assign s[0]=(t[0] ^ h[1]) | (h0 & t[0] & g[0]); //calculate summation
assign s[3:1]=(t[3:1] ^ h[4:2]) | (h[3:1] & t[2:0] & g[3:1]);
endmodule
2. 16-bit Ling Adder Verilog Code
//***** 16-bit ling adder *******
module ling16(sum,carryout,toutput,A_in,B_in,carryin,tinput);
output [15:0] sum;
//
output carryout;
// C16
input [15:0] A_in;
// A
input [15:0] B_in;
// B
input carryin;
// C0
wire [2:0] carry;
// each stage carryout C4 C8 C12
ling4 l1(sum[3:0],carry[0], A_in[3:0],B_in[3:0],carryin);
ling4 l2(sum[7:4],carry[1], A_in[7:4],B_in[7:4],carry[0]);
ling4 l3(sum[11:8],carry[2], A_in[11:8],B_in[11:8],carry[1],);
ling4 l4(sum[15:12],carryout,A_in[15:12],B_in[15:12],carry[2]);
endmodule
3. 16-bit Ling Adder Testbench
module stimulus;
reg [15:0] a;
reg [15:0] b;
reg cin;
wire [15:0]summation;
wire carry16;
ling16 u1(summation,carry16,,a,b,cin);
initial
#10 a=16'b1000000000001001;b=16'b1000000000001001;cin=1'b0;
#10 a=16'b1010101010101010;b=16'b0101010101010111;cin=1'b0;
#10 a=16'b0101010101010101;b=16'b0101010101010101;cin=1'b1;
#10 a=16'b1111111111111111;b=16'b0000000000000001;cin=1'b0;
#50 $finish;
end
initial
begin
$fsdbDumpfile("ling.fsdb");
$fsdbDumpvars;
end
endmodule
CLA
3.11
2073.6
Manchester
6.28
2211.84
Ling
6.93
2350.08
Design Optimization