LOGIC DIAGRAM:

TRUTH TABLE:
a
0
0
0
0
1
1
1
1

Inputs
b
0
0
1
1
0
0
1
1

c
0
1
0
1
0
1
0
1

do
0
0
0
0
0
0
0
1

d1
0
0
0
0
0
0
1
0

d2
0
0
0
0
0
1
0
0

Outputs
d3 d4
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0

TESTBENCH PROGRAM:
module Testbench;
reg a, b, c;
wire [7:0] d;
Decoder111 Decoder_1(a,b,c,d);
initial
begin

d5
0
0
1
0
0
0
0
0

d6
0
1
0
0
0
0
0
0

d7
1
1
0
0
0
0
0
0

//case 0
a = 0; b= 0; c=0;
#1 $display("d = %b", d);
//case 1
a = 0; b= 0; c=1;
#1 $display("d = %b", d);
//case 2
a = 0; b= 1; c=0;
#1 $display("d = %b", d);
//case 3
a = 0; b= 1; c=1;
#1 $display("d = %b", d);
//case 4
a = 1; b= 0; c=0;
#1 $display("d = %b", d);
//case 5
a = 1; b= 0; c=1;
#1 $display("d = %b", d);
//case 6
a = 1; b= 1; c=0;
#1 $display("d = %b", d);
//case 7
a = 1; b= 1; c=1;
#1 $display("d = %b", d);

end
endmodulelay("d = %b", d);
//case 7
a = 1; b= 1; c=1;
#1 $display("d = %b", d);
end
endmodule

OUTPUT WAVEFORM: