VL802 Low Power VLSI Design: Home work 1 Due on 9-4-2012 NOTE: In this assignment you should use

se 0.18m MOS transistor models and a power supply of 1.8V all your simulations. 1. Simulate an inverter and determine the short circuit power for the following cases. Wn = 0.2m, Ln = 0.18m, Wp = 0.5m, Lp = 0.18m, a) Input voltage is a 1MHz square wave of 0-1.8V amplitude with a rise (Tr) and fall (Tf) time of 0.1ns each. CL = 10fF and CL = 100fF b) Change rise and fall time to 0.5ns and repeat step (a) above. c) Determine the leakage power of the inverter for an input of 0 and an input of 1.8V and the back bias of the NMOS transistor is varied from 0.2V to -1.0V in steps of 0.2V 2. Design a CMOS circuit to implement the function F = A( B + C ) . Choose the device sizes such that the rise and fall times for the circuit are same as that of a min. sized inverter (Hint: you need to size the transistors appropriately). Assume the static probabilities of the inputs as PA = 0.9, PB = 0.4 and P = 0.2 . Compute the C dynamic power dissipated by the circuit for different transistor ordering. 3. Design single and double edge triggered D-flip flops and analyze the two for their relative power dissipation under the following conditions. Load Cap : = 100fF Clk : 1MHz Data rates (KHz) : 50 to 500 in steps of 50KHz. NOTE: 1) Assume any missing data appropriately Justify your assumptions. 2) You may use any circuit simulation tool (such as Tanner / electric / any Spice tool) for simulation. 3) You are required to submit a total of not more than four page summary of your findings along with the reasons for the observed results.