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    divyaftm
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    This document describes a VLSI implementation of a distributed architecture-based discrete cosine transform (DCT) circuit. The circuit uses a global clock signal that is divided and generates cosine values. It includes a 4-bit counter, clocked latch, complex accumulator, cosine value generator, and decoder. The design was simulated and provides a sample platform for performing a 1-dimensional DCT by integrating the module with a system on a chip platform to support multiple inputs.

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    Mpsoc Dct Part

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    This document describes a VLSI implementation of a distributed architecture-based discrete cosine transform (DCT) circuit. The circuit uses a global clock signal that is divided and generates cosine values. It includes a 4-bit counter, clocked latch, complex accumulator, cosine value generator, and decoder. The design was simulated and provides a sample platform for performing a 1-dimensional DCT by integrating the module with a system on a chip platform to support multiple inputs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as doc, pdf, or txt
    15 views3 pages

    Mpsoc DCT Part

    Uploaded by

    divyaftm
    This document describes a VLSI implementation of a distributed architecture-based discrete cosine transform (DCT) circuit. The circuit uses a global clock signal that is divided and generates cosine values. It includes a 4-bit counter, clocked latch, complex accumulator, cosine value generator, and decoder. The design was simulated and provides a sample platform for performing a 1-dimensional DCT by integrating the module with a system on a chip platform to support multiple inputs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as doc, pdf, or txt
    of 3

    VLSI IMPLEMENTATION OF DISTRIBUTED ARCHITECTURE BASED DCT

    System Global clock

    Clock Divider Reset 4 bit Counter

    Clocked Latch

    Complex Accumulato r

    Cos value generator

    Decoder

    DCT Output

    Reference Signals

    About CODE: This module is one part of the MPSOC Projects, here the Discrete cosine transform module is implemented and simulated. A sample platform for 1d DCT is designed her, Bu integrating the module with Soc platform we can provide N number of inputs .

    DATA FLOW OUTPUT

    Clock divider & Cos gen

    Complex Accumulator

    Counter with Latch

    Counter With Decoder

    Simulation Result

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