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    Clock Gate

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    mailsrikanth007
    The original RTL design had an asynchronous interface between two clocks (clka and clkb) with a MUX. After running the compile_ultra -gate_clock command, the MUX was replaced with an inserted clock gating (ICG) cell that has an enable signal controlled by clkb to gate clka.

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    Clock Gate

    Uploaded by

    mailsrikanth007
    90 views2 pages
    The original RTL design had an asynchronous interface between two clocks (clka and clkb) with a MUX. After running the compile_ultra -gate_clock command, the MUX was replaced with an inserted clock gating (ICG) cell that has an enable signal controlled by clkb to gate clka.

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    The original RTL design had an asynchronous interface between two clocks (clka and clkb) with a MUX. After running the compile_ultra -gate_clock command, the MUX was replaced with an inserted clock gating (ICG) cell that has an enable signal controlled by clkb to gate clka.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    90 views2 pages

    Clock Gate

    Uploaded by

    mailsrikanth007
    The original RTL design had an asynchronous interface between two clocks (clka and clkb) with a MUX. After running the compile_ultra -gate_clock command, the MUX was replaced with an inserted clock gating (ICG) cell that has an enable signal controlled by clkb to gate clka.

    Copyright:

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    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    of 2

    Pre ICG insertion (RTL Description)

    MUX Din sel

    clka clkb

    Already existing async interface between clocka and clockb in RTL

    After compile_ultra gate_clock Insertion


    ICG

    en

    Din

    Enclkb clka

    clkb

    Replacement of MUX by an ICG

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