26-FEB-2012:

tested fpga2_downval_1hour_sleep,
tic s were moving in FH,OBH1 ,trades were generated after 1 hr.
compiled & generated rbf's for fpga4,fpga9 . ma ing the copy of fpga4_obh_nse_c
m_v1.07 to (fpga4_stragy_dwnval_v1.09_24feb12, added new files 2 it ) & fpga9_ns
e_cm_rj_adj_bridge2_corr_19feb12_dbug_q_v1.07 to (fpga9_nse_cm_dwnval_bridge2_co
rr_dbug_v1.09_24feb12, added new files).
----------------------------------------------27-FEB-2012:
IN LOGS/ (03,01,05,0D )MEANS TO(PAIR_INFO,ord_bits,stoc _code,fpga(2)addr)
---------------------------------------------------------------------28-FEB-2012:
generated a testbench for bridge2 & bridge_patch ,for stoc 02,04,06,08 7 pairs
03,06,09,12,
executed in correct way for these conditions, generated dummy response for thes
e stoc _pairs,satisfying o3 condition at trd2 cancel.
for stoc code cant go zeros,use cloc condition for triggering signal in synch
,
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