****************************************

Report : timing
-path full
-delay max
-max_paths 1
Design : seq
Version: E-2010.12-SP5-2
Date : Mon Mar 26 16:54:29 2012
****************************************
Operating Conditions: TYPICAL
Wire Load Model Mode: top

Library: saed90nm_typ_ht

Startpoint: inp (input port cloc ed by cl )

Endpoint: outp_reg (rising edge-triggered flip-flop cloc ed by cl )
Path Group: cl
Path Type: max
Des/Clust/Port
Wire Load Model
Library
-----------------------------------------------seq
ForQA
saed90nm_typ_ht
Point
Incr
Path
----------------------------------------------------------cloc cl (rise edge)
0.00
0.00
cloc networ delay (ideal)
0.00
0.00
input external delay
1.00
1.00 r
inp (in)
0.00
1.00 r
U6/Q (XNOR2X2)
0.24
1.24 r
U3/Q (AO22X2)
0.16
1.40 r
outp_reg/D (DFFX2)
0.03
1.43 r
data arrival time
1.43
cloc cl (rise edge)
2.00
2.00
cloc networ delay (ideal)
0.00
2.00
outp_reg/CLK (DFFX2)
0.00
2.00 r
library setup time
-0.15
1.85
data required time
1.85
----------------------------------------------------------data required time
1.85
data arrival time
-1.43
----------------------------------------------------------slac (MET)
0.42
1