VHDL PROGRAM FOR D-FF library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; entity dff is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; q : buffer STD_LOGIC); end dff; architecture Behavioral of dff is begin process(d,clk) variable temp :STD_LOGIC; begin if clk='1' and clk'event then temp := d; else temp := q; end if; q<=temp; end process; end Behavioral;

VHDL PROGRAM FOR T-FF library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : buffer STD_LOGIC); end tff; architecture behavioral of tff is begin process(t,clk) variable temp:STD_LOGIC; begin if clk='1' and clk'event and t='1' then temp:= not q; else temp:= q; end if; q<=temp; end process; end behavioral;

VHDL PROGRAM FOR MUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; s0 : in STD_LOGIC; s1 : in STD_LOGIC; z : out STD_LOGIC); end mux; architecture Behavioral of mux is begin process(a,b,c,d,s0,s1) begin if s0='0' and s1='0' then z<=a; elsif s0='0' and s1='1' then z<=b; elsif s0='1' and s1='0' then z<=c; else z<=d; end if; end process; end Behavioral;

VHDL PROGRAM FOR DEMUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux is Port ( x : in STD_LOGIC; s0 : in STD_LOGIC; s1 : in STD_LOGIC; y0 : out STD_LOGIC; y1 : out STD_LOGIC; y2 : out STD_LOGIC; y3 : out STD_LOGIC); end demux; architecture Behavioral of demux is begin process(x,s0,s1) begin if s0='0' and s1='0' then y0<=x; elsif s0='0' and s1='1' then y1<=x; elsif s0='1' and s1='0' then y2<=x; else y3<=x; end if; end process; end Behavioral;

VHDL PROGRAM FOR 2:4 DECODER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec is Port ( a : in STD_LOGIC; b : in STD_LOGIC; e : in STD_LOGIC; z1 : out STD_LOGIC; z2 : out STD_LOGIC; z3 : out STD_LOGIC; z4 : out STD_LOGIC); end dec; architecture data of dec is signal abar,bbar:STD_LOGIC; begin z1 <= not (abar and bbar and e); abar <= not a; bbar <= not b; z2 <= not (abar and b and e); z3 <= not (a and bbar and e); z4 <= not (a and b and e); end data;

VHDL PROGRAM FOR FULL ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FA is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; s : out STD_LOGIC; cr : out STD_LOGIC); end FA; architecture data of FA is begin s <= a xor b xor c; cr <= (a and b)or(b and c)or(a and c); end data;

VHDL PROGRAM FOR HALF ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HA is Port ( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC); end HA; architecture data of HA is begin s <= a xor b; c <= a and b; end data;

VHDL PROGRAM FOR PARITY GENERATOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity parity is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; e : in STD_LOGIC; f : in STD_LOGIC; g : in STD_LOGIC; h : in STD_LOGIC; even : buffer STD_LOGIC; odd : out STD_LOGIC); end parity; architecture DATA of parity is signal i,j,k,l,m,n:STD_LOGIC; begin i<=a xor b; j<=c xor d; k<=e xor f; l<=g xor h; m<=i xor j; n<=k xor l; even<=m xor n; odd<=not even; end DATA;