CMOS Layers

n-well process p-well process Twin-tub process

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n-well process
Gate NMOS NMOS FOX PMOS PMOS

n+

n+

n+

n+

p+

p+

p+

p+

n-well p-substrate

MOSFET Layers in an n-well process

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Layer Types

p-substrate n-well n+ p+ Gate oxide Gate (polycilicon) Field Oxide

Insulated glass Provide electrical isolation

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Top view of the FET pattern

NMOS NMOS PMOS PMOS

n+

n+

n+

n+

p+

p+

p+

p+

n-well

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Metal Interconnect Layers

Metal layers are electrically isolated from each other Electrical contact between adjacent conducting layers requires contact cuts and vias

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Metal Interconnect Layers

Ox3 Via Metal2 Active contact Ox2

Metal1
Ox1 n+ n+ n+ n+

p-substrate

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Interconnect Layout Example

Gate contact Metal1 Metal2 Metal1 MOS

Active contact

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Designing MOS Arrays

A B C

x A B C

x
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Parallel Connected MOS Patterning

B A

x B X X

X y

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Alternate Layout Strategy

x x X A B A X X B X

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Basic Gate Design

Both the power supply and ground are routed using the Metal layer n+ and p+ regions are denoted using the same fill pattern. The only difference is the nwell Contacts are needed from Metal to n+ or p+

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The CMOS NOT Gate

Vp Contact Cut Vp

X
X

n-well

X Gnd Gnd

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Alternate Layout of NOT Gate

Vp Vp

x
X Gnd X

Gnd

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NAND2 Layout
Vp Vp

a.b a.b
X Gnd X

Gnd

b
a

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NOR2 Layout
Vp Vp X X

ab

ab
X

Gnd

b
Gnd

a b

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NAND2-NOR2 Comparison
Vp X X X

X X Gnd Vp X X

MOS Layout

Wiring Gnd
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X X

General Layout Geometry

Vp Shared drain/ source

Individual Transistors
Gnd

Shared Gates

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Graph Theory: Euler Path

Vp x x Vertex b c

Edge

a Out

y y Vertex a

Gnd
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Stick Diagram

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Stick Diagrams
Cartoon of a layout.

Shows all components.

Does not show exact placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of compliance with layout or design rules. Useful for interconnect visualization, preliminary layout layout compaction, power/ground routing, etc.

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Stick Diagrams Metal poly ndiff

pdiff
Can also draw in shades of gray/line style.

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Stick Diagrams
Buried Contact

Contact Cut

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5V

5v

Dep

Vout

Enh

Vin

0V

0V
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Stick Diagram - Example I

A
OUT

NOR Gate

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Stick Diagram - Example II

Power

Out

C B
Ground

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Points to Ponder
be creative with layouts
sketch designs first

minimize junctions but avoid long poly runs

have a floor plan plan for input, output, power and ground locations

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The End

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