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    Vlsi Cat-3

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    THIRUNEELAKANDAN
    The document is an exam paper for an Electronics and Communication Engineering course. It contains questions about VLSI design and testing techniques. It asks the student to explain system level test techniques, self-test techniques and memory self-test techniques in detail. It also asks the student to briefly explain automatic test pattern generation technique.

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    Vlsi Cat-3

    Uploaded by

    THIRUNEELAKANDAN
    14 views1 page
    The document is an exam paper for an Electronics and Communication Engineering course. It contains questions about VLSI design and testing techniques. It asks the student to explain system level test techniques, self-test techniques and memory self-test techniques in detail. It also asks the student to briefly explain automatic test pattern generation technique.

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    VLSI_CAT-3

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    The document is an exam paper for an Electronics and Communication Engineering course. It contains questions about VLSI design and testing techniques. It asks the student to explain system level test techniques, self-test techniques and memory self-test techniques in detail. It also asks the student to briefly explain automatic test pattern generation technique.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    14 views1 page

    Vlsi Cat-3

    Uploaded by

    THIRUNEELAKANDAN
    The document is an exam paper for an Electronics and Communication Engineering course. It contains questions about VLSI design and testing techniques. It asks the student to explain system level test techniques, self-test techniques and memory self-test techniques in detail. It also asks the student to briefly explain automatic test pattern generation technique.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    of 1

    SURYA GROUP OF INSTITUTIONS SCHOOL OF ENGINEERING & TECHNOLOGY

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEETRING

    (b). Explain in detail about System Level Test Techniques.

    (15)

    CAT-III/ APR12

    Sixth semester
    EC2354-VLSI DESIGN

    12. (a). With the essential circuit modules, explain in details about Self-Test Techniques and Memory Self-Test Techniques. (15) Max marks: 50 (OR)

    Time: 90 min
    PART A

    (10X2=20)

    (b).Explain briefly about Automatic Test Pattern Generation Technique. (15)

    1. What are the advantages of pseudo-nMOS circuits? 2. What is SFPL? 3. What are footed and unfooted dynamic circuits? 4. What are the properties of domino logic? 5. What is called pulsed latch? 6. What is the need of testing?

    7. What is burn-in testing?


    8. What is stuck-at fault? 9. What is controllability and observability? 10. What is delay fault testing?
    PART B (2X15=30)

    11.(a). Explain in details the sequence of Scan Design Techniques. (15) (OR)

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