Sumador completo de 1 bit library ieee; use ieee.std_logic_1164.

all; entity suma is port(a,b,c:in std_logic; s,k:out std_logic); end; architecture sumador of suma is begin s <= (a xor b) xor c; k <= ((a xor b ) and c) or (a and b); end sumador;

Sumador completo de 5 bits library IEEE; use IEEE.std_logic_1164.all; entity suma5 is port ( A, B: in std_logic_vector(4 downto 0); CI : in std_logic; S: out std_logic_vector(4 downto 0); CO : out std_logic); end suma5; architecture flow1 of suma5 is component suma port ( A, B, CI : in std_logic; S, CO : out std_logic); end component; signal X: std_logic_vector(2 downto 0); begin x1: suma port map (A(0), B(0), CI, S(0), X(0)); x2: suma port map (A(1), B(1), X(0), S(1), X(1)); x3: suma port map (A(2), B(2), X(1), S(2), X(2)); x4: suma port map (A(3), B(3), X(2), S(3), X(3)); x5: suma port map (A(4), B(4), X(3), S(4), k); end flow1;