Microcontroller based system design

Prepared By Ansiya Eshack

Standard ttl inverter circuit totem pole arrangement

Operation of ttl inverter

TTL nand gate circuit

Open collector inverter circuit

Tristate inverter circuit

EQUIVALENT CIRCUIT FOR TRISTATE OUTPUT IN THE HIGH-Z STATE

MOSFET SYMBOLS

n-channel switch

p-channel switch

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CMOS INVERTER CIRCUIT

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CMOS NAND GATE

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COMPARISON OF TTL & CMOS PERFORMANCE

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BASIC PROGRAMMABLE OR ARRAY

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BASIC PROGRAMMABLE AND ARRAY

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PROGRAMMABLE READ ONLY MEMORY (PROM)

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PROGRAMMABLE LOGIC ARRAY (PLA)

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PROGRAMMABLE ARRAY LOGIC (PAL)

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GENERIC ARRAY LOGIC (GAL)

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BASIC PLA STRUCTURE

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UNPROGRAMMED

COMPACT PLA STRUCTURE

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UNPROGRAMMED

PLA EXAMPLE

Z1=X2X1X0+X2X1X0+X2X1X0
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Z0=X2X1X0+X2X1X0

BASIC PAL STRUCTURE

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PAL IMPLEMENTATION OF AN SOP EXPRESSION

A A B B

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X=AB+AB+AB

AB

AB

X=AB+AB+AB

AB
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X=ABC+ABC+AB+AC

TRISTATE CONTROL

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ACTIVE LOW OUTPUT

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ACTIVE LOW INPUT/OUTPUT

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PROGRAMMABLE POLARITY OUTPUT

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STANDARD PAL NUMBERING

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PAL 16L8

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PAL 16L8

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BASIC GAL STRUCTURE

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GAL ARRAY

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GAL 22V10 OUTPUT LOGIC MACROCELL (OLMC)

GAL 22V10 OLMC CONFIGURATIONS S1=0 S0=0 Active-LOW registered mode

GAL 22V10 OLMC CONFIGURATIONS S1=0 S0=1 Active-HIGH registered mode

GAL 22V10 OLMC CONFIGURATIONS S1=1 S0=0 Active-LOW combinational mode

GAL 22V10 OLMC CONFIGURATIONS S1=1 S0=1 Active-HIGH combinational mode