Digital Receiver Block Diagram

20 channels of I/Q @ 2.16MSPS 16-bit

DDR RAM 16Mx16

12-bit 130/208 MSPS

A/D

A/D Intf

UWB 1 of 2

10 channels of I/Q @ 1.0833MSPS 16-bit Clock DCM In = DSP1 EMIF Clk Out = DSP1 EMIF Clk

Quadia Logic 1 of 2
Dual Queue VFIFO

1 of 20 channels Clk Clock circuitry

A/D Mux Mixer Gain CIC 60:1 J4 Link

1 of 20 channels J4 link
Test Mux

FIFO Test Mux

Data Flow Controller

FIFO Overflow detect DSP1 Registers

FIR 2:1

Spectral invert

DSP

FIFO

FIFO Interrupts

A/D
12-bit 130/208 MSPS

A/D Intf

NCO

Test Generator

Registers
A/D input select Mixer Freq Rev Code Status Gain Test

Register Test Controls 2-bit

Register Spectral Inversion 20-bit Overflow detect DSP2 Registers DRR FIFO Thresh

10 channels of I/Q @ 1.0833MSPS 16-bit

Triggering Register Rev Codes Clock DCM

StatusRegister DCMs locked

DSP

Command Channel

Input = Fs/60 Output1 = Fs*22/60

Clock DCM In = DSP2 EMIF Clk Out = DSP2 EMIF Clk Reset

Interrupts

PCI

PCI FPGA

Revisions 9/1/05 Initial Entry DM 9/8/05 Corrected diagram to have 20 channels 9/14/05 Updated for CIC Rate 9/30/05 Updated sample rate to 208 MSPS

Confidential