Code: R5 210504

R5
DIGITAL LOGIC DESIGN
(Common to CSS, IT and CSE)

B.Tech II Year I Semester (R05) Supplementary Examinations, May 2012

Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) 2 (a) (b) Solve for x (i) (257) 8 = (x) 2 (ii) 21.625) 10 = (x) 8 = (iii) (BC.2) 16 = (x) 8 Convert (163.875) 10 to binary, octal and hexadecimal

Max Marks: 80

(iv) (33) 10 = (201) x

Obtain the dual of the following expressions (i) AB + A (B+C) + B (B+D) (ii) A+B+ABC. Why NAND and NOR gates are known as universal gates? Simulate all the logical operations using NAND and NOR gates. Minimize the following expression using K-map and realize using NAND gates f = m (0, 1, 4, 5, 6, 7, 9, 11, 15) + d (10, 14). Minimize the following expression using K-map and realize using NOR gates. F m (0,4, 6,7,8,12,13,14,15) Explain the difference between a MUX and DEMUX. Realize 16 input multiplexer by cascading of two 8-input multiplexers 74151. Explain the operation of a 3-to-8 decoder 74 LS 138 realize 4 to-16 decoder using two 3-to-8 decoder. Explain about the radiation of SR flip flop, JK flip flop using D Flip Flop. Explain about the analysis of clocked sequential circuits in detail. Explain the difference between asynchronous and synchronies counter. Design MOD 10 ripple counter. Design and construct MOD-5 synchronous counter using JK Flip Flop. Explain in detail about sequential programmable devices. Explain in detail about ROM. What do you mean by hazard? Classify and explain. Explain the methods to eliminate static hazards in asynchronous circuits. *****

3 (a) (b)

4 (a) (b)

5 (a) (b) 6 (a) (b) 7 (a) (b) 8 (a) (b)