Slide 1

Hp ng MCS 51
GV: Trn Nht Khi Hon

S chn

Slide 2

Nhc li tn gi cc thanh ghi

Slide 3

Trng thi cc thanh ghi khi Reset

Slide 4

Cu trc chng trnh Hp ng MCS 51

Slide 5

Mt s lu
Phn ch thch phi t sau du ; Nhn:
Dng cho cc lnh nhy Phi vit lin tc, v kt thc bng du : Nhn lun bt u bng mt k t

Slide 6

Tn chng trnh con (ging nh nhn):

Phi vit lin tc, v kt thc bng du : Nhn lun bt u bng mt k t

Khng phn bit ch hoa, thng

Lnh gi Dng hng dn trnh bin dch Dng h tr ngi lp trnh Khng c bin dch sang m my Khng phn bit ch hoa hay thng

Slide 7

Mt s lnh gi thng s dng

Org: dng t on m v tr mong mun DB (defined bytes): dnh mt s nh trong vng RAM, ROM chng trnh EQU (equal): dng t tn bin hoc nh ngha hng s DATA: Tng t nh EQU, nh ngha bin 8 bit BIT: Tng t EQU, nh ngha bin 1 bit Dseg, Cseg, Bseg: nh ngha v tr u cc phn on Data, Code v Bit DS: dnh mt hoc mt s bytes trong vng RAM AT: Xc nh a ch vng nh cn t phn on

Slide 8

Cc bc Son tho chng trnh hp ng

Slide 9

Bi tp
U7 AT 89C51 39 38 37 36 35 34 33 32 P0.0/A D0 P0.1/A D1 P0.2/A D2 P0.3/A D3 P0.4/A D4 P0.5/A D5 P0.6/A D6 P0.7/A D7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XT AL1 XT AL2 RS T EA /VP P P2.0/A 8 P2.1/A 9 P2.2/A 10 P2.3/A 11 P2.4/A 12 P2.5/A 13 P2.6/A 14 P2.7/A 15 P3.0/RXD P3.1/T XD P3.2/INTO P3.3/INT1 P3.4/T O P3.5/T 1 P3.6/WR P3.7/RD PS EN ALE /PROG 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 29 30 VCC

Slide 10

VCC

220
D1

220 D1 D2
2

Q1 1

8.2K

1 2 3 4 5 6 7 8 19 18 9 31

1 2MHz

33pF

33pF

Lp trnh cho led D1 sng D2 tt trong 0.5s. Sau , D1 tt v D2 sng trong 0,5s v lp li Gi s c chng trnh delay500ms

Bi tp 1. Thit k mch gm 24 led gn vo 3 port 2. Vit chng trnh:

Slide 11

1. Cho 1 led port 0 sng chy t tri sang phi, 2. Sau 1 led ca Port 2 sng chy t phi sang tri, 3. Cui cng l 1 led ca port 3 sng chy t tri sang phi 4. lp li 3 cng vic trn v hn ln

Lp trnh c cu trc Phn phi vng nh V lu Vit chng trnh con

Slide 12

Bi tp V mch in Lp trnh c cu trc

Slide 13