Professional Documents
Culture Documents
Xem Them Vixulychuong3
Xem Them Vixulychuong3
Xem Them Vixulychuong3
NGNH IN T-VIN THNG I HC BCH KHOA NNG CA H VIT VIT, KHOA CNTT-TVT
Ti liu tham kho [1] K thut vi x l, Vn Th Minh, NXB Gio dc, 1997 [2] K thut vi x l v Lp trnh Assembly cho h vi x l, Xun Tin, NXB Khoa hc & k thut, 2001
CHNG 3 VI X L 8088-INTEL
3.1 Kin trc v hot ng ca 8088 - Nguyn l hot ng - S khi chc nng 3.2 Cu trc thanh ghi ca 8088 3.3 Phng php qun l b nh 3.4 M t tp lnh Assembly
Nguyn l hot ng ca mt b vi x l
Tm v copy cc byte lnh t b nh
Gii m lnh
N V THC HIN - EU
Bao gm CU v ALU CU : Gii m lnh to ra cc tn hiu iu khin nhm thc hin lnh c gii m ALU: thc hin cc thao tc khc nhau i vi cc ton hng ca lnh
T CHC CA MICROPROCESSOR
CPU Control registers
Status Registers
Mt th tc n gin gm 3 bc:
Ly
Fetch 1
Decode 1
Execute 1
Fetch 2
Decode 2
Execute 2
...
Microprocessor
Busy
Idle
Busy
Busy
Idle
Busy
...
Bus
C CH PIPELINING
Pipelining
Fetch 1
Fetch 2
Fetch 3
Fetch 4
Store 1
Fetch 5
Fetch 6
Load 2
Fetch 7 Idle
...
Bus
Decode Decode 5 6
Decode 7
...
Instruction Unit
Exec. 1
Exec. 2
Exec. 3
Exec. 4
Idle Idle
Exec. 5
Exec. 6
Idle
Exec. 7
Execution Unit
Memory request
Memory request
Instr Pointer
EIP BL
Index Registers
IP
Stack Pointer
FLAG ESP
SP
Base
EBX
BH BX
Flags
EFLAG
Base Pointer
EBP
BP
Count
CH CX ECX
CL
Segment Registers
CS
Dest Index
EDI
DI
Data
DH DX EDX
DL DS
Source Index
ESI
SI
ES
SS FS GS
Extra Segment
Stack Segment
AH BH CH DH CS DS SS ES
15
AL BL CL DL
0
AX BX CX DX
IP SP BP SI DI
} }
AH BH CH DH
AL BL CL DL
AX BX CX DX
- Lu tr tm thi d liu truy cp nhanh hn v trnh khi phi truy cp b nh - C cng dng c bit i vi mt s cu lnh
CS DS SS ES
- Lu tr a ch segment ca mt nh cn truy cp
IP SP BP SI DI
- Lu tr a ch offset ca mt nh cn truy cp
THANH GHI C
15 0
x OF DF IF TF SF ZF x AF x PF x CF
- Khng phi tt c cc bit u c s dng - Mi bit c s dng c gi l mt c - Cc c u c tn v c th c Lp/Xo ring l - Bao gm cc c trng thi v cc c iu khin
FLAGS REGISTER
80386, 80486DX
80286
80486SX
3.3 PHNG PHP QUN L B NH - B nh c xem l mt tp hp cc nh - Mi nh c nhn dng bng mt a ch vt l duy nht 20-bit - Trong hot ng truy cp mt nh, a ch vt l ca n c to ra t hai gi tr 16-bit: a ch segment v a ch Offset - a ch logic = a ch segment:a ch offset
19 a ch vt l
15
15
0000
3.4 M T TP LNH ASSEMBLY CA 8086/8088 - Khun dng: Mnemonics Cc ton hng - Nhm lnh chuyn s liu - Nhm lnh s hc - Nhm lnh logic - Nhm lnh R nhnh - Nhm lnh thao tc string - Nhm lnh hn hp
NHM LNH CHUYN S LIU DATA TRANSFER INSTRUCTIONS -Chuyn s liu (sao chp s liu) t v tr ny sang v tr khc - Ngun s liu khng thay i - ich s c gi tr nh gi tr ca Ngun - Cc lnh chuyn s liu khng nh hng n cc c trng thi trn thanh ghi c - Mt s lnh tiu biu: MOV, XCHG
DATA TRANSFER INSTRUCTIONS - MOV KHUN DNG: MOV CH,NGUN - Tc dng: (ch) (Ngun) - ch: c th l:
1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)
Ngun: c th l:
MT S LU I VI MOV
- ch v Ngun phi c cng kch c - ch v Ngun khng th ng thi thuc b nh - Nu ch l mt thanh ghi segment ca VXL th Ngun khng th l mt gi tr c th (ni cch khc, khng th np gi tr trc tip cho mt thanh ghi segment bng lnh MOV)
T/h2: c th l:
MT S LU I VI XCHG
- T/h1 v T/h2 phi c cng kch c - T/h1 v T/h2 khng th ng thi thuc b nh - T/h1 v T/h2 khng th l cc thanh ghi segment
CC MODE A CH
- Khi thc hin lnh, VXL s thc hin nhng thao tc nht nh trn s liu, cc s liu ny c gi chung l cc ton hng. - Cc ton hng trong mt cu lnh c th l mt phn ca cu lnh ( dng m my), c th nm mt thanh ghi ca VXL hoc B nh -Cch xc nh ton hng trong cc cu lnh c gi l cc mode (nh) a ch
CC MODE A CH
- Mode a ch thanh ghi: MOV AX,BX - Mode a ch tc th: MOV AL,55h - Cc mode a ch b nh: Cc cch thc xc nh a ch vt l ca ton hng nm trong b nh: Mode a ch trc tip Cc mode a ch gin tip
NH CC MODE A CH B NH NH TH NO?
BP
CC V D
Instruction Comment Addressing Mode Register 89 D8 Memory Contents MOV AX, BX Move to AX the 16-bit value in BX
OP MODE
MOV AX, DI
Register
89 F8
OP
MODE
MOV AH, AL
Register
88 C4
OP
MODE
Immediate
B4 12
OP
DATA8
Immediate
B8 34
OP
DATA16
Immediate
B8 lsb msb
OP
DATA16
MOV AX, X
Immediate
B8 lsb msb
OP
DATA16
Direct
A1 34 12
OP
DISP16
Direct
A1 lsb msb
OP
DISP16
CC V D
Instruction Comment Move to the memory location pointed to by DS:X the value in AX Move to AX the 16-bit value pointed to by DS:DI Move to address DS:DI the 16-bit value in AX Move to AX the 16-bit value pointed to by DS:BX Move to the memory address DS:BX the 16-bit value stored in AX Move to memory address SS:BP the 16-bit value in AX Move to AX the value in memory at DS:BX + TAB Move value in AX to memory address DS:BX + TAB Move to AX the value in memory at DS:BX + DI Addressing Mode Memory Contents
MOV [X], AX
Direct
A3 lsb msb
OP
DATA16
Indexed
8B 05
OP
MODE
MOV [DI], AX
Indexed Register Indirect Register Indirect Register Indirect Register Relative Register Relative Base Plus Index
89 05
OP
MODE
8B 07
OP
MODE
MOV [BX], AX
89 07
OP
MODE
MOV [BP], AX
89 46
OP
MODE
8B 87 lsb msb
OP
MODE
DISP16
MOV TAB[BX], AX
89 87 lsb msb
OP
MODE
DISP16
8B 01
OP
MODE
CC V D
Addressing Mode
Instruction
Comment
Memory Contents
89 01
OP
MODE
8B 81 34 12
OP
MODE
DISP16
C7 81 34 12 78 56
M MY
Mt lnh c th di t1 n 6 byte Byte 1 gm: Opcode (6 bit) xc nh php ton cn thc hin Bit D xc nh ton hng REG ca Byte 2 l ngun hay ch: 1: ch
0: Ngun
Bit W xc nh kch c ca ton hng l 8 bit hay 16 bit 0: 8 bit
1: 16 bit
Byte 2 gm:Mode field (MOD), Register field (REG) Register/memory field (R/M field)
ANATOMY OF AN INSTRUCTION
Opcode
Mode
Displacement
Data/Immediate
D W
OPCODE
Opcode contains the type of instruction we execute plus two special bits, D and W The mode byte is used only in instructions that use register addressing modes and encodes the source and destination for instructions with two operands D stands for direction and defines the data flow of the instruction
MOD
REG
R/M
D=0, data flows from REG to R/M D=1, data flows from R/M to REG W=0, byte-sized data W=1, word (in real mode) or double-word sized (in protected mode)
Anatomy of an instruction
Opcode Mode Displacement Data/Immediate
D W
OPCODE
MOD field specifies the addressing mode 00 no displacement 01 8-bit displacement, sign extended 10 16-bit displacement 11 R/M is a register, register addressing mode If MOD is 00,01, or 10, the R/M field selects one of the memory addressing modes
MOD
REG
R/M
W=0 (Byte) AL CL DL BL AH CH DH BH
W=1 (Word) AX CX DX BX SP BP SI DI
W=1 (DWord) EAX ECX EDX EBX ESP EBP ESI EDI
EXAMPLE
Consider the instruction 8BECh 1000 1011 1110 1100 binary Opcode 100010 -> MOV D=1 data goes from R/M to REG W=1 data is word-sized MOD=11, register addressing REG=101 destination, R/M=100 source MOV BP, SP
W=0 AL CL
W=1 AX CX
010
011 100 101 110 111
DL
BL AH CH DH BH
DX
BX SP BP SI DI
EDX
EBX ESP EBP ESI EDI
DISPLACEMENT ADDRESSING
MOD 00 01 10 11
Examples: If MOD=00 and R/M=101 mode is [DI] If MOD=01 and R/M=101 mode is [DI+33h] If MODE=10 and R/M=101 modes is [DI+2233h]
111
DS:BX
EXAMPLE
W=0 AL CL
W=1 AX CX
Instruction 8A15h 1000 1010 0001 0101 Opcode 100010 -> MOV D=1, data flows from R/M to REG W=0, 8-bit argument MOD=00 (no displacement) REG=010 (DL) REG=101 ([DI] addressing mode) MOV DL, [DI]
010
011 100 101 110 111
DL
BL AH CH DH BH
DX
BX SP BP SI DI
EDX
EBX ESP EBP ESI EDI
R/M Code
000 001 010 011 100 101 110 111
Function
DS:BX+SI DS:BX+DI SS:BP+SI SS:BP+DI DS:SI DS:DI SS:BP DS:BX
DIRECT ADDRESSING
Example: 8816 00 10 1000 1000 0001 0110 0000 0000 0001 0000 Opcode 100010 -> MOV W=0 (byte-sized data) D=0 data flows from REG MOD 00, REG=010 (DL), R/M=110 Low-order byte of displacement 00 High-order byte of displacement 10 MOV [1000h], DL
Code 000 001 010 011 100 101 111 W=0 AL CL DL BL AH CH BH
W=1 AX CX DX BX SP BP
110
DH
SI
DI
ESI
EDI
Opcode 10001100
MOD=11 (register addressing) REG=001 (CS) R/M=011 (BX) 8CCB
M MY
REG xc nh thanh ghi cho ton hng th nht
M MY
MOD v R/M cng nhau xc nh ton hng th hai
M MY
MOD v R/M cng nhau xc nh ton hng th hai
V D
M ho lnh MOV
BL,AL
Opcode i vi MOV l 100010 Ta m ho AL sao cho AL l ton hng ngun: D = 0 (AL l ton hng ngun) W bit = 0 (8-bit) MOD = 11 (register mode) REG = 000 (m ca AL)
NHM LNH S HC
Bn cnh tc dng, cn ch n nh hng ca lnh i vi cc c trng thi Cc lnh s hc th/thng: ADD, SUB, Cc lnh s hc khc: CMP. NEG, INC, DEC, nh hng n cc c trng thi
CF OF AF
Ngun: c th l:
NH HNG CA ADD
CF c lp nu trn khng du (c nh t MSB) OF c lp nu trn c du: - C nh t MSB, Khng c nh vo MSB - C nh vo MSB, Khng c nh t MSB AF c lp nu c nh t nibble thp vo nibble cao (t bit 3 vo bit 4)
Cc bit nht nh trn thanh ghi c iu khin hot ng hoc phn nh trng thi ca vi x l
Cc
c iu khin (TF, IF, DF) c trng thi (CF, PF, AF, ZF, SF, OF)
Quyt
Cc
B
CC C IU KHIN
TF - Trace flag
TF
CC C TRNG THI
Carry
Zero
result is 0
result is negative signed overflow occurred during add or subtract
Sign
Parity
Overflow
Auxiliary
(SIGNED) OVERFLOW
Can only occur when adding numbers of the same sign (subtracting with different signs) Detected when carry into MSB is not equal to carry out of MSB
Easily
detected because this implies the result has a different sign than the sign of the operands
UNSIGNED OVERFLOW
The carry flag is used to indicate if an unsigned operation overflowed The processor only adds or subtracts - it does not care if the data is signed or unsigned!
Ngun: c th l:
NH HNG CA SUB
CF c lp nu trn khng du (c mn vo MSB) OF c lp nu trn c du: - C mn t MSB, Khng c mn t MSB - C mn t MSB, Khng c mn vo MSB AF c lp nu c mn t nibble cao vo nibble thp (t bit 4 vo bit 3)
Ngun: c th l:
MT S V D
AL 1100 1010 NOT AL AL 0011 0101 AL 0011 0101 BL 0110 1101 AND AL, BL AL 0010 0101 AL 0011 0101 BL 0000 1111 AND AL, BL AL 0000 0101 AL BL 0011 0101 0110 1101 OR AL, BL AL 0111 1101 AL BL 0011 0101 0000 1111 OR AL, BL AL 0011 1111 AL 0011 0101 BL 0110 1101 XOR AL, BL AL 0101 1000
MT S NG DNG
Bi ton Xo bit: Xo mt bit no ca mt ton hng m khng lm nh hng n cc bit cn li ca ton hng Bi ton Kim tra bit: Xc nh mt bit no ca mt ton hng l bng 0 hay 1 (thng qua gi tr ca mt c trng thi) Bi ton Lp bit: Lp mt bit no ca mt ton hng m khng lm nh hng n cc bit cn li ca ton hng
Cc lnh logic khc: Lnh TEST, Cc lnh dch (Shift) v Cc lnh quay (Rotate) Lnh TEST ch khc lnh AND l khng gi li kt qu ca php ton Cc lnh dch v Cc lnh quay u c hai khun dng: Khun dng 1: Mnemonic Ton hng,1 Khun dng 2: Mnemonic Ton hng,CL Tc dng ca mt cu lnh theo khun dang 2 ging nh tc dng lin tip ca N cu lnh tng ng theo khun dng 1, vi N l gi tr ca thanh ghi CL
CF
Register 0
Register
CF
Register
CF
RCR
ROL
ROR
JMP nhn
Nhy gn: E9 xx xx (3 byte) Nhy ngn: EB xx (2 byte) Nhy xa: EA xx xx xx xx (5 byte) Nhn: tn do ngI lp trnh t t ra theo qui tc t tn ca Assembler v c th t vo trc mt cu lnh bt k trong chng trnh cng vi du :
Nhn s c dch thnh a ch Khong cch nhy: Khong cch i s (c du) t lnh nhy n lnh cn thc hin
Lnh nhy ngn cng khong cch nhy 8-bit c du vo gi tr hin thi ca IP Lnh nhy gn cng khong cch nhy 16-bit c du vo gi tr hin thi ca IP
cho CS v IP cc gi tr mi
M MY CA LNH NHY
1106:0100 EB2A JMP 012C 012C-0102=002A 1106:0102 EBFC JMP 0100 0100-0104=FFFC 1106:0104 E97F00 JMP 0186 0186-0106=0080 (too far for short!) 0186-0107=007F 1106:0107 E9F5FE JMP FFFF FFFF-010A=FEF5
Jxxx nhn
Cc lnh nhy iu kin n: ph thuc vo gi tr ca 1 c. JNZ/JNE - Nhy nu c ZF = 0, ngha l kt qu ca php ton trc khc khng JC - Nhy nu CF = 1, ngha l cu lnh trc lp c carry JZ/JE JNC
T hp vi lnh nhy khng iu kin c th vt qua gii hn ny. Cc lnh nhy iu kin kp: ph thuc vo gi tr ca nhiu c JB/JNAE JNL/JGE
CMP TEST
CU TRC IU KIN
mov ax,n cmp ax,7 jz nhan1 lnh 1 jmp nhan2 nhan1:lnh 2 nhan2:lnh 3
CU TRC LP
mov ax,n
nhan1: cmp ax,0 jz nhan2 lnhi sub ax,2 jmp nhan1 nhan2: lnhk
CU TRC IU KIN - OR
char n,k; unsigned int w; if (n<>k || w<=10) whatever();
;if(n<>k||w<=10) mov ah,n cmp ah,k jne then_ cmp w,10 ja end_if then_: call whatever end_if:
LNH LOOP
LOOP nhan
Gim CX i 1 Nu (CX) <> 0 th JMP nhan. Nu khng th tip tc thc hin lnh theo trt t bnh thng
LOOPZ/E V LOOPNZ/E
Cc bin th ca LOOP Gi tr ca c ZF c th lm kt thc sm vng lp Loop while ZF/equal && CX!=0 Loop while (NZ/ not equal) && CX!=0
Lu : LOOP gim CX nhng khng nh hung n cc c LOOPZ == LOOPE LOOPNZ==LOOPNE Cc lnh trong vng lp c th tc ng n c ZF (CMP ?)
STACK ?
(SS:SP) tr n nh ca stack (SS:BP) truy cp stack ngu nhin (khng theo LIFO)
STACK INITIALIZATION
The .stack directive hides an array allocation statement that looks like this
The_Stack
DB
On program load
SS
is set to a segment address containing this array (usually The_Stack starts at offset 0) SP is set to the offset of The_Stack+Stack_Size which is one byte past the end of the stack array
This
is an empty stack
Stack Size: 000C
SS:0340
SP:000C
The stack grows backwards through memory towards the start of the stack segment
Stack Size: 000C
Push decrements stack pointer SS:0340 Pop increments stack pointer SP:0008
PUSH
PUSH ngun
Push
ngun vo stack
thanh ghi c vo stack
PUSHF
Push
V D PUSH
Stack Size: 000C
3C 09 A4 40 2C FF A2 43 07 06 4C 2A 09 46
SS:0340
SP:0008
PUSH AX
AX: 0123
3C 09 A4 40 2C FF A2 23 01 06 4C 2A 09 46
SS:0340
SP:0006
POP
POP ch
Pop
d liu t nh stack vo ch
d liu t nh stack vo thanh ghi c
POPF
Pop
V D POP
3C 09 A4 40 2C FF A2 23 01 06 4C 2A 09 46
SS:0340
SP:0006
POP ES
3C 09 A4 40 2C FF A2 23 01 06 4C 2A 09 46
SS:0340
ES: 0123
SP:0008
TRN STACK!
Stack Size: 000C
SS:0340
SP:FFFE
SS:0340
SP:000D
TH TC
Tn_Th_tc PROC kiu ;thn ca th tc RET ;quay v chung trnh gi Tn_Th_tc ENDP
nh l NEAR
Tr v t mt th tc (NEAR) RET
pop
gi tr nh stack vo IP
TH TC FAR
Tr v t th tc (FAR) RET
pop
gi tr t nh stack ln lt vo IP v CS
GI NGT
Gi ngt l mt li gi th tc c bit
FAR Thanh ghi c phi c bo ton Thanh ghi c c push, TF v IF b xo CS v rI IP c push a ch ca mt chng trnh con phc v ngt (Vector ngt) tng ng vi S ngt c copy vo CS v IP
INT S ngt
TR V T NGT
XUT K T RA MN HNH PC
Ngt 21h
Ngt ny h tr rt nhiu dch v trn PC Nhn dng dch v bng s dch v (s hm). S dch v cn c np vo thanh ghi AH Tu theo tng dch v, c th cn thm mt s i s khc c np vo cc thanh ghi xc nh
K t c hin th ti v tr hin thI ca con tr
AH = 2, DL = M ASCII ca k t cn xut
XUT XU K T RA MN HNH PC
NHP 1 K T T BN PHM PC
Dch v 01h ca ngt 21h Khi NSD g mt k t t bn phm:
nu k t c nhp l k t iu khin
Sao
CC C IM
MOVSB, MOVSW
Chuyn
REP
V D: TNH TIN CC NH
mov mov mov std rep cx, 7 di, offset a+9 si, offset a+6 ;lp c DF movsb
SI DI
V D
pattern mov mov mov cld rep
SI
db "!@#*" db 96 dup (?) cx,96 si, offset pattern di, offset pattern+4 movsb
DI
! @ # * a
LU TR STRING
STOSB, STOSW Copy AL hoc AX vo mt mng byte hoc word
ch (ES:DI)
ph thuc DF
V D:
arr dw 200 dup (?) mov ax,50A0h mov di,offset arr mov cx,200 cld rep stosw AX 50 A0
A0 50 A0 50 arr
DI
NP STRING
LODSB, LODSW
Byte
hoc word ti (DS:SI) c copy vo AL hoc AX SI tng hoc gim 1 hoc 2 gi tr ph thuc DF
V D:
mov di, offset b mov si, offset a mov cx,30 cld lp: lodsb and al,0DFh stosb loop lp
QUT STRING
SCASB, SCASW So snh AL hoc AX vi byte hoc word tI (ES:DI) v t ng tng hoc gim DI Lnh ny nh hng n cc c trng thi
Tu
V D
arr db 'abcdefghijklmnopqrstuvwxyz' mov di, offset arr mov cx,26 cld mov al,target repne scasb jne nomatch
SO SNH STRING
CMPSB, CMPSW So snh byte hoc word ti (DS:SI) vi byte hoc word tI (ES:DI), tc ng n cc c v tng hoc gim SI v DI Thng dng so snh hai mng vi nhau
V D
mov si, offset str1 mov di, offset str2 cld mov cx, 12 repe cmpsb jl str1smaller jg str2smaller ;the strings are equal - so far ;if sizes different, shorter string is less
NHM LNH HN HP
- Cc lnh Lp/Xo trc tip cc c:
STC, CLC STD, CLD STI, CLI - Lnh NOP (No Operation): Khng lm g!!! - Lnh NOP thng c dng trong cc vng lp to tr (delay)bng phn mm - Cc lnh Nhp/Xut d liu i vi cc cng I/O IN OUT
LNH IN
- Nu a ch ca cng Nh hn hoc bng FFh: IN Acc, a ch cng - Trong : Acc c th l AL hoc AX - Nhp d liu t cng vo Acc - Nu a ch ca cng Ln hn FFh: MOV DX, a ch cng IN Acc, DX - Trong : Acc c th l AL hoc AX - Nhp d liu t cng vo Acc
LNH OUT
- Nu a ch ca cng Nh hn hoc bng FFh: OUT a ch cng, Acc - Trong : Acc c th l AL hoc AX - Xut d liu t Acc ra cng - Nu a ch ca cng Ln hn FFh: MOV DX, a ch cng OUT DX, Acc - Trong : Acc c th l AL hoc AX - Xut d liu t Acc ra cng
TM TT CHNG
- Tnh tng thch v Cu trc thanh ghi ca cc vi x l h x86 - Tnh tng thch v Tp lnh ca cc vi x l h x86