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    Shifo Maher
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    Copyright:

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    Download as TXT, PDF, TXT or read online from Scribd
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    4 views1 page

    Verilog

    Uploaded by

    Shifo Maher

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as txt, pdf, or txt
    of 1

    module smpl_circuit(A,B,C,x,y); input A,B,C; wire e; output x,y; and g1 (e,,A,B); not g2 (y,C); or g3 (x,e,y); endmodule

    http://www.a-mot.com/vb/t117922.html

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