Thumb Instruction Set Quick Reference Card

Key to Tables <loreglist> A comma-separated list of Lo registers, enclosed in braces, { and }. <loreglist+LR> <loreglist+PC> A comma-separated list of Lo registers. plus the LR, enclosed in braces, { and }. A comma-separated list of Lo registers. plus the PC, enclosed in braces, { and }.

All Thumb registers are Lo (R0-R7) except where specified. Hi registers are R8-R15. Operation Move Assembler MOV Rd, #<immed> MOV Rd, Rm MOV Rd, Rm 6 CPY Rd, Rm ADD Rd, Rn, #<immed> ADD Rd, Rn, Rm ADD Rd, Rm ADD Rd, #<immed> ADC Rd, Rm ADD SP, #<immed> ADD Rd, SP, #<immed> ADD Rd, PC, #<immed> SUB Rd, Rn, Rm SUB Rd, Rn, #<immed> SUB Rd, #<immed> SBC Rd, Rm SUB SP, #<immed> NEG Rd, Rm MUL Rd, Rm CMP CMN CMP NOP AND EOR ORR BIC MVN TST LSL LSL LSR LSR ASR ASR ROR 6 REV Rn, Rm Rn, Rm Rn, #<immed> Rd, Rd, Rd, Rd, Rd, Rn, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rm Rm Rm Rm Rm Rm Rm, #<shift> Rs Rm, #<shift> Rs Rm, #<shift> Rs Rs Rm Updates Action N Z Rd := immed N Z * * Rd := Rm Rd := Rm Rd := Rm N Z C V Rd := Rn + immed N Z C V Rd := Rn + Rm Rd := Rd + Rm N Z C V Rd := Rd + immed N Z C V Rd := Rd + Rm + C-bit R13 := R13 + immed Rd := R13 + immed Rd := (R15 AND 0xFFFFFFFC) + immed N Z C V Rd := Rn Rm N Z C V Rd := Rn immed N Z C V Rd := Rd immed N Z C V Rd := Rd Rm NOT C-bit R13 := R13 immed N Z C V Rd := Rm N Z * * Rd := Rm * Rd N Z C V update CPSR flags on Rn Rm N Z C V update CPSR flags on Rn + Rm N Z C V update CPSR flags on Rn immed None N Z Rd := Rd AND Rm N Z Rd := Rd EOR Rm N Z Rd := Rd OR Rm N Z Rd := Rd AND NOT Rm N Z Rd := NOT Rm N Z update CPSR flags on Rn AND Rm N Z C* Rd := Rm << shift N Z C* Rd := Rd << Rs[7:0] N Z C Rd := Rm >> shift N Z C Rd := Rd >> Rs[7:0] N Z C Rd := Rm ASR shift N Z C* Rd := Rd ASR Rs[7:0] N Z C* Rd := Rd ROR Rs[7:0] Rd[31:24] := Rm[7:0], Rd[23:16] := Rm[15:8], Rd[15:8] := Rm[23:16], Rd[7:0] := Rm[31:24] Rd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:24] := Rm[23:16], Rd[23:16] := Rm[31:24] Rd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:16] := Rm[7] * &FFFF Notes Immediate range 0-255. * Clears C and V flags. Not Lo to Lo. Flags not affected. Any register to any register. Flags not affected. Immediate range 0-7. Not Lo to Lo. Flags not affected. Immediate range 0-255. Immediate range 0-508 (word-aligned). Flags not affected. Immediate range 0-1020 (word-aligned). Flags not affected. Immediate range 0-1020 (word-aligned). Flags not affected. Immediate range 0-7. Immediate range 0-255. Immediate range 0-508 (word-aligned). Flags not affected. * C and V flags unpredictable in 4T, unchanged in 5T and above Can be Lo to Lo, Lo to Hi, Hi to Lo, or Hi to Hi. Immediate range 0-255. Flags not affected.

Arithmetic

Immediate Lo to Lo Hi to Lo, Lo to Hi, Hi to Hi Copy Any to Any Add Lo and Lo Hi to Lo, Lo to Hi, Hi to Hi immediate with carry value to SP form address from SP form address from PC Subtract immediate 3 immediate 8 with carry value from SP Negate Multiply

Compare negative immediate No operation Logical AND Exclusive OR OR Bit clear Move NOT Test bits Shift/rotate Logical shift left Logical shift right Arithmetic shift right Rotate right Bytes in word Bytes in both halfwords Bytes in low halfword, sign extend

Allowed shifts 0-31. * C flag unaffected if shift is 0. * C flag unaffected if Rs[7:0] is 0. Allowed shifts 1-32. * C flag unaffected if Rs[7:0] is 0. Allowed shifts 1-32. * C flag unaffected if Rs[7:0] is 0. * C flag unaffected if Rs[7:0] is 0.

Reverse

6 REV16 Rd, Rm 6 REVSH Rd, Rm

Operation Load with immediate offset, word halfword byte with register offset, word halfword signed halfword byte signed byte PC-relative SP-relative Multiple Store with immediate offset, word halfword byte with register offset, word halfword byte SP-relative, word Multiple Push/ Push Pop Push with link Pop Pop and return Pop and return with exchange Branch Conditional branch Unconditional branch Long branch with link Branch and exchange Branch with link and exchange Branch with link and exchange Extend Signed extend halfword to word Signed extend byte to word Unsigned extend halfword to word Unsigned extend byte to word Processor Software interrupt state Change processor state change Set endianness Breakpoint

Assembler LDR Rd, [Rn, #<immed>] LDRH Rd, [Rn, #<immed>] LDRB Rd, [Rn, #<immed>] LDR Rd, [Rn, Rm] LDRH Rd, [Rn, Rm] LDRSH Rd, [Rn, Rm] LDRB Rd, [Rn, Rm] LDRSB Rd, [Rn, Rm] LDR Rd, [PC, #<immed>] LDR Rd, [SP, #<immed>] LDMIA Rn!, <reglist> STR Rd, [Rn, #<immed>] STRH Rd, [Rn, #<immed>] STRB Rd, [Rn, #<immed>] STR Rd, [Rn, Rm] STRH Rd, [Rn, Rm] STRB Rd, [Rn, Rm] STR Rd, [SP, #<immed>] STMIA Rn!, <reglist> PUSH <loreglist> PUSH <loreglist+LR> POP <loreglist> 4T POP <loreglist+PC> 5T POP <loreglist+PC> B{cond} label B label BL label BX Rm 5T BLX label 5T BLX Rm 6 6 6 6 6 6 6 5T SXTH Rd, Rm SXTB Rd, Rm UXTH Rd, Rm UXTB Rd, Rm SWI <immed_8> CPSID <iflags> CPSIE <iflags> SETEND <endianness> BKPT <immed_8>

Action Rd := [Rn + immed] Rd := ZeroExtend([Rn + immed][15:0]) Rd := ZeroExtend([Rn + immed][7:0]) Rd := [Rn + Rm] Rd := ZeroExtend([Rn + Rm][15:0]) Rd := SignExtend([Rn + Rm][15:0]) Rd := ZeroExtend([Rn + Rm][7:0]) Rd := SignExtend([Rn + Rm][7:0]) Rd := [(R15 AND 0xFFFFFFFC) + immed] Rd := [R13 + immed] Loads list of registers [Rn + immed] := Rd [Rn + immed][15:0] := Rd[15:0] [Rn + immed][7:0] := Rd[7:0] [Rn + Rm] := Rd [Rn + Rm][15:0] := Rd[15:0] [Rn + Rm][7:0] := Rd[7:0] [R13 + immed] := Rd Stores list of registers Push registers onto stack Push LR and registers onto stack Pop registers from stack Pop registers, branch to address loaded to PC Pop, branch, and change to ARM state if address[0] = 0 R15 := label R15 := label R14 := address of next instruction, R15 := label R15 := Rm AND 0xFFFFFFFE R14 := address of next instruction, R15 := label Change to ARM R14 := address of next instruction, R15 := Rm AND 0xFFFFFFFE Rd[31:0] := SignExtend(Rm[15:0]) Rd[31:0] := SignExtend(Rm[7:0]) Rd[31:0] := ZeroExtend(Rm[15:0]) Rd[31:0] := ZeroExtend(Rm[7:0]) Software interrupt processor exception Disable specified interrups Enable specified interrups Sets endianness for loads and saves. Prefetch abort or enter debug state

Notes Immediate range 0-124, multiple of 4. Clears bits 31:16. Immediate range 0-62, even. Clears bits 31:8. Immediate range 0-31. Clears bits 31:16 Sets bits 31:16 to bit 15 Clears bits 31:8 Sets bits 31:8 to bit 7 Immediate range 0-1020, multiple of 4. Immediate range 0-1020, multiple of 4. Always updates base register. Immediate range 0-124, multiple of 4. Ignores Rd[31:16]. Immediate range 0-62, even. Ignores Rd[31:8]. Immediate range 0-31. Ignores Rd[31:16] Ignores Rd[31:8] Immediate range 0-1020, multiple of 4. Always updates base register. Full descending stack.

label must be within 252 to + 258 bytes of current instruction. See Table Condition Field on reverse. label must be within 2Kb of current instruction. Encoded as two Thumb instructions. label must be within 4Mb of current instruction. Change to ARM state if Rm[0] = 0. Encoded as two Thumb instructions. label must be within 4Mb of current instruction. Change to ARM state if Rm[0] = 0

8-bit immediate value encoded in instruction.

<endianness> can be BE (Big Endian) or LE (Little Endian). 8-bit immediate value encoded in instruction.

Thumb Instruction Set Quick Reference Card

Vector Floating Point Instruction Set Quick Reference Card

Key to Tables {cond} <S/D> <S/D/X> <VFPsysreg> See Table Condition Field S (single precision) or D (double precision). As above, or X (unspecified precision). FPSCR, or FPSID. Fd, Fn, Fm {E} {Z} <VFPregs> Sd, Sn, Sm (single precision), or Dd, Dn, Dm (double precision). E : raise exception on any NaN. Without E : raise exception only on signaling NaNs. Round towards zero. Overrides FPSCR rounding mode. A comma separated list of consecutive VFP registers, enclosed in braces ( { and } ). Action Notes Fd := Fn * Fm Fd := (Fn * Fm) Fd := Fd + (Fn * Fm) Fd := Fd (Fn * Fm) Exceptions Fd := Fd + (Fn * Fm) IO Invalid operation Fd := Fd (Fn * Fm) OF Overflow Fd := Fn + Fm UF Underflow Fd := Fn Fm IX Inexact result Fd := Fn / Fm DZ Division by zero Fd := Fm Fd := abs(Fm) Fd := Fm Fd := sqrt(Fm) Set FPSCR flags on Fd Fm Use FMSTAT to transfer flags. Set FPSCR flags on Fd 0 Use FMSTAT to transfer flags. Dd := convertStoD(Sm) Sd := convertDtoS(Dm) Fd := convertUItoF(Sm) Fd := convertSItoF(Sm) Sd := convertFtoUI(Fm) Sd := convertFtoSI(Fm) [address] := Fd. Immediate range 0-1020, multiple of 4. Saves list of VFP registers, starting at address in Rn. synonym: FSTMEA (empty ascending) synonym: FSTMFD (full descending) Fd := [address]. Immediate range 0-1020, multiple of 4. Loads list of VFP registers, starting at address in Rn. synonym: FLDMFD (full descending) synonym: FLDMEA (empty ascending) Sn := Rd Rd := Sn Sn := Rd, Sm := Rn Architecture VFPv2 only Rd := Sn, Rn := Sm Architecture VFPv2 only Dn[31:0] := Rd, Dn[63:32] := Rn Architecture VFPv2 only Rd := Dn[31:0], Rn := Dn[63:32] Architecture VFPv2 only Dn[31:0] := Rd Use with FMDHR. Rd := Dn[31:0] Use with FMRDH. Dn[63:32] := Rd Use with FMDLR. Rd := Dn[63:32] Use with FMRDL. VFPsysreg := Rd Stalls ARM until all VFP ops complete. Rd := VFPsysreg Stalls ARM until all VFP ops complete. CPSR flags := FPSCR flags Equivalent to FMRX R15, FPSCR

Operation Vector arithmetic

Scalar compare Scalar convert

Multiply and negate and accumulate negate and accumulate and subtract negate and subtract Add Subtract Divide Copy Absolute Negative Square root Two values Value with zero Single to double Double to single Unsigned integer to float Signed integer to float Float to unsigned integer Float to signed integer Multiple, unindexed increment after decrement before

Save VFP registers

Load VFP registers Multiple, unindexed increment after decrement before ARM to single Single to ARM Two ARM to two singles Two singles to two ARM Two ARM to double Double to two ARM ARM to lower half of double Lower half of double to ARM ARM to upper half of double Upper half of double to ARM ARM to VFP system register VFP system register to ARM FPSCR flags to CPSR

Transfer registers

Assembler FMUL<S/D>{cond} Fd, Fn, Fm FNMUL<S/D>{cond} Fd, Fn, Fm FMAC<S/D>{cond} Fd, Fn, Fm FNMAC<S/D>{cond} Fd, Fn, Fm FMSC<S/D>{cond} Fd, Fn, Fm FNMSC<S/D>{cond} Fd, Fn, Fm FADD<S/D>{cond} Fd, Fn, Fm FSUB<S/D>{cond} Fd, Fn, Fm FDIV<S/D>{cond} Fd, Fn, Fm FCPY<S/D>{cond} Fd, Fm FABS<S/D>{cond} Fd, Fm FNEG<S/D>{cond} Fd, Fm FSQRT<S/D>{cond} Fd, Fm FCMP{E}<S/D>{cond} Fd, Fm FCMP{E}Z<S/D>{cond} Fd FCVTDS{cond} Dd, Sm FCVTSD{cond} Sd, Dm FUITO<S/D>{cond} Fd, Sm FSITO<S/D>{cond} Fd, Sm FTOUI{Z}<S/D>{cond} Sd, Fm FTOSI{Z}<S/D>{cond} Sd, Fm FST<S/D>{cond} Fd, [Rn{, #<immed>}] FSTMIA<S/D/X>{cond} Rn, <VFPregs> FSTMIA<S/D/X>{cond} Rn!, <VFPregs> FSTMDB<S/D/X>{cond} Rn!, <VFPregs> FLD<S/D>{cond} Fd, [Rn{, #<immed>}] FLDMIA<S/D/X>{cond} Rn, <VFPregs> FLDMIA<S/D/X>{cond} Rn!, <VFPregs> FLDMDB<S/D/X>{cond} Rn!, <VFPregs> FMSR{cond} Sn, Rd FMRS{cond} Rd, Sn FMSRR{cond} {Sn,Sm}, Rd, Rn FMRRS{cond} Rd, Rn, {Sn,Sm} FMDRR{cond} Dn, Rd, Rn FMRRD{cond} Rd, Rn, Dn FMDLR{cond} Dn, Rd FMRDL{cond} Rd, Dn FMDHR{cond} Dn, Rd FMRDH{cond} Rd, Dn FMXR{cond} <VFPsysreg>, Rd FMRX{cond} Rd, <VFPsysreg> FMSTAT{cond}

Exceptions IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, IX IO, OF, IX IO, DZ, OF, UF, IX

IO, IX IO IO IO IO, OF, UF, IX IX IX IO, IX IO, IX

Vector Floating Point Instruction Set Quick Reference Card

FPSCR format 31 30 29 28 N Z C V FZ: 1 = flush to zero mode. Rounding (Stride 1)*3 Vector length 1 24 23 22 21 20 18 17 16 FZ RMODE STRIDE LEN Rounding: 0 = round to nearest, 1 = towards + 2 = towards , 3 = towards zero. , 12 IXE Exception trap enable bits Cumulative exception bits 11 10 9 8 4 3 2 1 0 UFE OFE DZE IOE IXC UFC OFC DZC IOC (Vector length * Stride) must not exceed 4 for double precision operands.

If Fd is S0-S7 or D0-D3, operation is Scalar (regardless of vector length). If Fd is S8-S31 or D4-D15, and Fm is S8-S31 or D4-D15, operation is Vector.

If Fd is S8-S31 or D4-D15, and Fm is S0-S7 or D0-D3, operation is Mixed (Fm scalar, others vector). S0-S7 (or D0-D3), S8-S15 (D4-D7), S16-S23 (D8-D11), S24-S31 (D12-D15) each form a circulating bank of registers.

Condition Field Mnemonic Description (Thumb) EQ Equal NE Not equal CS / HS Carry Set / Unsigned higher or same CC / LO Carry Clear / Unsigned lower MI Negative PL Positive or zero VS Overflow VC No overflow HI Unsigned higher LS Unsigned lower or same GE Signed greater than or equal LT Signed less than GT Signed greater than LE Signed less than or equal AL Do not use in Thumb Exceptions IO Invalid operation OF Overflow UF Underflow IX Inexact result DZ Division by zero

Description (VFP) Equal Not equal, or unordered Greater than or equal, or unordered Less than Less than Greater than or equal, or unordered Unordered (at least one NaN operand) Not unordered Greater than, or unordered Less than or equal Greater than or equal Less than, or unordered Greater than Less than or equal, or unordered Always (normally omitted)

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Document Number
ARM QRC 0001H

Change Log
Issue A B C D E F G H Date June 1995 Sept 1996 Nov 1998 Oct 1999 Oct 2000 Sept 2001 Jan 2003 Oct 2003 By BJH BJH BJH CKS CKS CKS CKS CKS Change First Release Second Release Third Release Fourth Release Fifth Release Sixth Release Seventh Release Eighth Release

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