2440

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

1-V DTMOS-Based Class-AB Operational Amplier: Implementation and Experimental Results

Herv Facpong Achigui, Student Member, IEEE, Christian Jsus B. Fayomi, Member, IEEE, and Mohamad Sawan, Fellow, IEEE

AbstractIn this paper, we describe a novel low-voltage class-AB operational amplier (opamp) based on dynamic threshold voltage MOS transistors (DTMOS). A DTMOS transistor is a device whose gate is tied to its bulk. DTMOS transistor pseudo-pMOS differential input pairs are used for input common-mode range enhancement, followed by a single ended class-AB output. Two versions of the proposed opamp (opamp-A and opamp-B) were fabricated in a standard 0.18- m CMOS process technology. Measurements under 5 pF and 10 k load conditions gave, for opamp-A, a DC open-loop gain of 50.1 dB, and a unity gain bandwidth (GBW) of 26.2 MHz. A common-mode rejection ratio (CMRR) of 78 dB, and input and output swings of 0.7 V and 0.9 V, respectively, were achieved. Opamp-B has been optimized for biomedical applications, and is implemented to build the analog front-end part of a near-infrared spectroreectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. A DC open-loop gain of 53 dB, a GBW of 1.3 MHz, and input and output swings of 0.6 V and 0.8 V, respectively, were measured. Opamp-A consumes 550 W with an input referred noise of 160 nV Hz at 1 kHz. Opamp-B consumes only 40 W and exhibits a lower input referred noise of 107 nV Hz at 1 kHz.

Index TermsCMOS analog integrated circuit, differential amplier, DTMOS, low-voltage operational amplier.

I. INTRODUCTION

ESIGN of high-performance analog IC circuits operating at low supply voltages has been gaining increasing importance in the last decade, especially for applications such as medical electronic implantable devices, as well as handheld and battery-powered electronic devices. Furthermore, the increasing use of mobile electronic products has directed the industry towards reducing dissipated power, especially for analog and mixed signal circuits. In addition, large-scale integrations are predicted to target 1-V operation, and even less [1]. However, the trend towards lowering the power supply voltage of circuitries in mixed-signal (digital/analog) environments often sacrices the speed, noise requirements, dynamic range,

Manuscript received October 13, 2005; revised June 8, 2006. This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC), the Microsystems Research Alliance of Quebec (ReSMiQ), and CMC Microsystems. H. F. Achigui was with the Polystim Neurotechnologies Laboratory, Electrical Engineering Department, Ecole Polytechnique de Montreal, Montreal, QC H3C 3A7 Canada. He is now with PMC-Sierra, Mont-Royal, QC H3R 3L5 Canada (e-mail: herve.achigui-facpong@polymtl.ca). M. Sawan is with the Polystim Neurotechnologies Laboratory, Electrical Engineering Department, Ecole Polytechnique de Montreal, Montreal, QC H3C 3A7 Canada (e-mail: mohamad.sawan@polymtl.ca). C. J. B. Fayomi is with the Microelectronics Laboratory, Computer Science Department, Universit du Qubec Montral, Montreal, QC H2X 3Y7 Canada (e-mail: cfayomi@ieee.org). Digital Object Identier 10.1109/JSSC.2006.883341

gain, bandwidth, and linearity of their analog counterparts. This poses a great challenge to circuit design. is necessary for The reduction of threshold voltage low-voltage operation; on the other hand, the threshold voltage does not scale down with the supply voltage of future standard CMOS technologies [2]. An obvious solution could be the use of multi-process threshold technology, but unfortunately, this kind of technology is more expensive and frequently not easy to reproduce. Some additional design advantages, such as low-noise structures, could be obtained by using BiCMOS technology, but at a higher cost. Several design techniques have been proposed for the implementation of 1-V operational ampliers (opamps); in fact, some authors reported circuit techniques for facilitating 1-V operation based on bulk-driving architectures [3][5]. However, substantially small input is obtained when compared to a contransconductance ventional gate-driven MOS transistor, and furthermore, the equivalent input referred noise is larger. Other circuit topologies using a standard CMOS technology process were reported, [6][13]. The major drawback of the architectures based on N-P complementary rail-to-rail input stage [7], [8], is the increase in the total harmonic distortion (THD) related to the use of N-P complementary transistors, which produces an offset voltage on the common-mode input voltage swing. Since the introduction of dynamic threshold voltage MOSFET (DTMOS) in 1994 [14], several low-supply voltage circuits have been proposed, but most of them achieved low threshold voltage by modifying the fabrication process, using the SOI technology [15], or by using multiple-input oating-gate transistors [16]. In single well process technology, a DTMOS transistor is made of only a pMOS transistor by connecting its gate to the bulk, no further manufacturing process or step is required, and the device can be used in any standard CMOS process. This would result in a partial forward bias of the source-to-bulk PN junction leading to a reduced threshold voltage as the gate input voltage changes with little drawback effects as the forward bias voltage is kept below 0.7 V for modern submicron technology [17]. In this paper, novel class-AB opamps for low-voltage, as well as low-power and low-noise applications have been fabricated and tested. The circuits make use of the DTMOS folded cascode differential input pairs to increase the input common-mode range (ICMR). Standard Miller compensation is used for bandwidth enhancement. Section II describes the opamp architecture, with a focus on the DTMOS transistor operation and measurements. Experimental results are reported in Section III along with the effectiveness of the proposed solution for the design of low-voltage low-power analog circuits.

0018-9200/$20.00 2006 IEEE

ACHIGUI et al.: 1-V DTMOS-BASED CLASS-AB OPERATIONAL AMPLIFIER: IMPLEMENTATION AND EXPERIMENTAL RESULTS

2441

TABLE I TRENDS IN LOW-VOLTAGE CMOS OPAMP

II. LOW-VOLTAGE DTMOS-BASED OPAMP Various methods have been used to design opamps under low-voltage operation. Table I gives a simplied overview of the methods used to overcome the main limitations when implementing 1-V opamp designs, along with their related performances. The proposed implementation makes use of DTMOS transistors. We have achieved an average threshold voltage of 0.35 V for pMOS-based DTMOS transistors, compared to 0.55 V for regular pMOS devices. Such threshold voltage shift is similar to value obtained when using forward-biased source-bulk junction design technique [18]. The opamp consists of a differential input stage and a class-AB output stage capable of driving off chip resistive load as described in the block diagram of Fig. 1(a). The biasing circuit consists of a standard current source using a resistor and an nMOS transistor. A wide-swing current mirror with high and output impedance is used to produce bias voltages as shown in Fig. 1(b), (c), and (d). A. DTMOS Transistor A DTMOS transistor is a device whose gate is tied to its substrate. Therefore, the device can be seen either as a lateral bipolar p-n-p, or as pMOS with a dynamically regulated threshold. Consequently, the substrate voltage in DTMOS to change changes with the gate input voltage, and causes accordingly, as demonstrated in (1): (1)

is the zero bias threshold voltage, the bulk where the Fermi potential. With the use of effect factor, and standard digital technology, we can only implement p-type DTMOS, as their n-well can be controlled. When the input voltage at the gate of a pseudo-pMOS-based DTMOS transistor is high, the transistor turns to the off-state, and presents the , off-current , and subthreshold slope as a regular same pMOS. When the input voltage decreases, the transistor is in is its on-state, and the bulk-to-source junction voltage of the DTMOS transistor forward biased and thus reduces thanks to the body effect, resulting in a higher source-to-drain than that of regular pMOS. This phenomenon current enables us to take advantage of the maximum input range, and makes the DTMOS transistor the choice for subthreshold operation logic, without the need for any extra area [19], [20]. In addition, due to its gate-to-body tied structure, DTMOS operating in the subthreshold region exhibit similar characteristics to a lateral bipolar p-n-p transistor, without requiring its relatively large base current to operate, and having lower icker noise than regular MOS [20]. B. Input Stage Design We recently proposed two folded cascode class-AB opamp architectures [19], [20] which are illustrated in Fig. 1(b) and (c). Typically, pMOS threshold voltage is much larger than that of nMOS; consequently, to achieve 1-V operation or less, we used in the differpMOS-based DTMOS transistor pairs ential input. In both proposed designs, the input stage uses a

2442

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 1. Schematic of the DTMOS-based opamp. (a) Block scheme. (b) Differential input stage for opamp-A. (c) Differential input stage for opamp-B. (d) Class-AB output stage.

folded cascode wide-swing current mirror . In addition, transistors and have been added to enhance the slew-rate limitation of the folded cascode conguration. When the opamp is slew-rate limited, these transistors prevent and from having large transients which the drain of change their small-signal voltages to levels close to the positive provide power-supply voltage. DTMOS transistors the required bias current for the differential input transistors, and for the cascode current mirror. For the opamp-A, which is illustrated in Fig. 1(b), the use of DTMOS differential pairs enables us to take advantage of the maximum input range, while having all transistors operating in the strong inversion region. and ( and ) are designed Also, transistors to provide adequate bias voltage to , respectively. These transistors implement the gain boosting technique for high DC gain enhancement [21]. The opamp-B circuit depicted in Fig. 1(c) has been optimized for biomedical applications and is implemented to build the analog front-end part of a near-infrared spectroreectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus.Such device would provide a portable, noninvasive

means of monitoring and imaging brain function and biological tissues, because of the relatively low absorption of water and high absorption of oxyhemoglobin and deoxyhemoglobin in the NIR region of 600900 nm. The NIRS device is composed of two parts: the emitter and the receivers. The emitter consists of three NIR laser diodes emitting light at discrete wavelengths of 735 nm, 840 nm, and 940 nm. The receivers are a set of six separate identical sensors, optically and electrically isolated from each other. Each sensor consists of a CMOS photodiode with a built-in current-to-voltage converter, voltage opamp, lter, and mixer. The CMOS photodiode transforms the reected light into current. A transimpedance amplier is used to transform the currents extracted from the photodiodes into voltages, and the low-noise, low-power, DTMOS-based class-AB opamp-B is used to selectively amplify the low-amplitude signal before it is ltered and then demodulated. and devices of the input The pMOS-based DTMOS stage of opamp-B are operated between weak and moderate inversion regions. Such operation ensures transconductance effor the lowest amount of input referred gate ciency noise voltage at the minimum possible bias current. However,

ACHIGUI et al.: 1-V DTMOS-BASED CLASS-AB OPERATIONAL AMPLIFIER: IMPLEMENTATION AND EXPERIMENTAL RESULTS

2443

TABLE II DEVICE SIZES OF DIFFERENTIAL INPUT STAGE FOR OPAMP-A AND OPAMP-B

Fig. 3. Microphotograph of the DTMOS-based opamp-A.

Fig. 4. Microphotograph of the DTMOS-based opamp-B.

Fig. 2. DTMOS transistor. (a) Micrograph of the device. (b) Test bench used. (c) Measured total source current against source-gate voltage for various sourcedrain voltage.

all other transistors are biased in the strong inversion region. Typically, CMOS transistors operating in subthreshold are biased at very small drain currents in the order of a few nanoamperes, but provide a limited gainbandwidth product (GBW). However, for CMOS transistors designed with large width-to) ratios, subthreshold operation is possible at modlength ( erately large currents, resulting in a lower input noise voltage and have and higher GBW product. The input devices

a ratio of 2733, to ensure subthreshold voltage operation under a bias current of 3.88 A per device. Furthermore, operational transconductance ampliers (OTAs) have been used to and , and to enprovide adequate bias voltages to hance small-signal operation stability. Since the negative feedback needed to stabilize the active cascode devices in opamp-A is provided by transistors used in a to operate in common-source conguration, for their linear region, the minimum voltage at their gate should be higher than one threshold voltage; thus, for very low level besignal amplitude, the feedback loop through comes unstable. With the use of OTA in the feedback loop of acin the opamp-B as depicted in tive cascode devices Fig. 1(c), this requirement is no longer necessary. Consequently, opamp-B exhibits enhanced stability while processing signals with small amplitude. Table II gives the device parameters of the differential input stage for both opamp-A and opamp-B.

2444

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 5. Measured transient results. (a) Step input response. (b) Sine response with an input signal amplitude of 0.7 V (d) Sine response with an input signal amplitude of 0.6 V for opamp-B.

for opamp-A. (c) Step input response.

C. Class-AB Output Stage The output stage is a key point in the design of low-voltage ampliers since it greatly affects the nal features of the amplier itself. The low-voltage class-AB output stage that we used is shown in Fig. 1(d) [22]. This architecture namely current subtracting class-AB has been originally based on a bipolar lowvoltage translinear loop that is used to perform the quiescent current control [23], [24]. The signal is split to the output by the , and current mirrors output transistors and , which provide a low impedance signal path to the output. Quiescent current control is based on the current . comparison performed at the drain of transistor III. EXPERIMENTAL RESULTS The proposed opamps were fabricated in a standard 0.18- m single-poly six-metal salicide CMOS process technology with

metal-to-metal (MiM) capacitors. Nominal values for the threshold voltages are approximately 0.47 V and 0.55 V for nMOS and pMOS transistors, respectively.

A. DTMOS Measurements A DTMOS device m m was fabricated and tested; its die micrograph is shown in Fig. 2(a). We used the Keithley 236 Source-Measure Unit (SMU) with the test setup as against illustrated in Fig. 2(b) to measure the source current for different values of the source-drain source-gate voltage voltage of the DTMOS transistor [Fig. 2(c)]. It is important larger to note that large leakage current is generated for than 0.7 V, as the source-to-bulk p-n junction diode becomes forward biased.

ACHIGUI et al.: 1-V DTMOS-BASED CLASS-AB OPERATIONAL AMPLIFIER: IMPLEMENTATION AND EXPERIMENTAL RESULTS

2445

Fig. 6. Measured step response for input signal with low amplitude (0.1 V (a) Opamp-A. (b) Opamp-B.

). Fig. 7. Measured DC transfers characteristics of the input common-mode range. (a) Opamp-A. (b) Opamp-B.

B. Opamps Measurements The die micrographs of opamp-A and opamp-B, using the input stage of the circuit presented in Fig. 1(b) and (c), are presented in Fig. 3 and Fig. 4, respectively. Measurements were taken using the Agilent 33250A function waveform generator and the Tektronix TDS7154 oscilloscope, with a 5-pF capacitive load in parallel with a 10-k load. The measured input and output common-mode range voltages are 0.7 V and 0.9 V for opamp-A, and 0.6 V and 0.8 V for opamp-B, respectively. The measured transient results for a step input signal are shown in Fig. 5(a) for opamp-A and in Fig. 5(c) for opamp-B. and 0.6 Fig. 5(b) and (d) depict the response to a 0.7 sinusoid input signal for the proposed opamp-A and opamp-B, respectively. For opamp-A, the measured DC open-loop gain is 50.1 dB with a GBW of 26.2 MHz and a common-mode rejection ratio (CMRR) of 78 dB. It consumes 550 W of power, and has an input referred noise of 160 nV Hz at 1 kHz. Also, for the opamp-B, which has been optimized for biomedical applications, we measured a DC open-loop gain of 53 dB, and a unity frequency of 1.3 MHz. The latter has a lower input referred noise of 107 nV Hz at 1 kHz, with a power consumption of only 40 W. The measured transient responses for a low amplitude step are shown in Fig. 6(a) for opamp-A, input signal of 0.1 introduced where the use of gain boosted transistors small oscillations, due to instability in the feedback loop through and as depicted in the graph active cascode devices of Fig. 6(a). The OTA used in the folded cascode at the input stage of opamp-B has enabled us to achieve higher stability when the inputs are processing a signal with small amplitude, as illustrated in Fig. 6(b). This ability for an opamp to linearly process small levels of input signal is a key requirement for the amplier for modules of the analog front-end receiver [20]. The DC transfers characteristic of opamp-A and opamp-B are depicted in Fig. 7(a) and (b), respectively. Moreover, Fig. 8(a)

2446

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 8. Measured common-mode input range. (a) Opamp-A. (b) Opamp-B.

and (b) illustrate the input common-mode range of opamp-A and opamp-B, respectively. In addition, the step input response measurements of opamp-A when it is used in a noninverting conguration with a gain of two is illustrated in Fig. 9(a), and the step input response when it is used in the inverting conguration is illustrated in Fig. 9(b). Similar results should be obtainable for the opamp-B. The minimum experimental supply voltage is 0.8 V. In fact, Fig. 10 depicts the ability of opamp-A to process the step when the input signal of an amplitude as high as 0.57 supply voltage is as low as 0.8 V. Table III summarizes the performances of both opamp-A and opamp-B. C. Harmonic Distortion Analysis With the use of a class-AB output stage, it is important to outline how far the proposed opamps can dependably reproduce the signal applied at its input. Evaluation of the misshapen responses between the fundamental frequency at the input and at the output is done by calculating the harmonic and inter-modulation distortion levels between the sample data. A fast Fourier transform (FFT) analysis was performed, and the power spectral density of opamp-As output signals are shown in Fig. 11(a),

Fig. 9. Measured transient results for opamp-A. (a) Noninverting conguration with a gain of 2; upper: input signal with amplitude of 0.299 V ; lower: output signal. (b) Inverting conguration with a gain of 1; upper: input signal with an amplitude of 0.3 V ; lower: output signal.

Fig. 10. Measured transient results for opamp-A under a supply voltage of 0.8 V with a step input signal of amplitude of 0.57 V .

with an input sinusoidal signal frequency of 4.0 kHz, and an am. Fig. 11(b) depicts the measured output signal plitude of 0.7

ACHIGUI et al.: 1-V DTMOS-BASED CLASS-AB OPERATIONAL AMPLIFIER: IMPLEMENTATION AND EXPERIMENTAL RESULTS

2447

TABLE III PERFORMANCE SUMMARY OF THE MEASURED RESULTS

Fig. 12. Measured total harmonic distortion. (a) Opamp-A. (b) Opamp-B.

spectrum of opamp-B, with an input sinusoidal signal frequency of 10 kHz and an amplitude of 0.6 . Fig. 12(a) and (b) show the measured THD of the eighth rst harmonics for opamp-A and opamp-B, respectively, in unity-gain conguration for different peak-to-peak amplitude level of a 4-kHz input sinusoidal signal. IV. CONCLUSION A novel opamp architecture was reported along with its experimental measurements. Two versions of this opamp were fabricated for 1-V applications using DTMOS transistors under standard 0.18- m CMOS process technology. Measurements show that the use of dynamic threshold pMOS transistors permits implementation of analog circuits at low supply voltage. For the rst design, opamp-A, the circuit operates with a power supply as low as 1-V, while providing a DC open-loop gain of 50.1 dB and a GBW of 26.2 MHz, under a load condition of 5 pF and 10 k . This opamp consumes 550 W of power. Applications of this circuit could include switched-capacitor lters, data converters or any sampled-data systems. However, the second design (opamp-B) exhibits a low power consumption of 40 W, while presenting a DC open-loop gain of 53 dB, a GBW of 1.3 MHz, and an input referred noise of 107 nV Hz at 1 kHz. These features were measured under the same load conditions as opamp-A. Opamp-B is intended to build the analog front-end part of a NIRS receiver of a multi-wavelength wireless brain oxymeter apparatus. The minimum experimental supply voltage is 0.8 V for the proposed circuits.
Fig. 11. Measured output spectrum. (a) Opamp-A with a sine input signal amplitude of 0.7 V . (b) opamp-B with a sine input signal amplitude of 0.6 V .

REFERENCES
[1] International Technology Roadmap for Semiconductors (ITRS), Update, Semiconductor Industry Association (SIA), 2004.

2448

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

[2] C. Hu, Future CMOS scaling and reliability, Proc. IEEE, vol. 81, no. 5, pp. 682689, May 1993. [3] B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, Designing 1-V opamps using standard digital CMOS technology, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 7, pp. 769780, Jul. 1998. [4] T. Lehmann and M. Cassia, 1-V power supply CMOS cascode amplier, IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 10821086, Jul. 2001. [5] I. Grech et al., A low voltage wide-input-range bulk-input CMOS OTA, Analog Integr. Circuits Signal Process., vol. 43, no. 2, pp. 127136, May 2005. [6] C. J. B. Fayomi, M. Sawan, and G. W. Roberts, Reliable circuit techniques for low-voltage analog design in deep submicron standard CMOS: A tutorial, Analog Integr. Circuits Signal Process., vol. 39, pp. 2138, Apr. 2004. [7] J. H. Huijsing et al., Low-voltage low-power opamp based ampliers, Analog Integr. Circuits Signal Process., vol. 8, pp. 4967, Jul. 1995. [8] J. F. Duque-Carrillo et al., 1-V rail-to-rail operational ampliers in standard CMOS technology, IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 3344, Jan. 2000. [9] E. K. F. Lee, Low-voltage opamp design and differential difference amplier design using linear transconductor with resistor input, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 8, pp. 776778, Aug. 2000. [10] J. Ramrez-Angulo et al., Low-voltage CMOS operational ampliers with wide input-output swing based on a novel scheme, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 5, pp. 772774, May 2000. [11] F. Schlogl and H. Zimmermann, Low-voltage operational amplier in 0.12 m digital CMOS technology, IEE Proc. Circuits, Devices Syst., vol. 151, no. 5, pp. 395398, Oct. 2004. [12] V. S. L. Cheung et al., A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers, IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 805816, May 2003. [13] S. Karthikeyan et al., Design of low-voltage front-end interface for switched-opamp circuits, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 7, pp. 722726, Jul. 2001. [14] F. Assaderaghi et al., A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation, in Proc. IEEE Electronic Devices Tech. Dig., Dec. 1994, pp. 809812. [15] B. K. James and L. Shih-Chia, Low-Voltage SOI CMOS VLSI Devices and Circuits. New York: Wiley, 2001. [16] J. Ramrez-Angulo et al., Low-voltage CMOS op-amp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input oating-gate transistors, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 1, pp. 111116, Jan. 2001. [17] W. de la Hidalga et al., Effect of the forward biasing the source-substrate junction in n-MOS transistors for possible low power CMOS integrated circuits applications, J. Vac. Sci. Technol B., vol. 16, no. 4, pp. 18121817, Jul. 1998. [18] P. E. Allen, B. J. Blalock, and G. A. Rincon, Low voltage analog circuits using standard CMOS technology, in Proc. Int. Symp. Low Power Design, 1995, pp. 209214. [19] H. F. Achigui, C. J. B. Fayomi, and M. Sawan, A DTMOS-based 1 V opamp, in Proc. Int. IEEE ICECS Conf., Dec. 2003, vol. 1, pp. 252255. [20] , A 1 V low power, low noise DTMOS based class AB opamp, in Proc. Int. IEEE NEWCAS Conf., Jun. 2005, pp. 8487. [21] K. Bult and G. Geelen, A fast settling CMOS op amp for SC circuits with 90 dB DC gain, IEEE J. Solid-State Circuits, vol. 25, no. 12, pp. 13791384, Dec. 1990. [22] F. Silveira and D. Flandre, Analysis and design of a family of lowpower class AB operational ampliers, in Proc. IEEE Int. Symp. Circuits and Systems, 2000, pp. 9499. [23] J. Fonderie and J. H. Huijsing, Operational amplier with 1-V rail-torail multipath-driven output stage, IEEE J. Solid-State Circuits, vol. 21, no. 12, pp. 18171824, Dec. 1991. [24] F. Thus, A compact bipolar class AB output stage using 1 V power supply, IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 17181722, Dec. 1992.

Herv Facpong Achigui (S01) received the B.Eng. and M.Sc.A. degrees, both in electrical engineering, from cole Polytechnique de Montral, Canada, in 2002 and 2006, respectively. He worked at Motorola in 2001 during his studies and joined Polystim Neurotechnologies Laboratory at Ecole Polytechnique de Montral in 2002. He was a research and teaching assistant at both Polystim Neurotechnologies and Universit du Qubec Montral (UQM) in the Computer Science Department from 2004 to 2006. He is currently with PMC-Sierra, Montreal, working on low-voltage CMOS mixed-signal integrated circuits and systems.

Christian Jsus B. Fayomi (M97) received the B.Eng. degree (with rst in ones year honors) in electromechanical engineering from cole Polytechnique de This, Sngal, in 1993 and the M.A.Sc. (with rst class honors) and Ph.D. degrees from cole Polytechnique de Montral, Canada, in 1995 and 2003, respectively, all in electrical engineering. From 1996 to 2001, he was with the mixed-signal design group of Goal Semiconductors Inc. Montral, working on readout electronic circuits for bolometers, phototransistors, microprocessor supervisory circuits, and data converters. From 1998 to 1999, he was also a Teaching Assistant at the Microelectronics and Computer Laboratory (MACS-Lab), Electrical Engineering Department, McGill University, Montral. From 2001 to 2002, he was with the Microelectronics Division of IBM, Essex Junction, VT, as an Advisory Engineer, designing data converters for video applications. He is currently Assistant Professor at Universit du Qubec Montral (UQM) in the Computer Science Department and is leading the Wireless Smart Devices Laboratory. Since June 2006, he has held the Adjunct Professor position in the Electrical and Computer Engineering Department at the Universit du Qubec Trois-Rivires (UQTR). His funded research area is the design of reliable low-voltage deep-submicron CMOS mixed-signal integrated circuits and systems.

Mohamad Sawan (F04) received the B.Sc. degree in electrical engineering from Universit Laval, Quebec, Canada, in 1984, and the M.Sc. and Ph.D. degrees in electrical engineering from Universit de Sherbrooke, Quebec, Canada, in 1986 and 1990, respectively. He then completed postdoctoral training at McGill University, Montral, Canada, in 1991, and in that same year, joined cole Polytechnique de Montral, where he is currently a Professor of Microelectronics. He has published more than 350 papers in peer-reviewed journals and conference proceedings, and has been awarded seven patents. His scientic interests focus on the design and testing of mixed-signal (analog, digital, and RF) circuits and systems, digital and analog signal processing, and the modelling, design, integration, assembly, and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward biomedical implantable devices and telecommunications applications. Dr. Sawan holds the Canada Research Chair in Smart Medical Devices. He heads the Regroupement stratgique en microsystmes du Qubec (Microsystems Strategic Alliance of Qubec-ReSMiQ) and is the founder of the Eastern Canada Chapter of the IEEE Solid-State Circuits Society. He also founded the International IEEE NEWCAS conference, co-founded the International Functional Electrical Stimulation Society, and founded the Polystim Neurotechnologies Laboratory at Ecole Polytechnique de Montral. He is the editor of Springer Mixed-Signal Letters, Distinguished Lecturer for the IEEE Circuits and Systems (CAS) Society, Chair of the IEEE Biomedical CAS (BioCAS) Technical Committee, and member of the Biotechnology Council representing the IEEE CAS Society. He received the Barbara Turnbull Award for spinal cord research (2003), the Medal of Merit from the Lebanese President (2005), the J. Armand Bombardier Award from the Association Francophone pour le savoir (ACFAS), and the American University of Science and Technology Achievement Award. Dr. Sawan is a Fellow of the Canadian Academy of Engineering and the IEEE.