SELVAM COLLEGE OF TECHNOLOGY,NAMAKKAL

DEPARTMENT OF ECE

TWO MARK

SUBJECT NAME : MICROCONTROLLER AND RISC ARCHITECTURE.

STAFF INCHARGE :Mr.R.RAGUMADHAVAN.

Selvam College of technology Department of Electronics and Communication Engineering Microcontroller And RISC Architecture Unit-1 8051 ARCHITECTURE 2 MARK QUESTIONS & ANSWERS 1. Features of 8051microcontroller. 8 bit controller operating on bit and byte. 256 bytes internal RAM and 4 kb internal RAM 64/60 kb external program memory address space 64 kb external data memory address space 4 numbers of 8 bit parallel ports. 2. Difference between microprocessor and microcontroller. s.no microprocessor It contains ALU,general 1 purpose reg, sp,pc,clock timing circuit, interrupt circuit Microcontroller It contains the circuitry of mp and in addition, it has built in ROM, RAM, I/O devices, timer and counters. It has one or two instructions to move data between memory and CPU.

2. It has many instructions to move data between memory and CPU.

3. Access times for memory and i/o devices are more. 4. Microprocessor based system is more flexible in design point of view. 5. Less no of pins are multi functioned More no of pins are mutlifunctioned Less flexible in design point of view. Less access time required.

3. State the functions of RS1 and RS0 bit in the flag register It is used to select the register banks RS1 0 0 1 1 RS0 0 1 0 1 Bank selection 00 H 07 H BANK 0 08H -0F H BANK 1 10H 17 H BANK 2 18 H 1F H BANK 3

4. Difference between RR A and RRC A instructions in 8051 RR A Rotate accumulator right The 8 bits in the accumulator are rotated 1 bit to the right.bit 0 is rotated in to the bit 7 position. No flags are affected. RRC A Rotate accumulator right through carry flag The 8 bits in the accumulator and the carry flag together rotated 1 bit to the right.bit 0 is moves in to the bit carry flag; the original value of the flag moves in to the bit 7 position. No flags are affected.

5. Show the format of PSW register of 8051 B7 CY B6 AC B5 F0 B4 RS1 B3 RS0 B2 OF B1 B0 P

6. What are the functions of DPTR register? The data pointers consist of a high byte (DPH) and a low byte (DPL). It functions is to hold a 16 byte address. It serves as a base register in indirect jumps, lookup table instructions and external data transfer. 7. List the interrupt structures of 8051. Priority level structure. External interrupts. Single step operation. 8. List the instruction sets of 8051. Data transfer Arithmetic Logical Branching Boolean
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9. List the addressing modes supported by 8051. Register addressing Direct byte addressing Register indirect Immediate Register specific Index 10. What are the operating modes of the timer of 8051? The operating modes of the timer are mode 0, mode1, mode2, mode3. In mode 0, timer will function as 13 bit timer, in mode1 will function as 16 bit timer, in mode2, function as 8 bit with auto reload feature. 11. List the interrupts of 8051 microcontroller. It has External interrupt -0 Timer-0 interrupt External interrupt-1 Timer-1 interrupt Serial port interrupts. 12. What are the dedicated address pointers in 8051? Program counter Data pointer. The PC is used as address pointer for program and DPTR is used as address pointer for data. 13. What are the register banks in 8051? The reg banks are internal RAM locations of 8051 which can be used as general purpose reg or scratch pad reg. The first 32 bytes of internal RAM of 8051 and organise as 4 reg banks with each bank consisting 8 locations. At any one time the processor can work with only one reg bank depending on the value of bits RS0 and RS1. 14. How stack is implemented in 8051. The 8051 LIFO .Stack can reside anywhere in the internal RAM it has 8 bit stack pointer to indicate the top if stack. This can be accessed by PUSH and POP instructions. During PUSH the SP is incremented by 1 and during POP the SP is decremented by 1.

15. Explain the interrupts of 8051 microcontroller. The interrupts are: Vector address External interrupt 0 Timer interrupt 0 External interrupt 1 Timer Interrupt 1 Serial Interrupt Receive interrupt : RI Transmit interrupt: TI 16. Define stack. Stack is a sequence of RAM memory locations defined by the Programmer. 17. What is program counter? How it will be useful in program execution? The program counter keeps track of program execution. To execute a program the starting address of the program is loaded in program counter. The PC sends out an address to fetch a byte of instruction from memory and increments its content automatically. : : 0023H 0023H : IE0 : : : : 0003H 000BH 0013H 001BH

: TF0 : IE1

: TF1

Selvam College of technology Department of Electronics and Communication Engineering Microcontroller And RISC Architecture Unit-2 8051Assembly language programming TWO MARK QUESTIONS & ANSWERS 1. How the baud rate is decided in mode1 and mode3 in the serial transmission of 8051 The baud rate depends on SMOD bit of PCON reg and the yimer-1 overflow rate shown below. The baud rate in mode 1 or 3= 2 / 32 (timer 1 overflow rate). 2. How to estimate the time taken to execute the instruction in 8031/8051 controller It is obtained by multiplying the time to execute machine cycle by the number of machine cycles of the instruction. The time to execute a machine time is 12 clock periods. Time to execute an instruction=C *12* T=C *12 *1/F. 3. List the various machine cycle of 8031/8051 controller. 4. External program memory fetch cycle. External data memory read cycle. External data memory write cycle. Port operation cycle.

List the instruction of 8051 that all the flag of 8051 The 8051 instruction that affect all the flag are ADD, ADDC, and SUBB

5. List the instruction of 8051 that affect overflow flag in 8051. The 8051 instruction that affect overflag are ADD, ADDC, DIV, MUL, and SUBB. 6. List the instruction of 8051 that always clear carry flag. The instruction that always clear carry flag are CLR C, DIV, MUL. 7. What are the operations performed by Boolean variable instruction of 8051? The Boolean variable instructions can carry or complement or move a particular bit 8. Write a program to perform multiplication of 2 nos using 8051. MOV A,#data 1 MOV B,#data 2 MUL AB
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MOV DPTR,#5000 MOV @DPTR,A(lower value) INC DPTR MOV A,B MOVX @ DPTR,A 9. Write a program to mask the 0th &7th bit using 8051. MOV A,#data ANL A,#81 MOV DPTR,#4500 MOVX @DPTR,A LOOP SJMP LOOP 10. List the addressing modes of 8051. Direct addressing Register addressing Register indirect addressing. Implicit addressing Immediate addressing Index addressing Bit addressing

11. Write about CALL statement in 8051. There are two subroutine CALL instructions. They are *LCALL(Long CALL) *ACALL(Absolute CALL) Each increments the PC to the 1st byte of the instruction & pushes them in to the stack.

12. Write about the jump statement. There are three forms of jump. They are LJMP(Long jump)-address 16 AJMP(Absolute Jump)-address 11 SJMP(Short Jump)-relative address 13. Write program to load accumulator ,DPH,&DPL using 8051. MOV A,#30 MOV DPH,A MOV DPL,A 14. Write a program to find the 2s complement using 8051. MOV A,R0 CPL A INC A 15. Write a program to add 2 8-bit numbers using 8051. MOV A,#30H ADD A,#50H 16. Explain the operating mode0 of 8051 serial ports. In this mode serial enters &exits through RXD, TXD outputs the shift clock.8 bits are transmitted/received: 8 data bits (LSB first).The baud rate is fixed at 1/12 the oscillator frequency. 17. Explain the operating mode2 of 8051 serial ports. In this mode 11 bits are transmitted(through TXD)or received (through RXD):a start bit(0), 8 data bits(LSB first),a programmable 9th data bit ,& a stop bit(1).ON transmit the 9th data bit (TB* in SCON)can be assigned the value of 0 or 1.Or for eg:, the parity bit(P, in the PSW)could be moved into TB8.On receive the 9th data bit go in to the RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32or1/64 the oscillator frequency.

18. Explain the mode3 of 8051 serial ports. In this mode,11 bits are transmitted(through TXD)or received(through RXD):a start bit(0), 8 data bits(LSB first),a programmable 9th data bit ,& a stop bit(1).In fact ,Mode3 is the same as Mode2 in all respects except the baud rate. The baud rate in Mode3 is variable. In all the four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode0 by the condition RI=0&REN=1.Reception is initiated in other modes by the incoming start bit if REN=1.

19. Write a program to swap two numbers using 8051. MOV A, #data SWAP A 20. Write a program to subtract two 8-bit numbers &exchange the digits using 8051. MOV A,#9F MOV R0,#40 SUBB A,R0 SWAP A 21. Write a program to subtract the contents of R1 of Bank 0from the contents of R0 of Bank 2 using 8051. MOV PSW,#10 MOV A,R0 MOV PSW,#00 SUBB A,R1

Selvam College of technology Department of Electronics and Communication Engineering Microcontroller and RISC architecture Unit-3 8051 Real World Interfacing 2 MARK QUESTIONS & ANSWERS 1. Give the M/IO used for interfacing technique. M/IO=1; microprocessor communicating with memory system. M/IO=0; microprocessor communicating with IO system. 2. Give the two methods for interfacing IO device. (Nov 2007) 1. Input/Output Mapped I/O. 2. Memory Mapped I/O. 3. Describe programmed I/O. The transfer of data is completely under the control of microprocessor program. The data transfer takes place only when I/O transfer instruction executed. 4. What is the input device used in I/O interfacing? The Input device used in I/O interfacing is buffer. The data transferred to output need to be latched so that it will be available for checking or displaying. 5. What is the output device used in I/O interfacing? The output device used in I/O interfacing is latch. When microprocessor wants to read data from input device it will enable the buffer so data so data will be transferred on to data bus of microprocessor 6. What is cycle stealing? The refresh cycles are accomplished by doing a write; a read .The refresh cycle is totally internal to the DRAM and is accomplished while other memory components in the system operate. This type of refresh is known as cycle stealing or hidden refresh. . 7. What is the range of IO in interfacing? IO devices can be mapped in the specified IO range as 255 or 65535. 8. What are the two ways to address the IO? The two ways to address the IO are 1. Direct Addressing 2. Indirect Addressing 3.

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9. What are the parameters needed to interface memory? Address to output delay (tACC) CE to output delay (tCE) Output enable to output delay (tOE). 10. What is meant by SRAM and its applications? Static RAM or SRAM is a type of RAM that uses a flip-flop as its basic storage element. Application: To avoid inserting WAIT states, most high speed micro computer systems require a cache memory subsystem. These systems are normally designed using SRAM. 11. What are the internal devices of 8255 ? The internal devices of 8255 are port-A, port-B and port-C. The ports can be programmed for either input or output function in different operating modes. 12. What are the internal devices of a typical DAC? The internal devices of a DAC are R/2R resistive network, an internal latch and current to voltage converting amplifier. 13. What do you meant by settling or conversion time in DAC? The time taken by the DAC to convert a given digital data to corresponding analog signal is called conversion time. 14. What are the different types of ADC? The different types of ADC are successive approximation ADC, counter type ADC flash type ADC, integrator converters and voltage-to-frequency converters. 15. What are the tasks involved in keyboard interface? The task involved in keyboard interfacing are sensing a key actuation, Debouncing the key and Generating key codes (Decoding the key). These task are performed software if the keyboard is interfaced through ports and they are performed by hardware if the keyboard is interfaced. 16. Give some examples of input devices to microcontroller based system. The input devices used in the microcontroller-based system are Keyboards, DIP switches, ADC, Floppy disc, etc.

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Selvam College of Technology Department of Electronics and communication Engineering Microcontroller and RISC architecture Unit-4 The ARM RISC Architecture 1. Give the difference between RISC and CISC processor A fixed (32-bit) instruction size with few formats; CISC processors typically had Variable length instruction sets with many formats. A load-store architecture where instructions that process data operate only on registers and are separate from instructions that access memory; CISC processors typically allowed values in memory to be used as operands in data processing instructions. A large register bank of thirty-two 32-bit registers, all of which could be used for any purpose, to allow the load-store architecture to operate efficiently; CISC register sets were getting larger, but none was this large and most had different registers for different purposes (for example, the data and address registers on the Motorola MC68000). 2. What are the advantages of RISC? A smaller die size. A shorter development time Higher performance 3. How the earlier RISC performance was improved. The earlier performance improved by two factors Pipelining A high clock rate with single cycle execution 4. What are the drawback of RISC processor? RISCs generally have poor code density compared with CISCs. RISCs don't execute x86 code. 5. What are the factors determine the CMOS circuit power consumption? Switching power Short circuit power Leakage current 6. What are the various approaches or low power design? Minimize the power supply voltage, Vdd. Minimize the circuit activity, A. Minimize the number of gates. Minimize the clock frequency, f.

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7. What are the features used in the ARM processor? a load-store architecture; fixed-length 32-bit instructions; 3-address instruction formats.

8. What are the features rejected in the ARM processor? Register windows. Delayed branches Single cycle execution of all instruction 9. What are the various registers used in Arm processor? When writing user-level programs, only the 15 general-purpose 32-bit registers (r0 to r!4), the program counter (r15) and the current program status register (CPSR) need be considered. The remaining registers are used only for system-level programming and for handling exceptions 10. Give the CPSR format for ARM.

N: Negative; the last ALU operation which changed the flags produced a negative result (the top bit of the 32-bit result was a one). Z: Zero; the last ALU operation which changed the flags produced a zero result (every bit of the 32-bit result was zero). C: Carry; the last ALU operation which changed the flags generated a carry-out, either as a result of an arithmetic operation in the ALU or from the shifter. V: overflow; the last arithmetic ALU operation which changed the flags generated an overflow into the sign bit 11. Explain about the memory organisation of ARM. Memory may be viewed as a linear array of bytes numbered from zero up to 232-l. Data items may be 8-bit bytes, 16-bit half-words or 32-bit words. Words are always aligned on 4-byte boundaries (that is, the two least significant address bits are zero) and half-words are aligned on even byte boundaries. 12. What are the principal components of 3 stage pipeline? Register bank,, ALU, Barrel shifter ,Address register, Data register, Instruction decoder 13. What are the operations done by 3 stage pipeline? Fetch; The instruction is fetched from memory and placed in the instruction pipeline. Decode; The instruction is decoded and the datapath control signals prepared for the next
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Cycle. In this stage the instruction 'owns' the decode logic but not the datapath. Execute; The instruction 'owns' the datapath; the register bank is read, an operand shifted, the ALU result generated and written back into a destination register. 14. What are the ways to find the breaks in the pipeline? The simplest way to view breaks in the ARM pipeline is to observe that: All instructions occupy the data path for one or more adjacent cycles. For each cycle that an instruction occupies the data path, it occupies the decode logic in the immediately preceding cycle. During the first data path cycle each instruction issues a fetch for the next instruction but one. Branch instructions flush and refill the instruction pipeline. 15. What are the ways to improve the performance of 5 stage pipeline? Increase the clock rate, fclk. Reduce the average number of clock cycles per instruction, CPI. 16. What are the stages available in the 5 stage pipeline? Fetch; The instruction is fetched from memory and placed in the instruction pipeline. Decode; The instruction is decoded and register operands read from the register file. There are three operand read ports in the register file, so most ARM instructions can source all their operands in one cycle. Execute; An operand is shifted and the ALU result generated. If the instruction is a load or store the memory address is computed in the ALU. Buffer/data; Data memory is accessed if required. Otherwise the ALU result is simply buffered for one clock cycle to give the same pipeline flow for all instructions. Write-back; The results generated by the instruction are written back to the register file,including any data loaded from memory. 17. What are the factors determines the minimum cycle time ? The minimum datapath cycle time is therefore the sum of: the register read time; the shifter delay; the ALU delay; the register write set-up time; the phase 2 to phase 1 non-overlap time.

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18. What the features are of ARM 7 processor? The ARM7, a 3 volt compatible rework of the ARM6 32-bit integer core, with the Thumb 16bit compressed instruction set; on-chip Debug support, enabling the processor to halt in response to a debug request; an enhanced Multiplier, with higher performance than its predecessors and yielding a full 64-bit result; EmbeddedlCE hardware to give on-chip breakpoint and watch point support. 19. What are the additional features provided by ARM 9 TDMI? Hardware single-stepping is supported. Breakpoints can be set on exceptions in addition to the address/data/control conditions supported by ARM7TDMI 20. How the ARM 9 TDMI supports the co-processor support. The ARM9TDMI has a coprocessor interface which allows on-chip coprocessors for floatingpoint, digital signal processing or other special-purpose hardware acceleration requirements to be supported.

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Selvam College of Technology Department of Electronics and communication Engineering Microcontroller And RISC Architecture Unit-5 The ARM Instruction And Assembly Language Programming 1. What are the data types accepted by ARM processor? ARM processors support six data types: 8-bit signed and unsigned bytes. 16-bit signed and unsigned half-words; these are aligned on 2-byte boundaries. 32-bit signed and unsigned words; these are aligned on 4-byte boundaries. 2. What do you meant by exception? Exceptions are usually used to handle unexpected events which arise during the execution of a program, such as interrupts or memory faults 3. What are the types of exception? Exceptions generated as the direct effect of executing an instruction. Exceptions generated as a side-effect of an instruction. Exceptions generated externally, unrelated to the instruction flow. 4. Explain the priorities for exception. Since multiple exceptions can arise at the same time it is necessary to define a priority Order to determine the order in which the exceptions are handled. On ARM this is: 1. Reset (highest priority); 2. Data abort; 3. FIQ; 4. IRQ; 5. Prefetch abort; 6. SWI, undefined instruction (including absent coprocessor). These are mutually exclusive instruction encodings and therefore cannot occur simultaneously. 5. Explain about the conditional execution. An unusual feature of the ARM instruction set is that every instruction (with the exception of certain v5T instructions) is conditionally executed. Conditional branches are a standard feature of most instruction sets, but ARM extends the conditional execution to all of its instructions, including supervisor calls and coprocessor instructions. The condition field occupies the top four bits of the 32-bit instruction field. 6. Explain about the branch instruction. Branch and Branch with Link instructions are the standard way to cause a switch in the sequence of instruction execution. The ARM normally executes instructions from sequential word addresses in memory, using conditional execution to skip over individual instructions where required. 7. Explain about the Branch, Branch with Link and exchange.
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These instructions are available on ARM chips which support the Thumb (16-bit) instruction set, and are a mechanism for switching the processor to execute Thumb instructions or for returning symmetrically to ARM and Thumb calling routines.

8. Explain about software interrupt. The software interrupt instruction is used for calls to the operating system and is often called a 'supervisor call'. It puts the processor into supervisor mode and begins executing instructions from address 0x08. 9. Explain the processor operations for the execution of software interrupt If the condition is passed the instruction enters supervisor mode using the standard ARM exception entry sequence. In detail, the processor actions are: 1. Save the address of the instruction after the SWI in r14_svc. 2. Save the CPSR in SPSR_svc. 3. Enter supervisor mode and disable IRQs (but not FIQs) by setting CPSR[4:0] to 100112 and CPSR [7to l]. 4. Set the PC to 08 and begin executing the instructions there. 10. What is the use of data processing instruction? The ARM data processing instructions are used to modify data values in registers. The operations that are supported include arithmetic and bit-wise logical combinations of 32-bit data types. One operand may be shifted or rotated en route to the ALU, allowing, for example, shift and add in a single instruction 11. Explain about single word and unsigned byte data transfer instruction. These instructions are the most flexible way to transfer single bytes or words of data between ARM's registers and memory. Transferring large blocks of data is usually better done using the multiple register transfer instructions, and recent ARM processors also support instructions for transferring half-words and signed bytes. 12. Explain about half word and signed byte data transfer. These instructions are not supported by some early ARM processors. As a result of their late addition to the architecture they are somewhat 'shoe-horned' into the instruction space as indicated by the split immediate field. 13. Explain about multiple register transfer instruction. The ARM multiple register transfer instructions allow any subset (or all) of the 16 registers visible in the current operating mode to be loaded from or stored to memory. A form of the instruction also allows the operating system to load or store the user-mode registers to save or restore the user process state, and another form allows the CPSR to be restored from the SPSR as part of a return from an exception handler. 14. Explain about the swap instruction. Swap instructions combine a load and a store of a word or an unsigned byte in a single instruction.
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15. What are the data types supported by ARM? Signed and unsigned characters of at least eight bits. Signed and unsigned short integers of at least 16 bits. Signed and unsigned integers of at least 16 bits. Signed and unsigned long integers of at least 32 bits. Floating-point, double and long double floating-point numbers. Enumerated types. Bitfields. The ARM C compiler adopts the minimum sizes for each of these types except the standard integer. 16. Explain about the thumb instruction. The Thumb instruction set can be incorporated into a 3-stage pipeline ARM processor macrocell with relatively minor changes to most of the processor logic (the 5-stage pipeline implementations are trickier). The biggest addition is the Thumb instruction decompressor in the instruction pipeline; this logic translates a Thumb instruction into its equivalent ARM instruction. 17. Give the properties of thumb instruction. The Thumb code requires 70% of the space of the ARM code. The Thumb code uses 40% more instructions than the ARM code. With 32-bit memory, the ARM code is 40% faster than the Thumb code. With 16-bit memory, the Thumb code is 45% faster than the ARM code. Thumb code uses 30% less external memory power than ARM code. 18. What is the application of thumb instruction. A high-end 32-bit ARM system may use Thumb code for certain non-critical routines to save power or memory requirements. A low-end 16-bit system may have a small amount of on-chip 32-bit RAM for critical routines running ARM code, but use off-chip Thumb code for all non-critical routines.

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