ATLAS - An Environment for NoC Generation and Evaluation

Aline Mello
UPMC - LIP6 4, Place Jussieu Paris, France
Aline.Vieira-de-Mello@lip6.fr

Ney Calazans and Fernando Moraes

PUCRS - FACIN Av. Ipiranga, 6681 Porto Alegre - Brazil
{calazans, moraes}@inf.pucrs.br

MPSoC is becoming a much more prevalent design style, to achieve tight time-to-market design goals, to maximize design reuse, to simplify the verication process and to provide exibility and programmability for post-fabrication reuse of complex platforms[6]. Networks-on-chip (NoCs) are employed as the communication infrastructure able to handle MPSoC communication requirements due to its scalability, power eciency, and support to globally asynchronous locally synchronous (GALS) paradigm[10][8][3]. NoCs are composed of cores connected to routers, and routers interconnected by communication channels [2]. The adoption of NoCs includes new challenges to the MPSoC design ow, such as choosing a suitable routing algorithm, NoC topology, buering strategy, ow control scheme, or reducing power dissipation. Due to the vast design space alternatives that these challenges may impose to the nal application and its required performance, the evaluation of NoCs become a mandatory step in the MPSoCs design ow[8][1]. The evaluation of NoCs is required to establish a good trade-o between the NoC architecture characteristics and the requirements of the given application. The ATLAS environment automates the various processes related to the design ow for some of NoCs (e.g. Hermes[7], Mercury) proposed by the GAPH Group[4] and eventually by other groups with which we collaborate. ATLAS is written in Java, allowing its execution in dierent hardware/software platforms. Figure 1 presents the ATLAS design exploration tool.

NoC Library

Power Equations

NoC Generation

Trac Generation

Simulation

Performance Evaluation

Power Evaluation

NoC
Trac Temporal Distribution

P P P
MPSoC

02 01 00

12 11 10

22 21 20

C C C
Output Trac Files

Input Trac Files

Figure 1: ATLAS design exploration ow The design ow included in the ATLAS framework contains the following tools: 1. The NoC Generation tool generates the network according to the conguration of following parameters: network dimension; communication channel bandwidth; buer depth; ow control (handshake or credit based); number of virtual channels; scheduling algorithm (round robin or priority); and routing algorithm (XY, west-rst, etc). The NoC is described in VHDL and its testbenches are described in SystemC. 2. The Trac Generation tool produces dierent trac patterns, for dierent injection rates and source/target pairs (e.g. random and complement). As described in [9], one important concept in trac modeling is the packet timestamp, which denes the ideal moment that a packet should be inserted into the NoC by a producer (P in Figure 1). The packet timestamp is calculated according dierent temporal trac distribution (e.g. normal, uniform and exponential). 3. The Simulation tool invokes a external VHDL/SystemC simulator: ModelSim. All generated trac les are interpreted and injected to the NoC. During the simulation, consumers (C in Figure 1) generate output les that are read by the trac analysis module, when the simulation nishes, allowing to compute the latency and throughput for each packet.

4. The Trac Evaluation tool veries if all packets were correctly received, and generates basic statistic data (e.g. a report le and graphics) concerning time to deliver packets. The report le presents some trac analysis results, such as: (i) total number of received packets, (ii) average time to deliver the packets, (iii) total time to deliver all packets and (iv ) the average, minimal, maximal and standard deviation time to deliver a packet. 5. The Power Evaluation tool uses an estimation model[5] to generate NoC power results (e.g. power reports). Atlas contains a set of predened equations annotated using a commercial power estimation tool (Synopsys PrimePower). These equations give the energy consumption and power dissipation according to the injection rate at each router port. The main contribution of the ATLAS environment is provide to the designer the possibility of evaluate the performance and power consumption of dierent NoC congurations, allowing optimize a NoC for a specic application or a set of them. NoCs generated by the ATLAS environment have been successfully prototyped in Xilinx FPGAs.

1. REFERENCES
[1] L. Benini. Application specic noc design. In Proceedings of the conference on Design, automation and test in Europe: Proceedings, DATE 06, pages 491495, 3001 Leuven, Belgium, Belgium, 2006. European Design and Automation Association. [2] L. Benini and G. De Micheli. Networks on chips: A new soc paradigm. Computer, 35:7078, January 2002. [3] T. Bjerregaard and S. Mahadevan. A survey of research and practices of network-on-chip. ACM Comput. Surv., 38, June 2006. [4] GAPH. Gaph main page. http://www.inf.pucrs.br/gaph/. [5] G. Guindani, C. Reinbrecht, T. Raupp, N. Calazans, and F. G. Moraes. Noc power estimation at the rtl abstraction level. VLSI, IEEE Computer Society Annual Symposium on, 0:475478, 2008. [6] G. Martin. Overview of the mpsoc design challenge. In DAC, pages 274279, 2006. [7] F. Moraes, N. Calazans, A. Mello, L. Mller, and L. Ost. Hermes: an infrastructure for low area overhead o packet-switching networks on chip. Integr. VLSI J., 38:6993, October 2004. [8] P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh. Performance evaluation and design trade-os for network-on-chip interconnect architectures. IEEE Trans. Comput., 54:10251040, August 2005. [9] L. Tedesco, A. Mello, D. Garibotti, N. Calazans, and F. Moraes. Trac generation and performance evaluation for mesh-based nocs. In Proceedings of the 18th annual symposium on Integrated circuits and system design, SBCCI 05, pages 184189, New York, NY, USA, 2005. ACM. [10] W. Wolf. The future of multiprocessor systems-on-chips. In Proceedings of the 41st annual Design Automation Conference, DAC 04, pages 681685, New York, NY, USA, 2004. ACM.