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Quartus II Schematic

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1. To mt project trn Quartus II :

Start -> Programs -> Altera -> Quartus II 7.2 -> Quartus II 7.2 ( 32 -Bit ) :

Hnh 1 : Mn hnh chnh.

Nhn tab File trn mn hnh chnh :

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Quartus II Schematic

------------------------------------------------------------------------------------------------------- M mt project mi : File -> New Project Wizard

Nhn Next >

Nhp ng dn th mc ca project ( c th to trc hoc nu cha to s

c t ng to ).
Nhp tn ca project.
Nhp top-level ca thit k cho project ( nn cho ging tn ca project ).
Nhn Next >

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Quartus II Schematic

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Nu ng dn th mc ca project cha c to trc :

Nhn Yes

Nhn Next >

Chn Family : Cyclone II

Chn Available devices : EP2C35F672C6 ( H ca Chip FPGA Cyclone II trn
Kit DE2 ).

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Quartus II Schematic

------------------------------------------------------------------------------------------------------- Nhn Next >

Nhn Next >

Nhn Finish ch v mn hnh chnh.

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Quartus II Schematic

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2. Thit k mt mch in n gin ( cng XOR ) dng

Schematic trn Quartus II:

M File -> New :

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Quartus II Schematic

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2.1

Chn Block Diagram/Schematic File

Save as file : File -> Save as

Chn v nhp cng Logic

Graphic Editor cung cp mt s th vin cha nhng linh kin in t, cho

php ngi s dng chn v nhp vo schemtic. Nhp p ln khong trng bn trong
ca s Graphic Editor hoc nhp ln biu tng
nh hnh di xut hin :

trong thanh cng c. Mt ca s

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Quartus II Schematic

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T ca s ny, ta c th tm v chn nhng linh kin hay cng logic m ta mun

nhp vo ca s Graphic Editor bng cch sau khi chn linh kin th ta nhp nt
OK. Th d ta mun nhp mt cng AND 2 ng vo, ta s tm v chn and2 t Library,
sau nhn OK, ta s c mt biu tng cng AND2 xut hin trn ca s Graphic
Editor. S dng chut di chuyn linh kin n v tr mong mun bng cch nhn
chut ln linh kin v ko ri nhp chut t n xung v tr mi. Nu mun nhp
mt cng AND2 ln th hai, ta c th lm nh cch trn hoc c th copy t biu tng
c sn trn ca s bng cch nhp phi chut, ko r chut to ra mt biu tng
th hai. Ta cng c th xoay biu tng ca linh kin bng vic s dng biu tng
trn thanh cng c.

2.2

Gn ng vo v ng ra cho linh kin:

Sau khi nhp linh kin vo trong ca s Graphic Editor, ta phi gn ng vo

v ng ra cho linh kin trong mch in. Qui trnh cng tng t nh tm v nhp linh
kin, nhng biu tng ng vo hay ng ra s c tm thy trong th vin
primitives/pin. Trong hnh di, ta s nhn thy biu tng ca ng vo v ng ra
c gn vo chn ca linh kin.

Sau khi gn ng vo v ng ra cho linh kin, ta phi t tn cho chng. t

tn, ta nhp p vo t pin_name ca ng vo hay ng ra. Mt hp thoi nh hnh sau
s xut hin:
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Quartus II Schematic

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Nhp tn cho chn linh kin vo Pin name(s), ri nhn OK.

2.3

Kt ni linh kin
Nhng linh kin trong mch phi c kt ni bng dy in. Nhn chn biu

trn thanh cng c kch hot Orthogonal Node Tool. Di chuyn con tr
tng
n u ca chn linh kin, nhn v gi chut tri v ko cho n khi ng dy chm
vo chn ca linh kin no m mnh mun kt ni ti. Ch , du chm en nh th
hin cho s kt ni gia hai ng dy dn.
Vi qui trnh tng t, ta s kt ni cho ton b mch in sao cho ng vi
chc nng hot ng m ta mong mun. Nu trong qu trnh kt ni dy, ta kt ni sai
dy dn no , ta c th xa dy dn i bng cch nhn chn dy dn ri nhn
phm Delete (Del) trn bn phm. Sau khi hon thnh kt ni dy, ta nhn biu tng
kch hot chc nng Select and Smart Drawing Tool. By gi ta c th sp t
li v tr ca mch in sao cho d nhn bng cch chn linh kin hoc dy dn v di
chuyn chng n mt vi tr thch hp hn. Th d, hnh di y l mt mch in
hon chnh:

Sau khi mch in c hon chnh, ta nh lu li. Mt file thit k s c lu

di nh dng .bdf. Thi d light.bdf
.
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Quartus II Schematic

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3. Trnh bin dch

Vi d liu vo l file nh dng .bdf ( light.bdf), nhiu cng c trong phn mm
Quartus II c dng phn tch, tng hp mch c thit k phn trn, ri sau
s to ra mt file thc thi dng np ln FPGA. Nhng cng c c s dng trong
qu trnh ny c gi l trnh bin dch. thc thi qu trnh bin dch, ta thc hin cc
bc sau:
Chn: Processing -> Start Compilation hoc nhn chn biu tng
trn
thanh cng c. Sau khi qu trnh bin dch c hon tt, mt bng bo co c to ra
nh hnh di:

xem li qu trnh bin dich, ta chn : Processing -> Compilation Report hoc

nhn chn biu tng

2.4

trn thanh cng c.

Message window

Phn mm Quartus II s hin th thng tin trong sut qu trnh bin dch trn ca
s Message widow. Nu s mch in c thit k trong phn Graphic Editor hon
ton ng, th mt thng bo The compilation was successful c hin th. Trong
trng hp qu trnh bin dch xut hin li th c ngha c li xy ra trong qu trnh
thit k trn Graphic Editor. Mi thng bo tng ng vi mt li c tm thy s xut
hin trn ca s Message. Nhp p vo thng bo li ta s bit r hn v li xy
ra trn mch in. Tng t, trnh bin dch cng thng bo mt s cnh bo Warning.
Ngoi ra ta cng c th tm hiu thm thng tin v li cng nh cnh bo bng cch nhn
chn vo thng bo ri nhn phm F1 trn bn phm.
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Quartus II Schematic

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2.5

Gn pin

V ta cha thc hin gn pin trn FPGA cho linh kin trong mch in thit k
trn nn khi thc hin bin dch th trnh bin dch Quartus II gn chn ca linh kin
vi pin ca FPGA mt cch ngu nhin. Tuy nhin, gi s trong thit k cng XOR n
gin trn, sau khi thit k c bin dch v np ln FPGA, ta mun hai ng vo x1, x2
c iu khin bi hai switch SW0 v SW1 cn kt qu ng ra f s c th hin trn
led LEDG0 ( SW0, SW1, LEDG0 c ghi trn Kit). Mt khc ta bit switch SW0 c
kt ni c nh vi pin N25 ca FPGA, tng t vy switch SW1 c kt ni c nh
vi pin N25 ca FPGA v led LEDG0 c kt ni c nh vi pin AE22 ca FPGA.
thc hin c iu ta phi gn chn linh kin trn mch ( x1, x2, f) vi pin tng ng
trn FPGA ( N25, N26, AE22). gn pin ta thc hin cc bc sau:
Chn Assignments > Pins, mt ca s nh hnh di s xut hin:

Trong mc Category chn Pin. Nhp p ln mc <<new>> trong ct To. Mt

ca s nh hnh di xut hin:

Nhn chn x1 gn pin trc, tip n nhp p ln mc ngay bn phi ca x1

trong ct Location, mt ca s nh hnh di s xut hin:

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Quartus II Schematic

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Ta nhp chn PIN_N25.

Tng t, ta gn pin cho chn ng vo x2 ti pin PIN_N26, v chn ng ra f ti
pin PIN_AE22. Sau khi gn pin hon tt, ta s c nh hnh di:

Lu li kt qu gn pin: File > Save

Ta phi bin dch li thit k trn vi kt qu gn pin ny v nh ta ni
trn, v qu trnh bin dch trn, trnh bin dch Quartus II ch gn pin mt cch ngu
nhin nn s khng ng vi yu cu thit k ca ta, do ta phi gn li pin cho ng
vi yu cu ri phi chy li qu trnh bin dch. Lc ny trnh bin dch Quartus II s s
dng nhng pin m ta gn cho chn ca mch in trong thit k phn tch, tng
hp v to ra mt file thc thi vic np xung cho FPGA.
Ngoi ra ta cng c mt cch khc gn pins cho design, c bit l rt hu
ch trong thit k m c nhiu chn, ta khng th ngi gn pin cho tng chn c v s
tn nhiu thi gian, Quartus II cung cp mt phng php gip ta gn nhiu pin vo hoc
g nhiu pin ra cng mt lc bng mt file c nh dng c bit dng cho mc ch ny
l nh dng .CSV. Format ca file ny nh sau:
Nu ta dng file text to file ny, th n gin ta ch cn nhp theo mu sau:

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Quartus II Schematic

-------------------------------------------------------------------------------------------------------To, Location
x1, PIN_N25
x2, PIN_N26
f, PIN_AE22
Nu ta dng Microsoft Excel, th ta s c format nh sau:

Sau khi to file c format nh trn, ta s thc hin vic gn pin nh sau:
- Chn Assignments -> Import Assignments, mt hp thoi nh hnh di
xut hin:

Click button , ch ng dn ca file ta va to trn. Ri nhn OK.

thun tin cho ngi s dng Altera cung cp mt file CSV c tn

DE2_pin_assignments, file ny lit k tt c cc pin ca FPGA, c format nh sau:

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Quartus II Schematic

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Nu ta mun s dng file c sn ny vo vic gn pin cho thit k ca ta th mt

yu cu bt buc khi ta t tn cho chn linh kin phi trng vi tn trong ct To ca file
ny. Th d, nu ta mun hai chn ng vo ca cng XOR c iu khin bi hai
Switch 0 v Switch 1 trn Kit DE2 th ta phi t tn cho hai chn ny ln lt l SW[0],
SW[1] nh trong ct To ca file ny. Do ta phi tham kho file ny trc khi t tn
cho chn linh kin khi gn pin ta s rt thun tin l khng phi to file.csv na m
ch cn Import file c sn ny vo thi.
Sau khi gn pin xong, ta bin dch li.
- Re- compiling design : Processing -> Start Compilation
- Review Compilation report : Processing -> Compilation Report

4 M phng mch thit k :

To input waveform : File -> New -> Other Files -> Vector Waveform File

Nhn OK

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Quartus II Schematic

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Chn thi gian thc hin m phng : Edit -> End Time
Nhp thi gian thc hin m phng.
Fit windown : View -> Fit in Windown
To waveform cho inputs : Edit -> Insert Node or Bus

Chn Node Finder

Chn Filter : Pins : all

Nhn button List
Chn signal bn Nodes found ; nhn >> chuyn sang bn Selected Nodes
Nhn OK

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Quartus II Schematic

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Chn mt input signal bng cch nhp chut vo signal .

Chn biu tng mi tn con tr
Di chuyn con tr sang mn hnh waveform .
Nhn v gi chut v ko r ( left ) trong mt khong thi gian ( gi s ta mun
trong khong thi gian t 40ns -> 60 ns , SW0 signal c gi tr 1, th ta nhn ,
gi v r chut trong khong thi gian t 40ns -> 60ns.

Nhn button 1 pha bn tri mn hnh

Tng t cho nhng tn hiu inputs khc, khng to waveform cho outputs (
XXX).
Save File Waveform : File -> Save As

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Quartus II Schematic

------------------------------------------------------------------------------------------------------- Thc hin m phng : Assignments -> Setting

Chn Simulator Settings

Chn Simulation mode : Functional / Timing
Ch ng dn ca input waveform va to.
Nhn OK
To simulation netlist : Processing -> Generate Functional Simulation Netlist
Chy m phng : Processing -> Start Simulation.
Quan st waveform ca Output.

5 Programming thit k Verilog trn FPGA :

5.1

Kt ni Kit DE2 vi my tnh qua cng USB-Blaster (phi ci t driver trc ).

Bt ngun Kit DE2.
C 2 mode : JTAG v Active Serial modes

JTAG mode :
Trn Kit DE2 , chuyn Switch RUN/PROG v v tr RUN
Trn mn hnh chnh Quantus II, chn Tools -> Programmer

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Nhn Hardware Setup , chn USB-Blaster[USB-0] ( Ch : phi ci t driver

cho USB-Blater trc ).

Nhn Close
Chn Mode JTAG
Nhn Add File , ch ng dn n File .sof (c to ra khi chy Compilation).
Check box Program/Configure

Nhn Start.
Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.

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Quartus II Schematic

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5.2

Active Serial Mode :

Chn Assignments -> Devide

Chn Family : Cyclone II

Chn Available devices : EP2C35F672C6
Nhn Device & Pin Option
Chn Tab Configuration

Chn Configuration device : EPCS64 ( h EPPROM trn Kit DE2 , dng

lu chng trnh np cho FPGA mi khi power on ).
Tng t JTAG nhng bc k tip .
Trn Kit DE2 , chuyn Switch RUN/PROG v v tr RUN
Trn mn hnh chnh Quantus II, chn Tools -> Programmer
Chn Hardware Setup : USB-Blaster[USB-0]

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------------------------------------------------------------------------------------------------------- Chn Mode : Active Serial Programming

Nhn Add File, ch ng dn n File .pof ( File c to ra trong qu trnh
chy Compilation ).

Check box Program/Configure.

Nhn Start programming chng trnh cho EPPROM.
Nhn Phm Restart trn Kit DE2,
Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.

END

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