VIT

UNIVERSITY

ECE 301 - VLSI System Design

(Fall 2012)

Course Information

Prof.S.Sivanantham School of Electronics Engineering VIT University Vellore, Tamilnadu. India E-mail: ssivanantham@vit.ac.in

Course outline
CMOS Logic Design Circuit Characterization and Performance estimation Verilog HDL Basics Digital System Design using Verilog HDL Introduction to Timing Analysis

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

Course Outcome (i)

After successful completion of this course, you will have the

ability to apply knowledge of mathematics, science, and engineering in the design, and analysis and modeling of digital integrated circuits. ability to describe and model digital design using a hardware description language. ability to design and conduct experiments in digital design using Verilog HDL and able to illustrate the outcome of the design. ability to design and analyze the performance (speed, Power, Area) of CMOS digital integrated circuits for different design specifications. knowledge on Verilog HDL constructs and operators accepted in logic synthesis and show how logic synthesis tool interprets these constructs.

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

Course Outcome (ii)

Ability to compute gate sizes on a path to optimize the path delay using logic effort. Ability to analyze a given problem in Verilog HDL Ability to develop problem-solving skills in order to be able to successfully approach a digital design project of medium to high complexity in the final semester. Ability to identify career paths and requisite knowledge and skills for career change/higher studies towards Microelectronics Engineering. Ability to gain knowledge of contemporary issues on modern VLSI Design through various websites. Ability to use modern EDA tools to Simulate and Synthesize the digital designs to verify their functionality and analysis its performance.
ECE301 VLSI System Design FALL 2012 S.Sivanantham

Prerequisite
Semiconductor Devices and Circuits Digital Logic Design

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

Course Resources
Course materials are available in VIT intranet (http://intranet.vit.ac.in) Resource Syllabus Course updates Tutorials Lecture notes, supplemental readings Homework assignments Stay connected with to get updates and more useful info related to the course. Facebook group: (VLSI System Design Fall2012-13) Link to the group: http://www.facebook.com/groups/vsd2012/ CHECK IT OFTEN
ECE301 VLSI System Design FALL 2012 S.Sivanantham

Course Plan
Lectures Problem Solving Home Assignments Lab assignments to Simulate and synthesize the Digital circuits using EDA tools like Modelsim, Xilinx ISE and Altera Quartus II d by Verilog HDL using EDA tools Group Project

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

Evaluation and Grading

CAT 1 (15 %) Module 3 and 4 CAT 2 (15 %) Modules 1 and 5 Lab assignments (20%) - (individual or group of 2-3 students, depends on assignments)
Assignment -1 (5 %) Assignment -2 (5 %) Assignment -3 (10 %)

TEE (50 %)

No Re-exam will be conducted for Absentees

ECE301 VLSI System Design FALL 2012 S.Sivanantham

Assignment
Assignments will either be individual or in pairs Read the assignment to see! Assignment due at beginning of class 10% penalty for each late period of 24 hours Not accepted >72 hours after deadline

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

Lab Assignments
Lab Assignments using the Xilinx/Altera VLSI design software will be an integral part of this course. There are no separate lab times. Details of each assignment will be posted on the course website/intranet course page.

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

Our Policy
Attendance and Conduct in Class: Students are expected to attend class and be bright and cheerful with lots of questions. It will be difficult to perform well in this class without attending the lectures. Cheating in any form will not be tolerated! This includes copying homework, copying circuit design files, cheating on exams, or any other form of unethical behavior.

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

Course Tools
Industry-standard design tools: Modelsim HDL Simulation Tools (Mentor)/ Xilinx ISE/Altera Quartus II for FPGA based Design and Implementation (for Lab assignments) [optional] Virtuoso, Spectre and Assura from Cadence (based on module 1 and 2) Tutorials will be available for all the tools These tools will be required as part of homework/ Lab assignments Can do it on own time (within deadline)

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

12

Required Text Books

Neil H. E. Weste and David Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Pearson Education, 3/e 2006

Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, PHI, Second Edition,2004.

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

References
Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits: A Design Perspective, Prentice Hall India, 2nd Ed, 2002. Sung-Mo Kang & Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis and Design, Tata McGrawHill, New Delhi, 2005 John P.Uyemura, CMOS Logic Circuit Design , Springer International Edition.2005 J. Bhasker, A Verilog HDL Primer, BP Publications.

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

Study Guidelines
Active Participation in the class Doing Home Assignments on time Utilize the FPGA/SOPC Lab (Room No:TT237) and ASIC Design Laboratory (Room No:TT237A) to simulate and synthesize the Digital Design described by Verilog HDL and Analyze the CMOS circuits using Cadence EDA tools. The students are encouraged to use various kind of EDA tools available in the lab.

ECE301 VLSI System Design

FALL 2012

S.Sivanantham

Study Guidelines
Participation in guest lectures will help the students to understand the contemporary issues Students are encouraged to refer the following website in addition to their class participation and reading required texts and reference books.
http://www.vlsi-design.net/ www.asic-world.com http://www.vlsichipdesign.com http://nptel.iitm.ac.in/ ( A video course on VLSI Circuits by Prof. S.Srinivasan, A web course on VLSI Design by Prof. A.N. Chandorkar will be really helpful) http://ocw.mit.edu/courses/ (MIT OpenCourseWare is a free publication of MIT course materials that reflects almost all the undergraduate and graduate subjects taught at MIT)
ECE301 VLSI System Design FALL 2012 S.Sivanantham

ECE301 VLSI System Design

FALL 2012

S.Sivanantham