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Duolog LPDDR2 Brochure v1
Duolog LPDDR2 Brochure v1
Duolog LPDDR2 Brochure v1
OVERVIEW The Duolog synthesizable LPDDR2 model is a fully functional, configurable, and cycle-accurate model based on the Elpida E13XXE10 series that can be targeted to a range of emulation systems. The synthesizable LPDDR2 model enables the user to extensively debug their device in simulation and then conduct intensive validation in the emulation environment.
I_RESET_N I_SYSTEM_CLK I_DDR_CLK I_DDR_CLK_N I_CA I_CKE I_CS_N I_REFRESH_RATE I_TDQSCK_RANGE I_DM Bank I_CHECK_DISABLES IO_DQ Command IO_DQS IO_DQS_N O_ERROR_STATUS O_ERROR_FLAG O_REFRESH_ERROR_STATUS O_REFRESH_ERROR_FLAG O_CLOCKING_VIOLATION Error Clock sync
Memory Wrapper
Standard Library
Power
Memory
Down Monitor
Data path
Refresh
Data
All information is subject to change without notice. 2009 Duolog Technologies Ltd. All Rights Reserved.
Backdoor Interface
Product Brief
Description
The Elpida E13XXE10 series are command based LPDDR2 modules with complex sequence based functionality including Read/ Write bursts, initialization, power down sequences, pre-charge, and refresh dependencies. This model provides the LPDDR2 behaviour. The core contains a data interface Central FSM which interprets and synchronizes commands from the LPDDR2 interface and parses command sequences used for initialization and high-level functions such as refresh, power down, etc. It stores the mode register and communicates with the Address Generator to handle bank addresses, interleaving, etc. The BANK FSMs independently verify command
Evaluations
All of Duologs synthesizable BFMs are available for evaluation. Contact us at info@duolog.com to obtain an evaluation copy or to request more information.
About Duolog
Founded in 1999, Duolog Technologies is a supplier of market leading EDA tools and solutions enabling SoC Flow Automation. Our tool offering is built on Socrates, a framework which enables rapid and effective SoC integration and verification of complex designs. Tools within Socrates include SoC Register Management, Spirit-compliant SoC Connectivity, and Testbench Automation. covertest
Module Validation
scoreboard
monitor
monitor
master
Preload
driver
DUT
responder
slave
Backdoor
LPDDR2 Model
System Validation
SoC
LPDDR2 Model
Backdoor
scoreboards
drivers / monitors
transactors
Preload memory
test
Duolog Technologies, Beacon Court, Sandyford, Dublin 18. Tel: +353-1-217 8400 Fax: +353-1-217 8401 Email: info@duolog.com Web: www.duolog.com
All information is subject to change without notice. All Rights Reserved. Duolog, Helix and the Duolog logo are trademarks of Duolog Technologies Limited. Other trademarks are trademarks of their respective owners. 2009 Duolog Technologies Ltd. Registration No. 316532 VAT No. IE6336532L