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RF AMP & SERVO SIGNAL PROCESSOR

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S1L9226X

INTRODUCTION
48-LQFP-0707 As a pre-signal & servo signal processor for the DISC-MAN, S1L9226X is a low voltage, low consumption current IC that can read CD-RW, and CD-R discs and can be applied to various products, such as the CDP/VCD/CDMP3 for the DISC-MAN. It is a hard-wired free-adjustment servo, which automatically controlled the control point of the pre-signal portion.

FEATURES
RF amplifier (CD, CD-R, CD-RW applicable) Gain setting & monitoring for the CD-R, CD-RW DISC RFAMP offset adjustment Focus error amp & Febias adjustment Tracking error amp & balance, gain adjustment FOK, defect, mirror detect Center voltage amplifier APC (Automatic Power Control) RF AGC & EQ control (AGC Level Control Compatible) Enhanced EFM slice (Double Asymmetry Method) Focus servo loop & offset adjustment Tracking servo loop & offset adjustment Sled servo loop Spindle servo loop Auto-sequence Fast search mode (1 - 36000 track jump) Interruption countermeasure Focus & Tracking servo muting controlled by EFM duty check RF peaking prevention system by EFM duty check Focus, tracking, spindle loop pole move option Operating voltage 2.7V 3.3V

Power saving mode <Notice> LPC Control used by side beam signal, it related to pick-up assurance. When used pick-up, the specification is present extra.

ORDERING INFORMATION
Device S1L9226X01Q0R0 Package 48-LQFP-0707 Supply Voltage 2.7V 3.3V Operating Temperature -20C +75C

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RF AMP & SERVO SIGNAL PROCESSOR

BLOCK DIAGRAM

PDBD

48

47

42

41

40

39

EQO EFMI

4 5

RF AGC & EQ Control Focus OK Detect Defect Detect Mirror Gen

Center Voltage

Tracking Error (RW) I/V AMP

RF & Focus Error (CD-RW) I/V AMP

PDAC

VREF

EQC

RFM

RFO

PDE

PDF

EQI

38 PD 37 LD 35 LPFT 34 TEIO

DCCI 45 DCC0 46 MCP 44 DCB 43 VCC/ VDD FRSH FSET FLB

APC. Laser Control & LPC

Focus Servo Loop - Gain & Phase Compensation - Focus Search - Offset Adjust - FZC Gen.

6 7 8 9

Tracking Servo Loop - Gain & Phase Compensation - Track Jump - Offset Adjust - TZC Gen.

TZC& SSTOP 36 ATSC 33 29 TEO 28 TEM

FGD 10

Hardware Logic - Auto-Sequencer - Fast Search - Febias, Focus Servo, Tracking Offset ADJ. - Tracking Balance & Gain Adjust - Interruption Detect - EFM Muting System

Sled Servo & Kick Gen

27 SLP 26 SLO 25 SLM

29 FEO 30 FEM 23 SPDLO 24 SPDLM

FSI 11

TGU 12 Micom Data Interface Logic Decoder

EFM Comparator 18 CLVI 20 LOCK 22 ASY 21 EFM

Spindle Servo LPF

13 ISTAT

14 MCK

15 MDATA

16 MLT

17 RESET

19 WDCK

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S1L9226X

APPLICATION DIAGRAM

from pick-up

10 F 120k 391 120k 47k 683 22k 103 88k

104 220
100F

100k

272

47 F 104 150k 222

39k 104 100k 29 TEO 28 TEM 27 SLP 26

Pick-up LD PD 55k A 55k C 55k B 55k D 82k F 82k E VR VCC GND

333 36 ATSC 37 LD 38 PD 39 PDAC 40 PDBD 41 PDF 42 PDE 35 LPFT 34 TEIO 33 TZC/SSTOP 32 GND 31 FEO 30 FEM

25 SLM SPO 24 100k SPM 23 103 ASY 22 10k EFM 21 LOCK 20 WDCK 19 10k From DSP From DSP 474 10k 20k SMDP 8.2k SMDS SMEF 474 to DSP

103 43 DCB 103 44 MCP 45 DCCI 333 46 DCCO 47 VREF 683 33 F

S1L9226X

SLO

CLVI 18 RESET 17 MLT 16 MDATA 15 MCK 14 333 From Micom From Micom From Micom From Micom To Micom

1M

FRSH

48 EQC EFMI EQO RFM RFO VCC EQI

ISTAT 13 FSET FGD TGU 12 104 10k FLB FSI 11 102

1 2pF

2 682

10

104 430k

104

2pF

22k

821

47 F

104

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PIN CONFIGURATION

36 ATSC 37 LD 38 PD 39 PDAC 40 PDBD 41 PDF 42 PDE 43 DCB 44 MCP 45 DCCI 46 DCCO 47 VREF

35 LPFT

34 TEIO

33 TZC/SSTOP

32 GND

31 FEO

30 FEM

29 TEO

28 TEM

27 SLP

26 SLO

25 SLM 12 TGU SPO 24 SPM 23 ASY 22 EFM 21 LOCK 20 WDCK 19

S1L9226X

CLVI 18 RESET 17 MLT 16 MDATA 15 MCK 14

FRSH

48 EQC EFMI EQO RFM RFO VCC EQI

ISTAT 13 FSET FGD 10 FLB FSI 11

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S1L9226X

PIN DESCRIPTION
Table 1. Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Symbol RFM RFO EQI EQO EFMI VCC FRSH FSET FLB FGD FSI TGU ISTAT MCK MDATA MLT RESET CLVI WDCK LOCK EFM ASY SPM SPO SLM SLO SLP TEM TEO FEM FEO I/O I O I O I P I I I I I I O I I I I I I I O I I O I O I I O I O RF summing amp. inverting input RF summing amp. output RFO DC eliminating input(use by MIRROR, FOK ,AGC & EQ terminal) RF equalizer output EFM slice input. (input impedance 47K) Main power supply Capcitor connection to focus search Filter bias for focus,tracking,spindle Capacitor connection to make focus loop rising band Terminal to change the hign frequency gain of focus loop Focus servo input Connect the component to change the high frequency of tracking Loop Internal status output Micom clock Data input Data latch input Reset input Input the spindle control output from DSP 88.2KHz input terminal from DSP Sled run away inhibit pin (L: sled off & tracking gain up) EFM output for RFO slice(to DSP) Auto asymmetry control input Spindle amp. inverting input Spindle amp. output Sled servo inverting input Sled servo output Sled servo noninverting input Tracking servo amp.inverting input Tracking servo amp. output Focus servo amp. inverting input Focus servo amp. output pin Description

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Table 1. Pin Description (Continued) Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol GND TZC/ SSTOP TEIO LPFT ATSC LD PD PDAC PDBD PDF PDE DCB MCP DCCI DCCO VREF EQC I/O P I B I I O I I I I I I I O I O I Main ground Tracking zero crossing input & Check the position of pick-up wherther inside or not Tracking error output & Tracking servo input Tracking error integration input (to automatic control) Anti-shock input APC amp. output APC amp. input Photo diode A & C RF I/V amp. inverting input Photo diode B & D RF I/V amp. inverting input Photo diode F & tracking(F) I/V amp. inverting input Photo diode E & tracking(E) I/V amp. inverting input Capacitor connection to limit the defect detection Capacitor connection to mirror hold Output pin to connect the component for defect detect Input pin to connect the component for defect detect (VCC+GND)/2 Voltage reference output AGC_equalize level control terminal & capacitor terminal to input in to VCA Description

MAXIMUM ABSOLUTE RATINGS

Item Power supply voltage Absolute Ratings Operating temperature Storage temperature Symbol VDD VI TOPR TSTG Rating 2.7 3.3 4.5 -20 75 -40 125 Unit V V C C

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ELECTRICAL CHARACTERISTICS
Table 2. Electrical Characteristics
Spec No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Characteristics Supply current 2.7V RF AMP offset voltage RF AMP offset voltage 2 RF AMP oscillation voltage RF AMP voltage gain AC RF THD characteristic RF AMP maximum output voltage RF AMP minimum output voltage RF CDRW gain AC1 RF CDRW gain AC2 RF CDRW gain AC3 Focus error offset voltage Focus error auto voltage ISTAT state after FEBIAS control Focus positive offset 1 Focus positive offset 2 Focus positive offset 3 Focus negative offset 1 Focus negative offset 2 Focus negative offset 3 Focus Error voltage gain 1 Focus Error voltage gain 2 Focus Error voltage gain difference Focus Error RW down Focus Error AC difference FERR maximum output voltage H FERR minimum output voltage L AGC max gain AGC EQ gain AGC normal gain AGC compress ratio Symbols ICCTY Vrfo Vrfo2 Vrfosc Grf Rfthd Vrfh Vrfl GRWAC1 GRWAC2 GRWAC3 VFEO1 VFEO2 VISTAT1 Vfep1 Vfep2 Vfep3 Vfen1 Vfen2 Vfen3 GFEAC GFEBD GFE GFERWD VFEACP VFEPPH VFEPPL GAGC GEQ GAGC2 CAGC AGC_EQ Focus Error RF AMP Test Block Min. 5 -100 -300 0 15.5 2.35 1.05 1.05 1.05 -525 -50 2.2 0 10 50 -80 -100 -180 19 19 -3 0.4 0 2.3 15 -3 3 0 Typ. 10 0 -200 50 18.5 1.30 1.30 1.30 -250 0 40 60 120 -40 -60 -120 23 23 0 0.7 50 19 1 6 2.5 Max. 20 100 -100 100 23.5 5 0.85 1.55 1.55 1.55 0 50 80 100 180 0 -10 -50 27 27 3 1.0 100 0.4 22 2.5 9 5 Unit mA mV mV mV dB % V V mV mV V mV mV mV mV mV mV dB dB dB mV V V dB dB dB dB

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Table 2. Electrical Characteristics (Continued)

Spec No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Characteristics AGC frequency AGC Level control AGC RF Sel TERR gain voltage gain 1 TERR gain voltage gain 2 TERR gain voltage gain 3 TERR gain voltage gain 4 TERR gain voltage gain 5 TERR gain voltage gain 6 TERR gain voltage gain 7 TERR balance gain TERR balance mode 1 TERR balance mode 2 TERR balance mode 3 TERR balance mode 4 TERR balance mode 5 TERR balance mode 6 TERR maximum output voltage H TERR minimum output voltage L TERR RW F gain 1 TERR RW F gain 2 TERR RW F gain 3 TERR RW E gain 1 TERR RW E gain 2 TERR RW E gain 3 APC PSUB voltage L APC PSUB voltage H APC PSUB LDOFF APC current drive H APC current drive L MIRROR minimum operating frequency MIRROR maximum operating frequency Symbols FAGC AGCL AGCS GTEF1 GTEF2 GTEF3 GTEF4 GTEF5 GTEF6 GTEF7 GTEE TBE1 TBE2 TBE3 TBE4 TBE5 TBE6 VTPPH VTPPL GRWTF1 GRWTF2 GRWTF3 GRWTE1 GRWTE2 GRWTE3 APSL APSH APSLOF ACDH ACDL FMIRB FMIRP MIRROR APC & Laser Control Tracking Error Test Block AGC_EQ Min. -5.0 0.95 15.5 4.5 0.98 0.98 0.95 0.90 0.98 0.98 10.5 0.95 0.95 0.95 1.0 1.0 1.0 1.9 1.05 1.05 1.00 1.05 1.05 1.00 1.8 2.4 1.35 30 Typ. 0 1.125 19.5 7.5 2.25 1.3 1.15 1.075 1.15 1.35 13.5 1.05 1.05 1.05 1.25 1.20 1.3 1.75 1.35 1.30 1.35 1.35 1.30 550 75 Max. 2.5 1.25 23.5 10.5 4.5 1.6 1.30 1.15 1.30 1.70 16.5 1.12 1.12 1.12 1.5 1.4 1.75 0.8 2.50 1.80 1.65 1.65 2.00 1.65 1.0 1.35 900 Unit dB dB dB dB V V V V V V V HZ kHz

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S1L9226X

Table 2. Electrical Characteristics (Continued)

Spec No. 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Characteristics MIRROR AM characteristic MIRROR minimum input voltage MIRROR gain option 1 FOK threshold voltage FOK threshold voltage 2 FOK output voltage H FOK output voltage L FOK FEEQ. characteristic Defect bottom voltage Defect CUTOFF voltage Defect minimum input voltage Defect maximum input voltage Symbols FMIRA VMIRL MIRRO1 VFOKT VFOKT2 VFOHH VFOKL FFOK FDFCTB FDFCTC VDFCTL VDFCTH Defect FOK Test Block MIRROR Min. 10 -450 Typ. 400 0.1 -360 Max. 600 0.2 -300 Unit HZ V kHz mV

-450
2.2 40 2.0 1.8

-560
45 670 4.7 0.3 -

-220
0.5 50 1000 0.5 -

mV
V V kHz HZ kHz V V

Defect option gain

Normal EFM duty voltage 1 Normal EFM duty symmetry Normal EFM duty voltage 3 Normal EFM duty voltage 4 Normal EFM minimum input voltage Normal EFM duty difference 1 Normal EFM duty difference 2 EFM2 duty voltage 1 EFM2 duty symmetry Double ASY voltage 1 Double ASY voltage 2 EFM2 minimum input voltage FZC threshold voltage ANTI-shock detection H ANTI-shock detection L TZC threshold voltage SSTOP threshold voltage Tracking gain win T1 Tracking gain win T2

FDFCTG
NDEFMN NDEFMA NDEFMH NDEFML NDEFMV NDEFM1 NDEFM2 EDEFMN1 EDEFMA DEFM1 DEFM2 EDEFMV VFZC VATSCH VATSCL VTZC VSSTOP VTGWT1 VTGWT2 Interface Enhanced EFM Slicer EFM Slice

-50 45 0 -100 20 20 -50 45 -375 125 30 20 -100 -150 -155 190 90

670
0 50 50 -50 50 50 0 50 -250 250 69 60 -60 0 -90 250 150

1000
50 55 100 0 0.12 80 80 50 55 -125 375 0.12 105 100 -20 150 -5 310 210

Hz
mV % mV mV V mV mV mV % mV mV V mV mV mV mV mV mV mV

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Table 2. Electrical Characteristics (Continued)

Spec No. 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Characteristics Tracking gain win T3 Tracking gain win T4 Tracking gain win T5 Tracking gain win T6 Tracking BAL win T1 Tracking BAL win T2 Reference voltage Reference current H Reference current L F. Servo off offset F. Servo DAC on offset F. Servo auto offset F. Servo auto ISTAT FERR FEBIAS status F. Servo loop gain F. Servo output voltage H F. Servo output voltage L F. Servo oscillation voltage F. Servo feed through F. Servo search voltage H F. Servo search voltage L Focus full gain F. Servo AC gain 1 F. Servo AC phase 1 F. Servo AC gain 2 F. Servo AC phase 2 F. Servo muting F.Servo AC gain difference F. Servo AC characteristic 1 F. Servo AC characteristic 2 F. Servo AC characteristic 3 Symbols VTGWT3 VTGWT4 VTGWT5 VTGWT6 VTBWT1 VTBWT2 VREF IREFH IREFL VOSF1 VOSF2 VAOF VISTAT2 VFEBIAS GF VFOH VFOL VFOSC GFF VFSH VFSL GFSFG GFA1 PFA1 GFA2 PFA2 GMUTT GFAD GFAC1 GFAC2 GFAC3 Focus Servo VREF Test Block Interface Min. 240 140 Typ. 300 200 Max. 360 260 Unit mV mV mV mV mV mV mV mV mV mV mV mV V mV dB V V mV dB V V dB dB deg dB deg dB dB

440 340
-50 -50 -100 -100 -100 -100 0 -65 2.2 -50 17 2.2 0 0.30 -0.70 40.0 17.0 30 14.0 30 1.5 1.75 1.05 1.05

500 400
0 0 0 0 0 0 250 0 0 21.5 100 0.50 -0.50 44.5 21.0 60 17.5 60 5 2.25 1.55 1.55

560 460
50 50 100 100 100 100 550 65 50 24 0.5 200 -35 0.70 -0.30 49.0 25.0 90 21.0 90 -15 8 2.80 2.05 2.05

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S1L9226X

Table 2. Electrical Characteristics (Continued)

Spec No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 Characteristics T. Servo DC gain T. Servo off offset T. Servo DAC offset T. Servo auto offset T.Servo STAT status T. Servo oscillation T. Servo ATSC gain T. Servo lock gain T. Servo gain up T. Servo output voltage H T. Servo output voltage L T. Servo jump H T. Servo jump L T. Servo DIRC H T. Servo DIRC L T. Servo output voltage L T. Servo AC gain 1 T. Servo AC phase 1 T. Servo AC gain 1 T. Servo AC phase 1 T. Servo full gain T. Servo AC characteristic1 T. Servo AC characteristic2 T. Servo loop mutt AC SL. Servo DC gain SL. Servo feed through Sled forward kick Sled reverse kick Sled output voltage H Sled output voltage L Sled lock off Symbols GTO VOST1 VTDAC VTAOF VTSTAT VTOSC GATSC GLOCK GTUP VTSH VTSL VTJH VTJL VDIRCH VDIRCL GTFF GTA1 PTA1 GTA2 PTA2 GTFG GTAC1 GTAC2 TSMTAC GSL GSLF VSKH VSKL VSLH VSLL VSLOCK Sled Servo Test Block Tracking Servo Min. 13.0 -100 150 -55 2.2 0 17.5 17.5 17.5 2.2 0.30 -0.70 0.30 -0.70 10.5 -180 18.1 -180 32 1.50 0.40 0 11.0 0.40 -0.80 2.2 -100 Typ. 15.5 0 320 0 100 20.5 20.5 20.5 0.5 -0.5 0.5 -0.5 14.5 -135 23.1 -135 36 2.00 0.80 50 14.0 0.60 -0.60 0 Max. 18.0 100 700 70 185 23.5 23.5 23.5 0.5 0.70 -0.30 0.70 -0.30 -39 17.5 -90 26.1 -90 40 2.50 1.30 100 17.0 -34 0.80 -0.40 0.5 100 Unit dB mV mV mV V mV dB dB dB V V V V V V dB dB deg dB deg dB mV dB dB V V V V mV

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Table 2. Electrical Characteristics (Continued)

Spec No. 158 159 160 161 162 163 164 165 166 Characteristics SP. Servo 1X gain SP. Servo 2X gain SP. Servo output voltage H SP. Servo output voltage L SP. Servo AC gain 1 SP. Servo AC phase 1 SP. Servo AC gain 2 SP. Servo AC phase 2 SP.Servo AC gain 3 Symbols GSP GSP2 VSPH VSPL GSPA1 PSPA1 GSPA2 PSPA2 GSP3 Test Block CLV Servo Min. 13.5 19.0 2.2 -3.0 -120 3.0 -120 0.85 Typ. 16.5 23.0 5.0 -90 10.0 -80 3 Max. 19.5 27.0 0.5 12.0 -50 17.0 -50 5.0 Unit dB dB V V dB deg dB deg -

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OPERATION DESCRIPTION
MICOM COMMAND $0X, $1X Item D7 Focus control Tracking control 0 0 Address D6 0 0 D5 0 0 D4 0 1 D3 FS4 Focus on Anti - shock D2 FS3 Gain down Brake - on Data D1 FS2 Search on TG2 Gain set D0 FS1 Search up TG1 Gain set FZC ATSC Istat Output

Tracking Gain Setting According to Anti-Shock D7 D6 D5 D4 D3 ANTI - shock 0 0 0 0 1 1 D2 Lens. Brake - on 0 1 D1 TG2 (D3 = 1) 0 High Freq. gain down 1 High Freq. gain normal 0 Gain normal D0 TG1 1 Gain up Istat ATSC

ANTI ANTI Lens Lens shock off shock on brake off brake on

Item Tracking gain control TG1. TG2 = 1 gain up

Hex TG2 $10 $11 $12 $13 $14 $15 $16 $17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

AS = 0 TG1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TG2 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0

AS = 1 TG1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0

$13, $17, $1B, $1F (AS0) $13, $17, $18, $1C (AS1) MIRROR muting turns off when the tracking gain goes up

$18 $19 $1A $1B $1C $1D $1E $1F

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$2X D7 0 D6 0 D5 1 D4 0 MODE $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F D3 D2 D1 D0

Tracking Servo Mode TM7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 TM5 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 0 TM4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

Sled Servo Mode TM3 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 TM2 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 TM1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

Operation of mode (TM1-TM7) TM1 0 1 Track. servo off Track. servo on TM2 0 1 TM4 0 0 1 TM6 0 0 1 Sled. servo on Sled. servo off TM3 0 1 1 TM5 0 1 1 Track. kick Fwd. jump Jump off Rev. jump Sled kick Fwd kick Kick off Rev kick

TM7 (jump) 1 Lens brake on

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DIRC (DIRECT 1 Track Jump) Tracking Condition DIRC = 1 TM 654321 000000 000010 010000 100000 000001 000011 010001 100001 000100 000110 010100 100100 001000 001010 011000 101000 DIRC = 0 654321 001000 001010 011000 101000 000100 000110 010100 100100 001000 001010 011000 101000 000100 000100 000100 100100 DIRC = 1 654321 000011 000011 100001 100001 000011 000011 100001 100001 000011 000011 100001 100001 000011 000011 100001 100001

Item Tracking Mode

Hex $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F

Register $3X

Address D15-D12

Focus & Sled Level value 1X

Focus search D11 PS4 search+2 0 D10 PS3 serach+1 0

SLED KICK D9 PS2 Kick+2 0 D8 PS2 Kick+1 0

T.servo cpeak mutting D7 Mutting when above EFM11T D6 PS5 Jump +1 0 0 0 0 0 1 1 0 0 1 1 0

Tracking jump D5 PS6 Jump 1/2 0 1 0 1 0 1 0 1 0 0X (0u) 0.25X (1.25u) 0.50X (2.50u) 0.75X (3.75u) 1.00X (5.00u) 1.25X (6.25u) 1.50X (7.50u) 1.75X (8.75u) D4 PS7 Jump 1/4

0011

2X

1 0: OFF 1: ON 0 1 1 1

3X

4X INITIAL

1 0

1 0

1 0

1 1 0 0 1

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ADDRESS D15-D12 0011

INTC D3 F.Servo Cpeak Mutt Mutting when above EFM11T D2 FSETC 0 1 (104K)

FSET (Focus, tracking CVL Pole Freq. setting resistor) D1 FSET2 24K X 0 0 1 1 D0 FSET1 12K X 0 1 0 1 1 External resistor applied 140K (580K) 116K (480K) 128K (530K) 104K (430K)

INITIAL

Select (First 8 bits of 16 bits)

D15 0

D14 0

D13 1

D12 1

D11

D10

D9

D8

Istat SSTOP

Focus Servo Search Level Control PS4 Search +2 PS3 Search +1 $30XX-$33XX $34XX-$37XX $38XX-$3BXX $3CXX-$3FXX S.X2, K.X2 $35XX

Sled Servo Kick Level Control PS2 Kick +2 Kick Kick Kick Kick X1 X2 X3 X4 PS1 Kick +1 $30XX, $34XX, $38XX, $3CXX $31XX, $35XX, $39XX, $3DXX $32XX, $36XX, $3AXX, $3EXX $33XX, $37XX, $3BXX, $3FXX S.X4, K.X4 $3FXX

Data Mode (level)

Search X1 Search X2 Search X3 Search X4

Data

S.X1, K.X1 $30XX

S.X3, K.X3 $3AXX

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Auto-Sequence Mode

Address 0 1 0 0 D3 0 0 1 1 1 1 0 D2 0 1 0 0 1 1 1

Data D1 0 1 0 1 0 1 0 D0 0 1 0: FWD 1: REV

Auto-sequence cancel Auto-focus 1-track jump 10-track jump 2N-track jump M-track jump Fast search

Speed Related Command ($F00, F03)

Address D11 1 D10 1 D9 1 D8 1 D7 0 D6 0 D5 0 D4 0 x x x x D3 D2

Data D1 D0

1X Speed ($F00, $F04, $08, $F0C) 2X Speed ($F03, $F07, $F0B, $F0F)

0 1

0 1

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RAM Register Set

Item Address Blind A, E Overflow. C BRAKE. B FAST FAST INI. Control Register 0 1 INI. Control Register $52XX $51XX F K 1 PS3X SSTOP on/off Off On 1 FJTS TEO output when fast search 0 PSTZC TZC on/off Off(SSTOP) On (TZC) 1 PEAKC EFM Peaking 0 ATS ATSC on/off T.BAL ATSC 1 FEB5 0 FZCOFF FZC on/off Off On 1 FEB4 $50XX D7 0.18ms 0.36ms 23.2ms D6 0.09ms 0.18ms 11.6ms D5 0.04ms 0.09ms 5.80ms D4 0.02ms 0.04ms 2.90ms 0.72ms 1 TRSTS T.Bal & GainReset Reset Set 1 FEB3 0.36ms 0 TZCIC TZC. Input TERR FERR 0 FEB2 0.18ms 0 MCC1 EQC output RFO EQO 1 FEB1 0.09ms 0 EQR AGC IN Level 2/3 IN Normal 1 FEB0 Data D3 D2 D1 D0

Ref posi-offset(3V) Ref voltage 3V depend on voltage MSB 10mv/step 0mV +125mV 0mV +250mV 0

Febias offset FSIO offset control the option LSB off on (+150mV) 0 MSB on (-150mV) off 1

RFO nega-offset fixed unrelated voltage 10mv/step 00 01 10 11 1 LSB -250mV 0mV -125mV 0mV 1

T.Jump T-off (TEO off) 1

off

00 01 10 11 0

1 INI. Febias offset regard on control

on 0

Before control the Febias offset $51xx TZCIC is set as the FERR 1and monitored TZC output . The ISTAT output set + offset , Febias offset control in sequence. If ISTAT of TZC output set - offset, $52XX is set as the FEB2 0. After get - offset, Febias offset control in sequence. * Remark : Phase of TZC output is opposite the input.

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Address KICK D FAST R PWM DUTY PD PWM WIDTH PW

HEX $6XXX

D11 11.6ms 23.2ms

D10 5.80ms 11.6ms

D9 2.90ms 5.80ms

D8 1.45ms 2.90ms

D7

D6

D5

D4

D3

D2

D1

D0

1 11.0ms 5.43ms 0 8 32 1 32 0 X 0 0 2.71ms 1 4 16 1 16 0 X 0 0 1.35ms 0 2 8 1 8 0 1 0 0

INI. 2N TRA. N M TRA. M Fast searchT $7XXX $7XXX INI. Brake point P $CXXX INI. CLV on/off register

0 4096 16384 0 16384 0

1 2048 8192 0 8192 0

1 1024 4096 0 4096 0

1 512 2048 0 2048 0

1 256 1024 0 1024 0 X X

0 128 512 0 512 0 X X X

1 64 256 1 256 1 X X X

0 32 128 1 128 1 X X X

0 16 64 1 64 1 X 0 0

CLV on, EFM on $99X1~$99XF CLV off, EFM off $99X0

INI Notice.

The actual value may be slightly different from the set value. A set value + 4 - 5 WDCK B, D, E set value + 3 WDCK C set value + 5 WDCK N, M, T, P set value + 3 TRCNT Caution - Among the 16 settings of PWM WIDTH 'PW' only one from D3, D2, D1, and D0 can be selected. (not 4bit combination) - More than 512 tracks are not recommended when 2N track and M track are used. (algorithm possesses problem generation) - Because PWM DUTY 'PD' can have 1 - 2 errors, should be set to "set value + 2"

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AUTOMATIC CONTROL COMMAND

Tracking Balance and Gain Control

Address D7 Tracking BAL. $800X - $801X Initial V. Tracking Gain. $810X - $811X Initial V. 0 0 0 0

Address D6 D5 0 D4 B4 0 0 G4 1 D3 B3 1 G3 0 D2 B2 1 G2 0

Data D1 B1 1 G1 0 D0 B0 1 G0 0

Tracking Balance and Gain Control Window & APC ON/OFF

DATA ADDRESS D7 STGW Tracking gain control windows $84X TGL 250mV 150mV INITIAL 0 TGH 200mV 300mV D6 STBW Tracking balance control windows ISTAT -20mV-20mV -30mV-30mV 0 OFF ON 0 OFF ON 0 OFF ON 0 D5 F.S.O.C D4 F.E.O.C D3 LDON

F.Servo FB.BIAS offset control offset control

$85

LD ON/OFF

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Additional Register Set

D3 RSTS $86X Focus servo offset DAC reset

D2 EQOC EQ0 offset Vref(1) VCC follow(0) Normal Buffer 1

D1 DFCT1 Defect input gain

D0 DFCT2 Input offset addition &87X

D3 DIRC Direct 1 track JUMP

D2 RSTF Focus error DAC RESET

D1 AGCL EQ0 output level UP

D0 EQB EQ respose GM

0 1 INITIAL

Reset Set 1

1.5X 1X 1

VR+0.25V VR+0.35V 1

0 1 INITIAL

ON OFF 1

Reset Set 1

UP Normal 1

12u 18u 1

$8EXX Focus & Tracking Servo Filter Control Command

Data Address $8EXX D7 D6 D5 D4 T. Servo Phase shift 0: low frequency 1: high frequency On Off 1 On Off 1 On Off 0 D3 D2 D1 D0

CLV Freq. movement 0: low frequency 1: high frequency On Off 1 On Off 0

Fcous freq. movement 0: low frequency 1: high frequency On Off 1 On Off 1 On Off 0

0 1 Initial V.

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$8FXX Tracking Servo Offset Control Command

Data Address $8F00 $8F1F D7 D6 D5 D4 D3 D2 D1 D0

Tracking servo offset control command 8F(000XXXXX) $8F1F $8F00 (-160mV +160mV) Control window is used with the balance window and monitors the ISTAT output Because tracking offset of approximately +30mV - +50mV is ideal in the system, consider the control setting by raising to ($8F1F $8F00) 3 - 5 steps after controlling the offset to 0mV. <Notice> Consider the measure setting by $8010 command of tracking switch and $811F command of tracking gain switch after $24 command. 1 0 0 0 0

Initial V.

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Photo-Diode I/V AMP Gain Setting for CD-R and CD-RW

DATA D7 Address Focus gain down D6 RWC3 1.5X D5 RW2C 2.0X D4 RWC1 1.25X RFO only 1 0 1 0 1 0 1 0 up RF & FERR GAIN I/V AMP Equivalence resistance Input resistance 55K Gain RFO ONLY GAIN Summing Resistance RFO Feed resistance ratio 22K RFO TOTAL RFO LOOP TOTAL RFO total 9.33 14.61 19.45 24.73 24.73 30.00 34.84 40.33 Compare to F 1.00 1.56 2.08 2.65 2.65 3.21 3.73 4.32

$82XX 07(0F) 06(0E) 05(0D) 04(0C) 03(0B) 02(0A) 01(09) 00(08) 0 1 INITIAL

RFO Focus error 1 1 1 Focus gain down bit 1 0 0 0 0 down up 1 1 0 0 1 1 0 0 up

1 stage gain 58.5K 91.5K 121.75K 154.75K 154.75K 187.75K 218.00K 251.00K 1.06 1.66 2.21 2.81 2.81 3.41 3.96 4.56

2 stage gain 10K 10K 10K 10K 10K 10K 10K 10K 22K/10K=2.2 22K/10K=2.2 22K/10K=2.2 22K/10K=2.2 22K/10K=2.2 22K/10K=2.2 22K/10K=2.2 22K/10K=2.2

normal normal normal normal Set the 8 when CD-RW mode 1 1 1 1

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Tracking Error CD-RW Mode Gain

DATA D3 Address SPEAK RWC8 1.5X RWC7 2.0X RWC6 1.5X TE
difference

D2

D1

D0

Tracking Error Input I/V AMP Resistance equivalence Resistance Difference 82K gain resistance 1 stage gain 391K 583K 786K 979K 979K 1171K 1374K 1567K 1.06 1.66 2.21 2.81 2.81 3.41 3.96 4.56 Tracking feed resistance ratio 22K

Terr total TERR LOOP TOTAL Terr total 3.392 5.312 7.07 8.992 8.992 10.91 12.67 14.592 compare to 7 1.00 1.56 2.08 2.65 2.65 3.21 3.73 4.32

$82XX 07(0F) 06(0E) 05(0D) 04(0C) 03(0B) 02(0A) 01(09) 00(08) 0 1 INITIAL 88K 44K 0 EFM Duty Check Freq.

Tracking error gain 1 1 1 1 0 0 0 0 up Norma l 1 1 1 0 0 1 1 0 0 up Norma l 1

2 stage gain 30K 30K 30K 30K 30K 30K 30K 30K 96K/30K=32 96K/30K=32 96K/30K=32 96K/30K=32 96K/30K=32 96K/30K=32 96K/30K=32 96K/30K=32

1 0 1 0 1 0 1 0 up Normal 1

Set the 0 (4.01X) when CD-RW mode setting (because need long lead in time to check 8 setp)

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ISTAT output Monitor Select Mode & RFO Offset Control.

DATA Address D7 MGA1 $83XX 0 1 INITIAL Mirror input gain 2X 1.5X 1 D6 MGA2 Mirror bias addition off on 0 Solution The monitor output in the table above is set as the focus error output and the focus error output level comparison $81XX is sent to ISTAT1 and ISTAT2 to allow the micom to monitor the focus error output. After $81XX is sent, it possible to monitor because the tracking gain window comparator are used commonly. With search command ($47), if the intensity of radiation set its target, focus search level is 1Vp-p, and peak value is 0.5V. As the table below, windows level transmit $84CX $513X command, ISTAT1 monitored at 500mV ISTAT output mode GSEL $844X $84CX CSTAT 1 0 INITIAL. 0X 2X 3X ISTAT 4X $841 $842 $CXXXX $80XX $81XX $8FXX $99XX $9900 CLV OFF Auto SEQ BUSY signal Focus Error Offset window Focus Servo Offset window Tracking gain window (TGL) Tracking Balance window Tracking Gain window (TGH) Tracking Servo offset window $9901 - $991F CLV ON CLV Command decording 250mV 150mV 5X Cpeak
FSDFCT

D5 RFOC T.Gain win input select focus error T.Gain 1

D4 TOCD Tracking offset comtrol on/off off on 1

D3 EMODEC EFM slice mode Double ASY Vref 1

D2 CSTAT ISTAT output option CSTAT CSTATB 1

D1 RFBC RFO offset FOK select FOK RFO offset 0

D0 GSEL T.Gain windows sel 200/300mV 400/500mV 0

Command. CD-RW Detect Method focus error CD-RW distinction

GSEL(TGH) TGL 0 200mV 300mV 6X FZCB

MIRROR

1 400mV 500mV 7X TZCB

DFCINT

Use the 6 types tracking gain window to distinguish the CD and CDRW disc. 1X ATSC FOK, LOCK or output 1 ISTAT output Change the ISTAT output by CSTAT Change the ISTAT output by CSTAT Change the ISTAT output by CSTAT

1 FOK TRCNT SSTOP

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RF AMP & SERVO SIGNAL PROCESSOR

AUTO-SEQUENCE
This function executes the chain of commands that execute auto-focus, track jump, and move. MLT latches the data at time L, and ISTAT is L during auto-sequence. It output H upon. AUTO FOCUS Flow-Chart

Auto Focus

Focus Search UP

FOK = H YES FZC = H YES FZC = L YES Focus Servo ON

NO

NO

During Blind "E" time set by register 5, FOK and FZC executions repeat until they become "H".

NO

END

Timing Chart Auto-focus receives the auto-focus command from the MICOM in the focus search down state and focus search up. The SSP becomes focus servo on when FZC changes to L after the internal FOK RZC satisfy 'H', all the time set blind 'E' (Register $5X). All the internal auto focus executes ended. And this status is sent to micom through the ISTAT output.
$47 Latch MLT FOK
Blind Time E FOK, FZC -> H

FZC

Focus Output ISTAT Internal STATUS

Search UP Search DOWN

Focus Servo ON

$02

$03

$03

$03

$08

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1 TRACK JUMP {$48(FWD), $49(REV)} Flow-Chart

1 Track Jump

Track Jump Sled Servo OFF

Forward jump when $48 and reverse jump when $49 Wait using the WDCK reference clock for blind "A" time, set by register 5. (1 WDCK = 0.011mS)
NO

WAIT (Blind A)

Trcnt = YES Track REV Jump

WAIT Brake "B"

Repeat check of whether TRCNT is continuously in "H" state with the WDCK reference clock for the brake "B" time, set by register 5, at the TRCNT rising edge.

Track, Sled Servo On

END

1 Track Jump Timing Chart {$48(FWD), $49(REV) inside ( ) Reverse}

$47 ( $49) MLT TRCNT

Blind Time A WAIT Blind Time B Trcnt "H"

Tracking Farward Jump

Track Output Sled Output ISTAT Internal STATUS

Track Servo ON Sled Servo ON Sled Servo OFF

Track Servo ON Tracking Revrese Jump Sled Servo ON

$25

$28 ($2C)

$28 ($2C)

$2C ($28)

$25

Receives $48 ($49) for 1 track jump and sets the blind and brake times through register $5X.

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RF AMP & SERVO SIGNAL PROCESSOR

10 TRACK JUMP {$4A(FWD), $4B(REV)} Flow-Chart

10 Track Jump

Track FWD Jump Sled FWD Kick

Foward jump & kick when $4A and reverse jump & kick when $4B. Wait using the WDCK reference clock for blind "A" time, set by register 5. (1 WDCK = 0.011mS)
NO

WAIT (Blind A)

Trcnt = 5 YES Track REV Jump, Sled FWD Kick

Tracking reverse jump & sled forward kick when $4A and tracking forward jump & reverse kick when &4B.
NO

C = Over Flow? YES Track, Sled Servo ON

Repeat check of TRCNT 1's cycle with the WDCK reference clock to determine if the cycle is long than the overflow "C" time, set by register 5.

END

10 Track Jump Timing Chart {$4A(FWD), $4B(REV) inside ( )Reverse }

$4A ( $4B) MLT TRCNT

Blind Time A WAIT Trcnt 5 Count Over Flow Time C Trcnt 1's Time Check Track Servo ON Tracking Revrese Jump Sled Forward Kick Sled Servo ON

FWD REV

Tracking Forward Jump

Track Output Sled Output ISTAT Internal STATUS

Track Servo ON Sled Servo ON

$25

$2A ($2F)

$2A ($2F)

$2E ($2B)

$25

10 track jump executes the tracking forward jump up to trcnt 5track count and turns on the tracking and sled servos after a tracking reverse jump until trcnt 1's cycle is longer than the overflow 'C' time. This operation checks whether the actuator speed is sufficient to turn on the servo.

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2N TRACK JUMP Flow-Chart

2N Track Jump
Track FWD Jump, Sled FWD Kick

Foward jump & kick when $4C and reverse jump & kick when $4D. Wait using the WDCK reference clock for blind "A" time, set by register 5. (1 WDCK = 0.011mS)
NO

WAIT (Blind A)

Trcnt = N? YES Track REV Jump, Sled FWD Kick C = Over Flow? YES WAIT (Kick "D") Track Servo ON, Sled FWD Kick Tracking & Sled Servo ON

Tracking reverse jump & sled forward kick when $4C and tracking forward jump & reverse kick when $4D.
NO

Repeat check of TRCNT 1's cycle with the WDCK reference clock to determine if the cycle is longer than the overflow "C" time, set by register 5. When $4C, the sled forward kick continues for KICK "D" time. When $4D, the sled reverse kick continues for KICK "D" time.

END

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2N Track Jump Timing Chart {$4C(FWD), $4D(REV) inside ( ) Reverse }

$4C ( $4D)

MLT TRCNT
Blind Time A WAIT Trcnt N Count C Over Flow Time C Trcnt 1's Cycle Time Check Track Servo ON Tracking Revrese Jump Sled Forward Kick Kick Time D Sled FWD Kick for D Time Sled Servo ON C Q Data Read Enable FWD REV

Tracking Forward Jump

Track Output Sled Output

Track Servo ON

Sled Servo ON

ISTAT Internal STATUS $25+$17 $2A ($2F) $2A ($2B)

$2E ($2B)

$26($27)

$25+$18

Similar to 10 tracks and executes by adding sled kick by the amount of kick 'D' time and the servo turns on after lens brake starts.

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M TRACK JUMP {$4E(FWD), $4F(REV)} Flow-Chart

M Track Jump

Track Servo OFF, Sled FWD Kick

Sled FWD kick when $4E and REV kick when $4F. Wait using the WDCK reference clock for blind "A" time, set by register 5. (1 WDCK = 0.011mS)
NO

WAIT (Blind A)

TRCNT = M? YES Tracking & Sled Servo ON

Count trcnt with the clock for M amount, set by register 7.

END

M TRACK JUMP TIMING CHART {$4E(FWD), $4F(REV) INSIDE () REVERSE}

$4E ( $4F) MLT TRCNT

Blind Time A WAIT Trcnt N Count Track Servo ON Tracking Servo OFF Treck Servo ON

FWD REV

Track Output

Sled Output

Sled Servo ON

Sled Forward Kick

Sled Servo ON

ISTAT Internal STATUS $25 $22 ($23) $22 ($23) $22 ($23) $25

Makes Trcnt to clock and counts to the value of M count, set by register 7, to execute sled kick.

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FAST SEARCH Flow-Chart

Fast Search Track Servo ON, Sled FWD Kick WAIT (Blind F)

Sled forward kick when $44 and sled reverse kick when $45.

Track FWD Jump, Sled FWD Kick WAIT (Blind K) NO

Tracking forward kick jump and sled forward kick when $44 and tracking reverse jump and sled reverse kick when $45 Execute the above conditions until TRCNT is the same as the brake point "P" count value, set by register 7. Repeat checks Trcnt, until Trcnt equals T set by register 7, like the PD and PW set by register 6, PWMs duty is decided with the PWs PWM1 period width used as the period, and PDs high. Low duty used as standard 4 bits (number selected from 0 - 15) When $44, the sled forward kick continues for kick "R" time. When $45, the sled reverse kick continues for kick "R" time.

Trcnt = P? YES Track FWD Jump, Sled FWD PWM Kick

Trcnt = T? YES Track Servo ON, Sled REV Kick WAIT (REV. Kick "R") Tracking & Sled Servo ON END

NO

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FAST SEARCH TIMING CHART {$44(FWD), $45(REV) INSIDE () REVERSE}

$44 ( $45) MLT TRCNT

Blind Time F WAIT Blind K WAIT

$5XX1 Tracking Servo Mutt

FWD REV
Trcnt P Count Trcnt T Count Kick "R" Walt

Track Output

Sled Servo ON

Tracking Forward Jump

Track Servo ON

Sled Output

Sled Servo ON

Sled Forward Kick

Sled servo Kick

Sled Servo ON Sled REV Kick

ISTAT Internal STATUS $25+$17 $26 ($27) $2A ($2F) $26 ($27) $25+$18

To Note During use of Auto-Sequence 1. Must send tracking gain up and brake on ($17) during 1, 10, 2N, track jump, and fast search. 2. Before the auto-sequence mode, MLT becomes 'L' and sequence operation executes at the initial WDCK falling edge after data latch. 3. During play, determine as FOK and GFS, not ISTAT. 4. Tracking gain up, brake, anti-shock and focus gain down are not executed in auto-sequence, and separate command must be provided. 5. If the Auto-sequence does not operate as Istat Max time over, apply $40 and use after clearing the SSP internal state. 6. 7. 8. 9. The above indicated WDCK receives 88.2kHz from DSP. (2x 176kHz) The auto-sequence internal trcnt and the actual trcnt are slightly different. Problems can be generated in the algorithm for 2N and M tracks if jump of more than 512 tracks are attempted; therefore, use them for less than 512 track jumps, if at all possible. Use the fast-search algorithm for more than 512 tracks, if possible.

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TRACKING BALANCE CONTROL CONCEPT

In tracking balance control, the micom compares and monitors the previously set DC voltage window and the tracking error DC offset, extracted from the external LPF for automatic control.

F F Beam E E Beam FDL FT2 Gain adjust 5bit Arrary 5bit (B4-B0) from Micom I/V AMP

5 bit arrary Gain control RH

Vdc RH

+ + -

AND TBAL RLO Logic

RHO

ISTAT1

MIRROR D TZC TE1 LPF LPFT CK

Summary of Operation When the focus and spindle servos are on, tracking balance control turns off the tracking and servo loops to open the tracking loop, extracts the DC offset by sending the error signal, passed through the optical pick-up and tracking error amp, through the external LPF, then this offset to the previously set window comparator level, and then informs of the completion the balance control to the micom through the ISTAT, when the dc offset of the tracking error amp in window is extracted. At this time, Tracking E beam-side I/V amps gain is selected by MICOM, and the 5-bit resistance arrays resistance value is selected by the 5-bit control signal. The values that MICOM applies are 00000 11111. If you select the switch, TESO DC offset increases the (2.5VV) (2.5V + V) one step at a time, to enter the pre-selected DC window level. When it enters that level, the balance adjust is completed, and the switch condition is latched at this time Because the TESO signal frequency is distributed up to 2kHz, the DC offset that passed through the LPF is not a correct value, if a DC component exists, and therefore, micom monitors the window output when the TESO signal frequency is above 1kHz. At this time, the frequency check the ISTAT pin. When TBAL output is H, balance control is complete.

Vdc < RLI <RHI RHO RLO TBAL (AND gate) H L L

RLI < Vdc < RHI H H H

RLI < RHI < Vdc L H L

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RHI: High level threshold value RLI: Low level threshold value Vdc: Window comparator input voltage TBAL: And gate output value of the window comparator output An Example of Tracking Balance Control Out of $8000 $801F 32 steps, the upper and lower 32 steps are used and recommand the CLV to CLV-P mode. After receiving $8110 as the gain when the focus and tracking are on, the control flow checks TRCNT frequency in ISTAT to see if the more than 7 TRCNT entered during 10ms. If yes, it checks the ISTAT, if no, it checks the number of TRCNT three times and goes on to the ISTAT check. Repeats fail, it raises the balance switch by 1 step. If ISTAT does not immediately go to H, it for 10 ms during ISTAT check after which it check whether ISTAT is H continuously for 10ms, is repeated three times. If the three repeats fail, it raises the balance switch by 1 step. The above wait 10 ms while running the system. It finds the average of the values obtained the three repeated execution of the entire above balance control. If only the balance values are from two of the three repeats, these values are averaged. If only two out of the three tries were successful in getting a balance value, average the two values. Set as balance switch, this average value +2. This is because the balance for the system and the minus value for the DC is stable in the system. Precision is important in balance adjust, and about 1+2 sec is spent as adjust time, which is accounted for. Balance Control Flowchart 1

Balance ADJ. Start $8000 Other Method - Can balance adjust while moving tracks - $F03 easy to trcnt freq check in the 2X mode -20mV - +20mV $84 X0XX -30mV - +30mV $84 X1XX Almost 20mV

Start - Environment Setting Focus on $08 Spindle on CLV-P mode Tracking off $20 Sled off gain $8110 Balance Window Level Setting

Repeat 3 times Change switch if failure after 3 repeats

NO

Balance ADJ. Switch Incnease by 1 step $8000 -> $801F

Check to see if TRCNT is 7 for 10ms B0 to B4 Switch Control

NO YES

ISTAT = H?
YES

Is ISTAT = H? Check if ISTAT is H after waiting 10ms repeat 3 times Change switch if failure after 3 repeats

If finds the average of the values obtained the three repeated execution of the entire above bacance control. If only two out of the three tries ware successtial in getting a bacance value, average the two value.

Present Control Value +2 Step then, ADJ end.

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Balance Control Flowchart 2

Balance ADJ. Start $8000 Other Method - Can balance adjust while moving tracks - $F03 easy to trcnt freq. check in the 2X mode -20mV - +20mV $84 X0XX -30mV - +30mV $84 X1XX

Start Environment Setting - Focus on $08 - Spindle on CLV-P mode - Tracking off $20 - Sled off gain $8110 Balance Window Level Seting

Balance ADJ. Switch Incnease by 1 step $8000 -> $801F

TRCNT Freq is High Enough? B0 to B4 Switch Control

NO YES

NO

1kHz Check

ISTAT = H?
YES

End ADJ.

When Tracking Balance The balance adjust is from $8000 to $801F, and the switch mode is changed one step at a time by 16-bit data transmission. After adjustment, a separate latch pulse is not necessary. If the Trcnt freq. is not high enough, the balance control can be adjusted at $F03 applied 2x mode . Here, we have suggested tracking off status for the balance adjust, but the same amount of flow can be balance adjusted while in track move. Among the 16 bit data, the tracking balance window setting level can be selected from 0: -20 mV +20mV 1: -30mV +30mV through the D6 bit. When the tracking balance adjust is complete, the tracking gain control starts.

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Tracking Balance Equivalent Resistance

Tracking Balance Data TSIO offset F equivalent Res. 391K 391K + 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K E equivalent Res. 480K 475K 468K 463K 455K 451K 444K 439K 433K 426K 421K 415K 409K 403K 397K 391K 385K 380K 374K 368K 361K 357K 350K 344K 336K 332K 327K 321K 315K 309K 303K 298K

Fixed Resistance and Parallel Resistance 100K/ 5bit R 15.22K 15.6K 16.1K 16.5K 17.2K 17.6K 18.3K 18.9K 19.5K 20.4K 21.0K 21.9K 22.7K 23.7K 24.7K 25.9K 27.1K 28.5K 30.0K 31.7K 33.9K 35.8K 38.3K 41.1K 44.5K 48.4K 52.8K 58.3K 65.1K 73.6K 84.8K 100K 5bit equivalence 17.9K 18.6K 19.3K 19.7K 20.8K 21.5K 22.4K 23.3K 24.3K 25.5K 26.6K 28.0K 29.4K 31.1K 32.9K 35K 37.2K 39.9K 43.0K 46.6K 51.4K 56K 62.2K 70K 80.4K 93.9K 112K 140K 187K 280K 560K 0K 35K

Variable Resistance (5bit) 70K 140K 280K 560K Comments

$8000 $8001 $8002 $8003 $8004 $8005 $8006 $8007 $8008 $8009 $800A $800B $800C $800D $800E $800F $8010 $8011 $8012 $8013 $8014 $8015 $8016 $8017 $8018 $8019 $801A $801B $801C $801D $801E $801F

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

1 0 1 0 1 0

252K F Equivalence Resistance

13K

26K

252K

13K

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 70K//35K = 23.3K 280K//140K = 93.3K 560K//280K = 186.6K 140K//35K = 28K 280K//35K = 31.1K 560K//35K = 32.9K 140K//70K = 46.6K 280K//70K = 56K 560K//70K = 62.2K 1//2 = 18.56K 10//560K = 17.96K 1 2 3 4 5 6 7 8 9 10
E Equivalence Resistance 5bit

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TRACKING GAIN CONTROL CONCEPT

F F Beam E E Beam I/V AMP 5bit (G4-G0) From Micom I/V AMP

Arrary Controlled by 5bit Switch

GHI Vac GLI

+ + -

TGH

AND TGO TGL Logic

INTAT To Micom

TE1 LPFT

LPF

Operation Summary Tracking gain control is executed by comparing the previously set gain set value of the window with the only the pure AC component of the signal TEIO (DC+AC) , which was extracted the resistance divide of the tracking error amp output, passed through the LPF and DC offset . The resistance divide regulates the gain by changing the 5 bit resistance combination with micom command. The tracking gain control is executed under the balance control, the same of focus loop on, spindle servo on, tracking servo off and sled servo off and controls amount of optical pick-up reflection and tracking error amp gain. External LPF cut-off freq. Is 1o 10Hz - 100Hz. The window comparator comparison level can be selected between +150mV - +300mV and +250mV - 200mV using the micom command. TGL outputs the +150mV and +250mV comparator outputs to TRCNT. TGH outputs the +300mV and +200mV comparator outputs to ISTAT. Vac < GLI <GHI TGH (ISTAT output) TGL (TRCNT output) H L GLI < Vac < GHI H H GLI < GHI < Vac L H

Gain control completes control when TGL output is H.

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1 Window Input GHI GLI

Vac

TGH (pin19)

TGL (pin18)

Tracking Gain Control In balance control, 16 bit data transmission changes the switch mode by 1step from $811F $8100, and , after adjustment, a separate latch pulse is not needed. The H duty check reference of TGL output of Trcnt output is above 0.1ms. The most appropriate method is chosen among the 4 control modes listed besides the ones above for control. Among the 12 bit data, the tracking balance window setting level can be selected from 0: +250mV (TGL) - +200mV (TGH), 1: +150mV (TGL) - +300mV (TGH) through the D3 bit. When the tracking gain adjust is complete, it enters the tracking & sled servo loop and TOC read.

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Gain Control Flowchart 1

Gain ADJ. Start $83F

Start - Environment Setting Focus on $08 Spindle on, CLV-P mode Tracking off $20 Sled off Gain Window Level Setting

Separate environment setting is not required when controlling the gain after controlling balance +150mV - +300mV $84 1XXX +250mV - +200mV $84 0XXX

32 TEP reduction of gain ADJ. Switch from $811F -> $8100

G0 to G4 Switch Control
NO

ISTAT = H?

YES

End ADJ.

In gain control, the micom command from $811F $8100 successively executes the down command and goes status 1 to 2 3. If it reaches status 2, control ends. Gain Control Method 1 The micom monitors the TGL output of ISTAT and, when it detects the output's H duty (0.1ms), ends. The window comparator level at this time is +150mV - +300mV. Gain Control Method 2 The micom monitors the TGH output of ISTAT and, when it detects the output's H duty (0.1ms), ends. The window comparator level at this time is +150mV - +300mV. Gain Control Method 3 The micom monitors the TGL output of ISTAT and, when it detects the output's H duty (0.1ms), ends. It changes the window comparator level at this time from +150mV - +300mV to +250mV - +200mV. Then it remonitors the TGL output of ISTAT, and, if it detects the output's H duty (0.1ms), control ends. If it latches the middle command between the previous micom command value and latter command value, +200mV gain control becomes possible. Gain Control Method 4 The micom monitors the TGL output of ISTAT and, when it detects the output's H duty (0.1ms), it down the micom command by 1 and control ends. The window comparator level at this time is +150mV - +300mV. Gain Control Method 5 Gain control is set to 32 steps in total and gain window is set to +250mV. (That is, start from $811F and head toward $8110) after setting $811F, it monitors the ISTAT to check whether five ISTAT were detected for 10ms. If yes, control ends, and, if not, it as gain switch is lowered by 1 step. The above process is repeated three times and the average value obtained from this repetition set as the gain control switch.

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Gain Control Flowchart 2

Gain ADJ. Start $811F

Start - Environment Setting Focus on $08 Spindle on, CLV-P mode Tracking off $20 Sled off Balance Window Level Setting

Separate environment setting is not required when controlling the gain after controlling balance +150mV - +300mV $84 1XXX +250mV - +200mV $84 0XXX

32 TEP reduction of gain ADJ. Switch from $811F -> $8110

G0 to G4 Switch Control
NO

Are there 5 ISTAT for 100ms?

YES

Gain switch seting after averaging the 3 repeats

End ADJ.

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Tracking Gain Equivalent Resistance

Tracking Gain Data $811F $811E $811D $811C $811B $811A $8119 $8118 $8117 $8116 $8115 $8114 $8113 $8112 $8111 $8110 $810F $810E $810D $810C $810B $810A $8109 $8108 $8107 $8106 $8105 $8104 $8103 $8102 $8101 $8100 TERR Gain 0.096 0.272 0.428 0.567 0.662 0.777 0.882 0.977 1.043 1.144 1.200 1.269 1.317 1.378 1.434 1.487 1.548 1.636 1.714 1.783 1.860 1.888 1.941 1.988 2.021 2.0625 2.100 2.134 2.158 2.189 2.217 2.243 TERR Gain 96K/32K x 3.0 5Bit Gain Ratio 0.032 0.090 0.142 0.189 0.220 0.259 0.294 0.325 0.347 0.381 0.400 0.423 0.439 0.459 0.478 0.495 0.516 0.545 0.571 0.594 0.620 0.629 0.647 0.662 0.673 0.6875 0.700 0.711 0.719 0.729 0.739 0.747 Proportional Resistance 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K Combined Resistance 0.5K 1.5K 2.5K 3.5K 4.25K 5.25K 6.25K 7.25K 8.0K 9.25K 10.0K 11.0K 11.75K 12.75K 13.75K 14.75K 8.0K 9.0K 10.0K 11.0K 12.25K 12.75K 13.75K 14.75K 15.50K 16.50K 17.50K 18.50K 19.25K 20.25K 21.25K 22.25K 7.5K 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7.5K 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 3.75K 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 2.0K 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1K 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Comments The gain at ratio is calculated in the TSIO terminal.

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EXAMPLE OF SYSTAM CONTROL

Disc Change

Power ON CLOSE

Disc Tray Check OPEN Replay TIME Loading

100ms Maximum

Focus Error Febias Automatic Control Start $878 +$87F+$841 transfer

100ms ISTAT L -> H?

100ms Maximum

Focus Offset Cancel Automatic Control Start $08+$867+(200ms wait)+ $86F+$842 transfer

100ms ISTAT L -> H?

Tracking Offset Cancel Start $8F1F -> $8F00 (ISTAT->H) Laser Diode ON LD ON, P-SUB $8560 Transmission Limit SW Check

2s Maximum

Focusing Auto-Focusing $47 Transmission NO Focus OK? FOK H? YES Spindle Servo Loop ON Tracking & Sled Loop OFF $20 Transmission NO TRY Count 3? YES Laser OFF $850 Transmission Display (no disc) Tracking Balance Adjust Standby Tracking Gain Adjust

300ms Maximum

TOC Read OK? PASS Disc 8/12Cm Check Play Back

FAIL

Laser OFF $850 Transmission Display (error), TRAY Open Standby

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FEBIAS OFFSET CONTROL

164K vb va 32K 32 + 160K 4K X1 X2 X4 X8 3K + vc + fcmpo

11

FSI

Febias offset control starts when it receives the febias offset control start command $841X from the micom. Febias offset control ends when the focus error amp output above 1/2 VCC after the focus output with 1/2 VCC at the focus error amp final output terminal. The voltage per 1 step of the focus offset control is approximately 17mV. The 5bit resistance DAC changes from 112mV up to - 112mV in 1 step, after which 1/2 step, approximately -8mV offset, is applied. The offset dispersion after febias offset control exists between -8mV - +8mV. The time per 1 step is 2.5ms; for 5 bits and total of 32 steps, the maximum required time is 128ms. Hardware performs the control from minus offset to plus offset. The febias offset re-control is when 4bit DAC is reset by $878. And Reset can be canceled only when the $87F applied D2 bit is changed from 0 1. The Febias DAC latch block reset for electrostatics and system operation is reset by Micom DATA and not by RESET terminal, the system reset.

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FOCUS OFFSET CONTROL

FSET 8 VC 3.6K 60K

+ +

to Digital

FSI 11 DFCTI FS3 FGD 10 580K

FZC I 20K

31 FEO

48K

Focus Phase Compensation FS2B

82K 40K
+

FS4B 470K 40K

30 FEM 10K 50K

+ -

PS 4 X1 X2 X3 X4 9 FLB 0 0 1 1 3 0 1 0 1

5K FS1

7 FRCH

Focus Offset control starts when it receives the Focus Offset control start command $842X from micom. Focus Offset control ends when the focus error amp output below 1/2VCC after the focus output with 1/2 VCC at the focus error amp final output terminal. The voltage per 1 step of the focus offset control is approximately 40mV. The 4 bit resistance DAC changes from 320mV up to -320mV in 1 step, after which 1/2 step, approximately -20ms offset, is applied. The offset dispersion after Focus offset control exists between -20mV - +20mV. The Febias Offset can be changed in 10mV step within the micom's 100mV range after focus offset control. The required per 1 step is 2.5ms; for 4 bits and total of 16 steps, the maximum required time is 128ms. For focus offset readjust, 4-bit DAC is reset by $867, and reset can be canceled only when the $86FX applied D3 bit is changed from 0 1. The Febias DAC latch block reset for electrostatics and operation error is reset by micom DATA and not by RESET terminal, the system reset.

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FEBIAS OFFSET SETTING Febias Control The FEBIAS offset control is automatically controlled to 0mV and can be controlled to 200mV. After the focus offset automatic control ends after FEBIAS offset automatic control, the command sets the internal positive and negative offsets in 20mV units to the micom. RF SUMMING AMPLIFIER APPICATION The RF I/V AMP can be controlled to 0.5X 8Step up to 1X - 4X CD-R and CDRW. The information related to CDR, CDRW disc detector is output as RFO level through the ISTAT. The RFO offset control is installed to prevent RF level clipping during low RFO voltage.

33pF CDRW Gain Sel

1

RFM 10K

22K 2pF

PDAC 39

RFO

CDRW Gain Sel 10K

PDBD 40

RF Offset Control

IV AMP

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RF EQUALIZE & AGC

Vin (t) Vcagc (t)

Modulator
Vo(t) =

Vo (t)

3x Gain AMP

HPF (3dB: 50kHz)

R5 (7.5K) Vcagc(t) Vin (t) tanh ( R6 (5.5K) 2Vt

Vin(t) = 0.73x (RFO)

EQO-AGC Output Iout = 2gm (Vid/2) = gm * Vid = (Iref) * (Vid/Vt) = Iref * (Vp-Vn)/Vt

V = I/C (115pF) Vp + Vn

if Vn > Vp Vcagc Increment (tanh (1-X)) if Vn < Vp Vcagc Decrement (tanh (1+X))

I/V Converter Control Range I * 10K

Full Wave Rectifier (RF Peak Envelope)

tanh tanh tanh tanh 0.1 = 0.5 = 0.1 = 2.0 = 0.1 0.462 0.7 0.964

Vref

The modulator output, which had the Veqc's Tanh term multiplied at the input, passes through the approximately 3X gain terminal to the ARF pad. On the one hand, the output is - rectified as it passes through the HPF having 50kHz pole frequency and follows the peak envelope the RF level. At this time, the pole frequency of the HPF is set to 50kHz so that the 3T - 11T component can pass through without attenuation. The RF level peak value is integrated at the 's CAP node after wave rectification. If this peak value is less than the already set voltage comparison, sinking current is output and, if not, sourcing current is output. The maximum peak value at this time is 10uA, which is I/V converted and applied as the modulator control voltage. Under the sinking condition, the Vcagc increases to 1outx10K and multiplied by Tanh (1-X); the sourcing condition, Vcagc decreases to Iout x10K and multiplied by Tanh (1+X), where X is (Veqc/2Vt). Overall, after detecting the 3T and 11T levels by full-wave rectification, it is compared to Tanh using the modulator and multiplied to the gain to realize the wave-form equalize. The above is related to the AGC concept, which means that a specific RF level is always taken

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OTHER BLOCK Tracking Error Amplifier The side spot photo diode current input to terminals E and F passes through the E Loop I-V and F Loop I-V Amps. It is then converted into voltage, in order to gain the difference signal in the Tracking Error Amp. This portion can perform 0.5X 8 step gain control up to 1X-4X for CD-R and CD-RW. Has the micom programming, which controls the balance by controlling gain at the E terminal and controls the gain at TEIO.

TEIO 34

LPFT 35

PDF 41

CD-RW, CD Gain Sel CD-RW, CD Gain Sel

Win Comp B_REF_CN Win Comp 13

PDE 42

16R8R 4R2R R Gain_UP/D Gain < 4:

G_REF_CNTR

BAL < 4:0 >

Focus OK circuit Focus Ok circuit makes the timing window, which turns on the focus in the focus search state by "output" FOK as L H if the RF level is above the reference after the difference in DC between and RFO terminals extracted and compared to the reference DC value.

40K RFO 2 EQI 3 40K 40K

+

57K 90K VC + 0.625V

+

FOKB

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MIRROR CIRCUIT After amplifying the RFI signal, the mirror signal peak and bottom holds. Peak hold can follow even at defect type traverse and bottom hold counts the tracks by following RF envelop at a jump. The mirror output is "L" on the disc track and "H" between tracks. Even if above 1.4 ms is detected, it outputs "H".

1.5K

44 MCP

38K EQI 3 17K

+

80K Peak and Bottom Hold 17K

+

96K

19K

+ -

MIRROR

EFM Comparator The EFM Comparator makes the Rf signal into a secondary signal. The Asymmetry generated by a fault during Disc production cannot be eliminated by only AC coupling, so control the standard voltage of the EFM Comparator to eliminate it.

- RF Double Asymmetry Conection - EFMI Peak Prevention System - Asymmetry Hold System

x5

22 ASY

EFMI

5 40K

21 EFM

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Defect Circuit After RFO signal inversion, bottom hold is carried out using only 2. Except, the bottom hold of holds the coupling level just before the coupling. Differentiate this with the coupling, then level shift it. Compare the signals to either direction to generate the defect detect signal.

DCC0 46 75K RFO 2 37.5K

+

DCC1 45

DEFECT Bottom Envelope Bottom Envelope 43K

+

28K 75K VC+0.6254V VC

43 DCB

APC Circuit When the laser diode operates in electrostatic field, the laser output temperature highly negative so the monitor photo diode controls the laser output at a fixed level. The laser control system is installed to absorb the deviation of the disc reflection. System controls the laser power using the tracking summing signal of the side beam to a fixed laser output.

LDON PD 38
+ -

5K 5K

55K
+ -

0.25K

37 LD

55K 5K

55K Laser Control

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Center Voltage Generation Circuit The center voltage is made by using the resistance divide.

30K 30K

47 VREF

RF Equalize Circuit The AGC block, which maintains the RF peak to peak level, possess the 3T gain boost. It detects the RF envelop and compares it to the reference voltage to control the gain. Receives the RF output to stabilize the RF level to 1Vpeak-peak, which is applied to the EFM slice input.

EQC 48

EQI 3

VCA

Equalize 4 EQO

ATSC The detection circuit for shock tracking gain up is composed of the window comparator.

+ -

ATSC 36

BPF
+ -

Tracking Gain UP

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Focus Servo If the focus servo loop phase has been compensated, the focus servo loop mutts if the defect is. The focus error signal at this time is differentiated by the 0.1uF capacitor to be connected to the terminal and the 470kohms resistance and is output es through the servo loop. Therefore, the focus output is held to value before the defect error during defect. The FSET terminal changes the at which the focus loop compensation is at its maximum. If the resistance to VDDA connected to the terminal, the phase compensation frequency is changed 1.2kHz below, and GND connected to the terminal, the frequency is changed 1.2kHz above. During focus search, Fs4 turns on to cutoff the error signal and to output the focus search signal through the FEO. When the focus is on, FS2 turns on, and the focus error signal input through the FSI is output through the loop to the output pin.

FSET 18 VC 3.6K 60K FSI 11

+ +

to Digital

FZC I 20K

31 FEO

48K

Focus Phase Compensation FS2B

82K 40K
+

DFCTI FS4B FS3 FGD 10 580K 470K 40K

30 FEM PS 4 X1 X2 X3 X4 9 FLB 0 0 1 1 3 0 1 0 1 10K 50K

+ -

5K FS1

7 FRCH

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Tracking Servo The tracking servo phase compensate the tracking servo loop and differentiates the tracking error signal, after which it outputs the signal through the servo loop. TGU exchanges the tracking gain up/down time constant. As in the focus loop, the phase compensation peak frequency is varied by the Fset terminal. If the resistance connected to the FSET terminal changes, the OP Amp dynamic range offeset changes also.

TM4 TEIO 34 TM3 TLPFI DFCTI 680K TG1B 10K TM1 110K 82K 680K 28 TEM

68P F

TGU 12 TG2B

470K

Tracking Phase Compensation

10K

90K TM7
+

29 TEO

8 FSET

The TM7 switch is a brake switch which turns the tracking loop on/off when the actuator is unstable after a jump. After the servo jumps 10 tracks, the servo circuit leaves the linear range and the actuator sometimes pursues the unstable track, preventing unnecessary jumps from undesired tracking errors. As the terminal which controls the tracking servo loop's high frequency gain, the Tgu terminal controls the desired frequency range of the gain through the external cap.

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Sled Servo This servo differentiates the tracking servo and moves the pick-up. It also outputs the sled kick voltage to make a track jump in the sled axis during track movement.

TM6

26 SLO

TM7 PS 2 X1 X2 X3 X4 0 0 1 1 1 0 1 0 1
+ -

25 SLM 27 SLP

TM2

Spindle Servo & Low Pass Filter The 200Hz LPF, composed of an external 20kohms resistance and 0.33uF cap, eliminiates the high frequency carrier component.

30K 30K
+

50K 100K

+ -

24 SP0

220K 220K

FVCO Double Speed

23 SPM

18 CLVI

8 FSET

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Mirror & Cpeak Mute (use only for tracking mute ) Used against ABEX-725A, this circuit processes the tracking mutting when mirror is detected. (No recommend) the tracking mutting when EFM duty is above 22T after it is checked. Mute does not operate in the following four cases. Micom tracking gain up command transmission (TG1, TG2 = 1) Anti-shock detection (ATSC) Lock falls to L Defect detection

TRCNT Output TRCNT is output of mirror and TZC. Mirror is the track movement detection output of the main beam; TZC is the track movement detection output of the side beam. TRCNT receives these two inputs to determine whether the present pick-up is moving from the inside to the outside or from the outside to the inside. It is used at $17 tracking brake operation.

MIRROR TZC Inverter Delay TZC EDGE Detection.

Trcnt Output TZC Rising, Falling EDGE Mirror Output.

CK

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NOTES