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GREGORY P. STONE (SBN 078329) gregory.stone@mto.com KATHERINE K. HUANG (SBN 219798) katherine.huang@mto.com PETER E. GRATZINGER (SBN 228764) peter.gratzinger@mto.com KEITH R.D. HAMILTON (SBN 252115) keith.hamilton@mto.com DAVID H. PENNINGTON (SBN 272238) david.pennington@mto.com MUNGER, TOLLES & OLSON LLP 355 South Grand Avenue, 35th Floor Los Angeles, CA 90071-1560 Telephone: (213) 683-9100 Facsmile: (213) 687-3702 PETER A. DETRE (SBN 182619) peter.detre@mto.com MUNGER, TOLLES & OLSON LLP 560 Mission Street, 27th Floor San Francisco, CA 94105 Telephone: (415) 512-4000 Facsimile: (415) 512-4077 Attorneys for Plaintiff RAMBUS INC. UNITED STATES DISTRICT COURT NORTHERN DISTRICT OF CALIFORNIA SAN FRANCISCO DIVISION RAMBUS INC., Plaintiff, v. LSI CORPORATION, Defendant. RAMBUS INC., Plaintiff, v. STMICROELECTRONICS N.V.; STMICROELECTRONICS INC., Defendants. Case No. 3:10-cv-05446 RS RAMBUS INC.S REPLY TO DEFENDANTS RESPONSIVE CLAIM CONSTRUCTION BRIEF Date: Time: Judge: August 29, 2012 10:00 a.m. Hon. Richard Seeborg

Case No. 3:10-cv-05449 RS

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TABLE OF CONTENTS Page I. II. INTRODUCTION .............................................................................................................. 1 CLAIM CONSTRUCTION ................................................................................................ 1 A. controller/controller device .............................................................................. 1 B. clock signal/external clock signal .................................................................... 3 C. operation code ..................................................................................................... 4 D. precharge information.......................................................................................... 5 E. register ................................................................................................................. 6 F. representative of .................................................................................................. 7 G. sample(s)/sampled/sampling ........................................................................ 9 H. synchronous dynamic random access memory device ...................................... 11 I. synchronously with respect to ........................................................................... 14 CONCLUSION ................................................................................................................. 15

III.

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TABLE OF AUTHORITIES Page(s) FEDERAL CASES In re Rambus Inc., No. 2011-1247 (Fed. Cir. Aug. 15, 2012)............................................................................... 12 O2 Micro Intl Ltd. v. Beyond Innovation Tech. Co., 521 F.3d 1351 (Fed. Cir. 2008)................................................................................................. 7 Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005)............................................................................................. 1, 2

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I.

INTRODUCTION Defendants Responsive Brief ignores much of the key intrinsic and extrinsic evidence

cited in Rambuss Opening Brief demonstrating that Rambuss proposed constructions are correct. Defendants also repeatedly misrepresent Rambuss prior claim construction positions, conjuring up purported inconsistencies where there are none. For the reasons set forth below and in Rambuss Opening Brief, the Court should construe the claim terms in dispute according to the constructions proposed by Rambus. II. CLAIM CONSTRUCTION A. controller/controller device

The parties dispute regarding the terms controller and controller device center on two issues: (1) whether the construction should specify that the controller includes circuitry to direct the actions of one or more memory devices and (2) whether the construction should specify that the controller is an integrated circuited device. With respect to the first issue, Defendants argue that Rambus incorrectly asserts that the claimed controller only controls one or more memory devices. Defs. Br. at 6 (emphasis in original). The word only, however, appears nowhere in Rambuss proposed construction. Contrary to the straw man that Defendants erect in order to make their argument, Rambuss proposed construction requires simply that the controller include circuitry to direct the actions of one or more memory devices, and does not preclude the controller from including circuitry to control other types of devices as well. Defendants cannot dispute that every asserted claim in which the term controller or controller device appears includes limitations that involve the controller directing the actions of one or more memory devices.1 As the Federal Circuit has emphasized, the claims themselves provide substantial guidance as to the meaning of particular claim terms. Phillips v. AWH Corp., 415 F.3d 1303, 1314 (Fed. Cir. 2005). Moreover, the
1

The asserted claims in which the terms at issue appear are set forth in Appendix A to the Joint Claim Construction and Prehearing Statement, LSI Dkt. #95-1. A document containing the text of all of the asserted claims is attached as Exhibit A to the Declaration of Peter A. Detre in Support of Rambuss Reply to Defendants Responsive Brief on Claim Construction (Detre Reply Decl.).
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specification makes clear that the controllers at issue must be able to control memory devices. See, e.g., 916 patent, col. 1:22-26 (stating that system described allows high speed transfer of blocks of data, particularly to and from memory devices); col. 3:52-54 (stating that invention includes a memory subsystem . . . including at least one memory device). With respect to the second issue, the Defendants argue that a controller should not be construed as a single-chip integrated circuit device for two reasons. First, Defendants point to a dependent patent claim in a patent from the Farmwald/Horowitz family in which a memory device was specified as being formed on a single semiconductor substrate. (Defendants misleadingly excise the word memory when they quote from the claim). Defs. Br. at 8. Defendants argue that had Rambus intended that a controller be limited to a single-chip device, it knew how to draft such claims. Id. But where, as here, the specification makes clear that the controllers at issue are single-chip devices, a claim limitation to that effect would be superfluous. Significantly, Defendants simply ignore the evidence from the specification cited by Rambus in its Opening Brief showing that the claimed controllers are integrated circuit devices. See Opening Br. at 12. Second, Defendants make much of a prior art patent in which an embodiment of a CPU was described as consisting of two chips. 2 Defs. Br. at 8. It is immaterial, however, whether CPUs or controllers in general may consist of multiple chips. The question here is whether the novel controllers described in the patents-in-suit may consist of multiple chips. As the specification makes clear, they cannot because those controllers are semiconductor devices with built-in integrated circuit bus interface[s]. See Opening Br. at 12 (quoting patent specification).

The application for the Jackson patent cited by Defendants was filed in 1978, a dozen years before the application for the Farmwald/Horowitz patents. See Declaration of John D. Cadkin in Support of Defendants Responsive Brief on Claim Construction (Cadkin Decl.), Ex. K. A claim term is to be construed according to the meaning that the term would have to a person of ordinary skill in the art in question at the time of the invention, i.e., as of the effective filing date of the patent application. Phillips, 415 F.3d at 1313. Evidence of the meaning of a claim term twelve years prior to the relevant time period in a rapidly changing technological area should be afforded little if any weight.
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Rambuss proposed construction properly situates the controller in the context of the claims and specification of the patents-in-suit. Defendants circular and generic proposed construction provides no guidance as to the meaning of the terms controller and controller device in the context of the patents-in-suit and should be rejected. B. clock signal/external clock signal

In its Opening Brief, Rambus pointed out that Defendants proposed construction of clock signal incorrectly suggests that being continuously present and repeat[ing] at regular intervals are just properties of the clock signals at issue here, rather than being necessary features of periodic signals. Opening Br. at 13. As an initial matter, Defendants do not dispute that a periodic signal necessarily repeats at regular intervals. Defs. Br. at 9 (stating that parties dispute only whether a periodic signal must be continuously present). Thus, Defendants effectively concede that their proposed construction, which suggests that such regular repetition is simply a property of the particular periodic signals at issue here, cannot be correct. Defendants do insist that a periodic signal need not be continuously present, but do not respond to Rambuss point that a signal that repeats at regular intervals must be continuously present because, otherwise, the repeating pattern would be interrupted at times when the signal was not present. See Defs. Br. at 9-10. Moreover, while complaining that Rambus fails to cite intrinsic evidence in support of its positions, Defendants concede that the specification describes the periodic signals at issuenamely the clock signals described in the specificationas continuously present. Id. at 10 (citing 916 patent, cols. 8:35-36, 19:4-5, 21:53-57). Defendants cite to a declaration of Rambuss technical expert, Robert Murphy, in a reexamination proceeding which states that a clock signal is a continuously present periodic signal, Defs. Br. at 10, to suggest that Mr. Murphy agrees that a periodic signal is not necessarily continuously present. Defendants misread the declaration. In the passage cited, Mr. Murphy is distinguishing a clock signal from the strobe signal in the patent under reexamination by emphasizing the continuously present nature of the periodic clock signal. Cadkin Decl., Ex. D (9/4/09 Murphy Decl.), at 24, 99 (arguing that clock signal in alleged prior art cannot be the claimed strobe signal, because, unlike strobe signal that is issued only at certain times, such a
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clock is a continuously present periodic signal). The passage cannot plausibly be read as implying that periodic signals are not necessarily continuously present. In fact, Rambus and Mr. Murphy have been entirely consistent that a periodic signal must be continuously present. For example, in a 2005 deposition taken in Hynix I, Mr. Murphy testified as follows: Q. Okay. So a periodic signal is a signal that has to repeat as long as the electronic device is turned on? [Objection omitted.] THE WITNESS: . . .So the device turned on, a signal was switching, switching, switching periodic all the way to this point, and then all of a sudden the signal disappeared. So if I had a picture of that point in time, no one of ordinary skill in the art would call that signal periodic. Detre Reply Decl., Ex. B (Deposition of Robert Murphy, Apr. 25, 2005), at 127:9-24. A periodic signal is a signal that repeats at regular intervals over the entirety of the

11 signal. It follows that the signal must be continuously present, rather than stopping and starting. 12 The Courts construction should reflect that being continuously present is a property of periodic 13 signals. 14 C. 15 Defendants argue that operation code should be construed as including control bits, 16 rather than just bits, to make clear that an operation code does not include address information 17 or data. Far from clarifying the construction of the term, Defendants proposal would serve only 18 to muddy the waters. Both Rambuss and Defendants proposed constructions state that the bits 19 in the operation code specify a type of action. Address information does not specify a type of 20 action; rather, it identifies a location in the memory array. Data does not specify a type of action; 21 rather it constitutes the information stored in the memory array. It is control information that may 22 specify a type of action. See, e.g., 916 patent, col. 9:46-48, 54-57 (control information in 23 AccessType field specifies whether the requested operation is a read or write and the type of 24 access). By inserting the redundant word control into an otherwise straightforward definition, 25 Defendants add uncertainty and confusion for the reasons stated in Rambuss Opening Brief. 26 Opening Br. at 14. 27 28
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D.

precharge information

The parties dispute regarding the appropriate construction of precharge information is limited to whether the information at issue should be specified to consist of one or more bits.3 In support of their assertion that precharge information need not consist of one or more bits, Defendants point to the specifications description of the access mode that, inter alia, determines whether the DRAM should precharge the sense amplifiers or save the contents of the sense amps for a subsequent page mode access. Defs. Br. at 13. But the portion of the specification quoted by the Defendants does not speak one way or another as to whether this precharge information is conveyed in the form of bits. In its Opening Brief, Rambus cited to the clear description in the specification that the referenced access mode, including precharge information, is specified by an AccessType field consisting of bits. Opening Br. at 15. Having no response, Defendants simply ignore the portions of the specification cited by Rambus. Defendants claim differentiation argument also fails because, even if the term precharge information were construed as consisting of one or more bits, both of the dependent claims cited by the Defendants, see Defs. Br. at 13, would further narrow the term: claim 6 of the 281 patent requires the precharge information to consist of a single bit, and claim 20 of the 696 patent provides details of the precharge information conveyed by one of the bits that constitute the information. Cadkin Decl., Exs. N & O. Moreover, every asserted patent claim in this case that includes the term precharge information specifies that the precharge information is included in an operation code.4 Both sides agree that an operation code consists of one or more bits; the claim construction dispute turns only on whether those bits should be specified to be control bits. See Section II.C, supra. Thus, Defendants cannot dispute that, for purposes of this case, precharge information is properly construed as consisting of one or more bits.

Defendants also assert that precharge information requires no construction. For the reasons set forth in Rambuss Opening Brief, the Court should construe the term. Opening Br. at 15. The asserted claims that include precharge information are claim 27 of the 037 patent and claims 1 and 19 of the 997 patent. LSI Dkt. #95-1 (Appendix A to Joint Claim Construction and Prehearing Statement). The text of these claims can be found in Ex. A to the Detre Reply Decl.
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Defendants point out that Rambus has previously agreed to a construction of precharge information that did not specify that the information consisted of one or more bits. Indeed, as Rambus pointed out in its Opening Brief, Judge Whytes construction of the term in Hynix I did not so specify and that construction is not incorrect. Opening Br. at 16. However, in the Coordinated Actions, Judge Whyte revised his construction to indicate that the information at issue consists of one or more bits, see id., and it makes sense to likewise provide that additional guidance regarding the meaning of the term in the context of the patents-in-suit here. E. register

Defendants argue that the construction of register should be broad enough to encompass memory cells in the memory array because the specification is silent as to whether a register may be included in the memory array. Defs. Br. at 14. The specification is, however quite clear that the memory array in a DRAM consists of memory cells for the storage of the data. See 916 patent, Fig. 1 & col. 1:61-65 (RAM array consists of memory cells with one bit of data stored at the intersection of each word and bit line); id., col. 23:52-55 (The DRAM memory array is divided into a number of subarrays 150-157, for example, 8. Each subarray is divided into arrays 148, 149 of memory cells.); col. 24:13-15 (internal I/O lines supply data to memory cells). As Defendants acknowledge, the registers at issue are described in the specification as storing other kinds of information such as device IDs or delay times. Defs. Br. at 15. Consequently, registers are not memory cells and are not part of the memory array. Defendants also oppose specifying that the information stored in a register consists of one or more bits, but fail to cite to any disclosure in the specification to suggest that a register could store information in any other form.5 Defendants simply ignore the intrinsic evidence cited by Rambus establishing that information is stored in registers in the form of bits. Opening Br. at 17. Defendants misconstrue Rambuss argument when they say that Rambus argues that the use of the term information [in Defendants proposed construction], implies that Defendants register can only store one bit. Defs. Br. at 15. It is not Defendants use of the term information that may imply the storage of only one bit; rather it is the fact that Defendants proposed construction includes a single storage element. Defendants do not address Rambuss argument that a register could consist of a storage element or a group of storage elements to accommodate multiple bits. Opening Br. at 17-18. -6RAMBUSS REPLY TO DEFENDANTS RESPONSIVE CLAIM CONSTRUCTION BRIEF CASE NOS. 3:10-CV-05446, 3:10-CV-05449

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Defendants do cite to a Rambus patent claim that provides for storage of information indicative of a range of addresses in address registers to argue that it would be inappropriate to construe register as storing bits when certain claims require that it store information. Defs. Br. at 15. But information and bits are not mutually exclusive; rather, bits are a form of information and the specification is clear that address information, like other information stored in registers, consists of bits. See, e.g., 916 patent, col. 4:5-6 (memory addresses [may be] up to 40 bits wide); col. 7:61 - 8:1 (A master can . . . write address values (up to 40 bits in the preferred embodiment, 1012 bytes), preferably contiguous, into device address-space registers.). The intrinsic evidence establishes that a register is distinct from the memory cells in the memory array, stores information in the form of bits, and can consist of multiple storage elements; the Courts construction of the term should reflect these important features. F. representative of

Defendants argue that the term representative of should not be construed and, instead, should just be assigned its ordinary meaning because it is a non-technical term used in a nontechnical sense. Defs. Br. at 16. The Federal Circuit has made clear, however, that whether a term should be construed does not turn on whether it is technical. For example, in O2 Micro Intl Ltd. v. Beyond Innovation Tech. Co., 521 F.3d 1351, 1361 (Fed. Cir. 2008) the district court had declined to construe the non-technical term only if and had assigned the term its ordinary meaning. The Federal Circuit held that this was error, stating [a] determination that a claim term needs no construction or has the plain and ordinary meaning may be inadequate when a term has more than one ordinary meaning or when reliance on a term's ordinary meaning does not resolve the parties dispute. Id. Here, while Defendants have failed to offer their own construction for representative of, they will undoubtedly seek to read the term very broadly in order to argue that Rambuss claims are anticipated by prior art. Significantly, Defendants do not disclaim such a broad reading, and, contrary to Defendants argument, Rambuss concern is far from hypothetical. Defs. Br. at 16. In the Coordinated Cases, in the context of arguments regarding the prior art Bennett patent, Judge Whyte rejected a broad reading of the term, finding that one value being representative
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of another requires more than a functional relationship between the two and that [t]he word representative implies some level of recognition by another that the first value indicates or represents the second. Opening Br. at 18-19 (quoting Order Denying Motion for Summary Judgment No. 1 of Invalidity, 05-cv-00334-RMW, Dkt. #2873). Defendants have raised the very same Bennett patent as prior art here and, presumably, will be making similar arguments. See Detre Reply Decl., Exs. C & D (Exhibit B to LSI and STMicro Invalidity Contentions, respectively, listing Bennett patent as primary reference for all asserted claims). Defendants complain that Rambus has not cited any intrinsic evidence in support of its proposed construction of is representative of as indicates. A consideration of the specification, however, establishes that there can be no legitimate dispute regarding the meaning of is representative of in the context of the Farmwald/Horowitz patents. The term is representative of appears in claim limitations related to variable block size and programmable latency, such as the block size information is representative of an amount of data to be output by the memory device and the value is representative of a number of cycles of an external clock signal to transpire after which the memory device outputs the amount of data. 916 patent, claim 15. With respect to the block size information limitation, the specification discloses a BlockSize field and an example of an encoding to translate the value of BlockSize to an amount of data. 916 patent, col. 11:44-67. Thus, the specification discloses a correspondence between the BlockSize value and an amount of data that is more than a mere functional relationship between the twothe BlockSize value is intended to, and does, indicate an amount of data. Similarly, with respect to the claim limitation involving a value representative of a number of cycles of an external clock signal to transpire, the specification discloses that, in a preferred embodiment, an access-time register stores a value equal to the number of cycles of the external clock signal to transpire. 916 patent, col. 16:7-13.6 Again, the specification discloses that the

The specification states that the value stored in the access-time register is preferably one-half the number of bus cycles for which the slave device should wait. 916 patent, col. 16:8-9. However, in a preferred embodiment, there are two bus cycles per clock cycle, id., col. 19:39-50, so this value actually corresponds to the number of clock cycles that the slave device should wait. -8RAMBUSS REPLY TO DEFENDANTS RESPONSIVE CLAIM CONSTRUCTION BRIEF CASE NOS. 3:10-CV-05446, 3:10-CV-05449

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relationship between the value stored in the access-time register and the number of cycles of the external clock signal to transpire is not merely a functional relationshipthe access time value is intended to, and does, indicate the number of clock cycles. Because the scope of the term is representative of is likely to be disputed in this litigation, the Court should construe the term, consistently with the intrinsic and extrinsic evidence cited by Rambus, as indicates. G. sample(s)/sampled/sampling

Defendants proposed construction elides the critical distinction between sampling and the more general capturing. As the intrinsic and extrinsic evidence cited by Rambus in its Opening Brief establish, sampling involves capturing the values of a signal at one or more discrete points in time. Defendants refer to some of the same intrinsic evidence cited by Rambus and assert, without discussion, that this evidence does not, however, mandate that sampling must occur at one or more discrete points in time. Defs. Br. at 17. The opposite is true. For example, Defendants note that the specification states that [v]ariable delay lines 103 and 105 are adjusted via feedback lines 116, 115 so that input receivers 101 and 111 sample the bus clocks just as they transition. Id. (quoting 916 patent, col. 23:11-14). The bus clocks, like all clock signals, transition between high and low voltages at certain discrete points in time. See 916 patent, Fig. 13 (illustrating bus clocks, BUS CLOCK1 and BUS CLOCK2, including transitions between high and low voltages). It is at those discrete points in time that the specification indicates that the input receivers sample the bus clocks. Defendants also note that the specification states that each device pin . . . is connected to two clocked receivers, one to sample the even cycle inputs, the other to sample the odd cycle inputs. Defs. Br. at 17 (quoting 916 patent, col. 21:58-62). The reference to clocked receivers indicates that the receivers sample the inputs at the discrete points in time identified by the transitions of a clock signal. Rambus also pointed out that the specification refers to a sample period, namely the time period between successive samples, and that this reference would make no sense unless sampling were done at discrete points in time separated by time periods. Opening Br. at 20. Defendants simply ignore this evidence.
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Rambus also cited extrinsic evidence for how one of ordinary skill in the art would understand the term sampling. See Opening Br. at 19 (quoting 1988 IEEE Dictionary definition of sampled data as [d]ata in which the information content can be, or is, ascertained only at discrete intervals of time). Defendants, by contrast, are unable to cite any dictionary definition that supports their proposed construction. Instead, through creative use of ellipses and other techniques, Defendants falsely claim that Rambus and its experts admitted during the course of the ITC proceedings that sampling refers simply to capturing. Thus, Defendants cite deposition testimony of one of Rambuss experts, Steven Przybylksi, as follows: Q: [W]hen it says, capturing data . . . does that constitute sampling data as you understand the term? A: Itscapturing data . . . Defs. Br. at 18 (ellipses in Defs. Br.). Defendants strategic placement of ellipses obscures the fact that the question actually asked was whether capturing data on the rising edge of DSTB

13 constituted sampling. Cadkin Decl., Ex. W (Przybylski Depo, 8/18/2011) at 89:23-25 (emphasis 14 added). During this portion of the deposition, Dr. Przybylski was being questioned about the 15 DSTB* signal in the NextBus Specification, certain alleged prior art. Detre Reply Decl., Ex. E 16 (Przybylski Depo., 8/18/2011), at 87:11-12. The relevant timing diagram, Figure 4-11 of the 17 NextBus specification, shows DSTB* transitioning from low to high voltages at discrete points in 18 time. Detre Reply Decl., Ex. F (NextBus Specification) at 4-15. The discussion in the deposition 19 refers to capturing the data on those rising edges of DSTB*i.e. at discrete points in time. 20 Because the data was being captured at discrete points in time, it constituted sampling. Rambus 21 and Dr. Przybylski have been entirely consistent on this point. See, e.g., Detre Reply Decl., Ex. E 22 (Przybylski Depo., 8/18/2011) at 208:5-7 ([A]s I define it there, sampling means capturing the 23 data at a discrete point in time.). 24 Similarly, Defendants assert that, in its tutorial in the ITC proceedings Rambus stated 25 that sampling refers to captu[ring] data on the bus. Defs. Br. at 17. Again, the Defendants 26 omit the key portion of the slide that they purport to be quoting. The full sentence states: The 27 Barth I patents introduced another signal known as a data strobe that identifies when to capture 28
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data on the data bus (called sampling). Cadkin Decl., Ex. U (emphasis added). The data strobe in the Barth I patents identifies the discrete points in time when the data is to be captured; it is this process that Rambus referred to as sampling in its tutorial. Defendants also assert that Rambuss proposed construction is ambiguous, citing to Figure 13 of the patent specification. Defs. Br. at 18-19. While Defendants argument on this point is somewhat murky, Figure 13 and the related text in the specification are perfectly clear. Figure 13 shows the input signal being sampled at times 125 and 127i.e. bits of data are received at these discrete points time by two input receivers, designated as an even input receiver that samples at time 127 and an odd receiver that samples at time 125. 916 patent, col. 23:39-42. The falling edges of the clock signal Internal Clock Complement 74 is used as a timing reference for the even input receiver while Internal Clock 73 is used as a timing reference for the odd input receiver. The input sampling actually occurs a short period of time after the falling edges of these clock signals due to sampler delay, namely the time required after the clock edge for the input receiver circuitry to actually sample the data. 916 patent, col. 23:26-28. The intrinsic evidence and extrinsic evidence establish that sampling refers to obtaining values at discrete points in time, and Rambus has always been consistent on this point. Defendants arguments to the contrary should be rejected. H. synchronous dynamic random access memory device

Defendants do not seriously dispute that a synchronous dynamic random access memory device, or synchronous DRAM device, is an integrated circuit device, i.e. a single chip per the Federal Circuits and the parties agreed construction. All that Defendants have to say on this score is that the term synchronous dynamic random access memory device is absent from the specification. Defs. Br. at 21. But, as pointed out Rambuss Opening Brief, the specification does include the term DRAM device, and Defendants do not address the intrinsic evidence establishing that a DRAM device is an integrated circuit device. See Opening Br. at 21. It therefore follows that a synchronous DRAM device, which is a particular sort of DRAM device, must also be an integrated circuit device. Furthermore, Defendants state that they do not dispute

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that a synchronous DRAM device includes one or more arrays of DRAM cells. Defs. Br. at 21. Consequently, it makes sense to provide that additional clarity in the terms construction. Defendants argue, contrary to Rambuss proposed construction, that a synchronous DRAM device can include a memory controller. This morning, the Federal Circuit issued its opinion in In re Rambus Inc., No. 2011-1247 (Fed. Cir. Aug. 15, 2012). Detre Reply Decl., Ex. I. Although the Court held that a memory device could include certain control functionality, such as the logic necessary to receive and output specific data, it made clear that a memory device cannot include a controller that perform[s] the control function of a CPU or bus controller. Id., at 15. Thus, the construction here should reflect that a synchronous DRAM device does not include a controller that performs the control function of a CPU or bus controller.7 Finally, Defendants address what it means for a DRAM device to be synchronous. Although Defendants assert that Rambus spills much ink insisting that a synchronous memory device must receive a clock signal, Defs. Br. at 21 (emphasis in original), in fact Rambus conserved its ink on this point. That is because at the time that it filed its Opening Brief, Rambus was unaware that Defendants were challenging the hitherto non-controversial point that a synchronous memory device receives a clock signal. Indeed, all of Rambuss prior litigation opponents have agreed on this point. For example, in the Coordinated Actions, Hynix, Micron, Samsung and Nanya all proposed construing synchronous memory device as a memory device that receives an external clock signal. Detre Reply Decl., Ex. G. As set forth in Rambuss Opening Brief, Judge Whytes construction of synchronous memory device also included, inter alia, the requirement that the device receive an external clock signal. Opening Br. at 23. Rambus assumed that it was implicit in Defendants proposed construction that the synchronous DRAM device receive the external clock signal because that construction provides

The Federal Circuit also held that a memory device need not consist of a single chip. As discussed above and in Rambuss Opening Brief, however, the evidence establishes that a synchronous dynamic random access memory device, the term to be construed here, is limited to a single chip. Opening Br. at 21-22.
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that the clock signal regulate the timing of device operations.8 Defendants fail to explain how the external clock signal is supposed to regulate the timing of the operations of the synchronous DRAM device if that device does not receive the clock signal and, therefore, cannot use it to time its operations. Persons of ordinary skill in the art understand that one of the key differences between asynchronous and synchronous memory devices is that the latter receives a clock signal that is used as a timing reference. A leading text on memory devices puts it this way: Historically DRAMs have been controlled asynchronously by the processor. This means that the processor puts addresses on the DRAM inputs and strobes them in using the RAS\ and CAS\ pins. . . . Synchronous control means that the DRAM latches information from the processor in and out under the control of the system clock. . . . An advantage of synchronous DRAMs is that the system clock is the only timing edge that must be provided to the memory. Detre Reply Decl., Ex. H (Betty Prince, High Performance Memories (1996)), at 137 (emphasis added). The intrinsic evidence is of accord. In particular, the memory devices described in the specification receive one or more clock signals. See, e.g., 916 patent, Fig. 2 (showing CLOCK1 and CLOCK2 going to, inter alia, DRAM devices). Moreover, these memory devices must receive a clock signal in order to carry out the operations described in the specification. For example, as discussed above, the specification discloses that memory devices may contain an access-time register that stores a value equal to the number of cycles of a clock signal to transpire before the memory device outputs data. See pp. 8-9, supra. Of course, unless the memory device actually receives the clock signal, it would be unable to ascertain when the necessary number of clock cycles had transpired. Defendants point to claim 26 of U.S. Patent No. 6,324,120, a patent in the Farmwald/Horowitz family, which claims a synchronous dynamic random access memory device The parties seem to agree that an external clock signal is used to time operations in synchronous memory devices. In its Opening Brief, Rambus explained why its formulation (that the clock signal governs the timing of the response to a read request, write request, or operation code) is superior to Defendants vague formulation (that the clock signal be used to regulate the timing of device operations). Opening Br. at 22-23. Defendants do not address this issue in their brief.
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and includes a limitation that the device contain clock receiver circuitry to receive an external clock signal. Defs. Br. at 22. Defendants argue that the limitation would be superfluous if a synchronous DRAM device necessarily received a clock signal. Defendants reasoning is faulty, however, because the limitation that they cite introduces the external clock signal that figures in other limitations and, therefore, serves as the requisite antecedent basis for the external clock signal in those limitationsfor example, a subsequent limitation provides that block size information is sampled synchronously with respect to the external clock signal. Cadkin Decl., Ex. Y. The intrinsic and extrinsic evidence is of accord: a synchronous DRAM device receives an external clock signal which governs the timing of the response to a read request, write request, or operation code, as Rambuss proposed construction provides. I. synchronously with respect to

Defendants proposed construction of synchronously with respect to is operating in step (or in phase) with respect to. Although Defendants now assert that in step does not mean in phase in their proposed construction, Defs. Br. at 23, the most natural reading of the parenthetical or in phase is that is intended to provide a synonymous phrase to in step. Additionally, while disclaiming that in step means in phase, Defendants provide no guidance as to what in step is intended to mean. To the extent that Defendants intend in step with to mean occurring or transitioning at the same time, their proposed construction is flatly contradicted by the intrinsic evidence. As Rambus pointed out in its Opening Brief, the specification refers to signals as synchronized even when they do not transition at the same time so long as they have a known timing relationship. Opening Br. at 24. Defendants complain that Rambus is misrepresent[ing] the intrinsic record. Defs. Br. at 23. To the contrary, the specification plainly states that outputs 107 and 108 are synchronized with the two bus clocks, 916 patent, col. 23:21-22 (emphasis added), while the dotted lines on Figure 13 plainly shows that the transition of these two delay line outputs do not line up with the transitions of the bus clocks but are shifted from them by a

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known amount. (The specification explains that this known amount of time is equal to the delay in the input sampler. 916 patent, col. 23:14-20.) Defendants assert that it is not the delay line outputs but rather the internal device clock which must be synchronized with the bus clocks. Defs. Br. at 23 (emphasis in original). As an initial matter, that the internal device clock may be synchronized with the bus clocks does not preclude the delay line outputs from also being synchronized with the bus clocks. As discussed above, the disclosure in the specification is unambiguous that the delay line outputs are in fact synchronized with the bus clocks. Moreover, while describing the internal device clock as synchronized with the bus clocks, Defendants concede that the transitions of this internal clock do not line up with the bus clock transitions but, rather, occur midway between transitions of the two bus clocks. Defs. Br. at 24. Thus, the internal clock signal is another example of a signal disclosed in the specification that is considered to be synchronized with the bus clocks because there is a known timing relationship between it and the bus clocks even though their transitions do not occur simultaneously. The specification is clear that two signals will be considered synchronous with respect to one another, even if their transitions do not line up, so long as they have a known timing relationship. Lastly, Defendants cite to certain Rambus patent claims and certain statements in the prosecution history of Rambus patents that refer to data being output synchronously with respect to edge transitions of a clock signal. Defs. Br. at 24-25. Defendants assert without further discussion that these claims and statements somehow support their proposed construction rather than Rambuss. In fact, the claims and statements cited by Defendants are entirely consistent with Rambuss proposed construction and simply provide that there is a known timing relationship between the output data and the edge transitions of a clock signal. III. CONCLUSION For the reasons stated herein and in Rambuss Opening Claim Construction Brief, Rambus respectfully submits that the Court should adopt its proposed claim constructions of the claim terms in dispute.

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DATED: August 15, 2012

MUNGER, TOLLES & OLSON LLP By: /s/ Peter A. Detre Peter A. Detre Attorneys for Plaintiff RAMBUS INC.

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