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A 10-mW Two-Channel Fully Integrated System-on-Chip for Eddy-Current Position Sensing

Michael Oberle, Student Member, IEEE, Robert Reutemann, Student Member, IEEE, Jrgen Hertle, Student Member, IEEE, and Qiuting Huang, Fellow, IEEE

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AbstractThe use of magnetic bearings in small biomedical devices poses new challenges for the integration of complex embedded electronic systems. This paper describes a low-power fully integrated two-channel system-on-a-chip (SOC) for twodimensional (2-D) differential position sensing in magnetic bearings through two pairs of eddy current sensors. It consists of a 312.5 kHz switched-capacitor (SC) sine-wave generator, a two-channel data acquisition unit including a 19-dB quadruple difference instrumentation amplifier, and a demodulating 12-bit analog-to-digital (A/D) converter with DSP-compatible serial interface. A signal-to-noise-plus-distortion ratio (SNDR) of more than 60 dB has been achieved, which corresponds to a resolution of better than 3 m at a maximum displacement range of 3 mm. The entire system has been integrated in a standard 0.6- m CMOS technology and consumes 10 mW at a 2.7-V supply. Index TermsDecimation filter, differential difference amplifier, eddy-current sensors, magnetic bearing, modulator, sine-wave generator, systems-on-chip.

displacement information with high resolution for smooth bearing operation. The power budget is tight and the system design is a challenging task. The organization of this paper is as follows. Section II provides an insight into eddy-current-based position control of magnetic bearings. Section III describes the architecture of the novel eddy-current sensing IC, and the implementation of the building blocks will be discussed in Section IV. Finally, experimental results of the system are presented in Section V. II. POSITION MEASUREMENT BY EDDY-CURRENT SENSORS Reliable long-term operation needs a precise control algorithm to achieve a wear-free and nearly frictionless rotation. This requires a position measurement that is proportional to standoff and independent of temperature drift. Eddy current sensors are widely used for noncontact position, displacement, and proximity measurements [1]. When the sensor coil is driven by an ac current, it generates an oscillating magnetic field which induces eddy currents in any nearby metallic object. This current generates a magnetic field opposing that of the sensor coil. This effect diminishes total magnetic flux in the sensor coil and can finally be sensed as a change of the coils resistance and inductance. Coil and target constitute the primary and (shorted) secondary of a weakly coupled air-core transformer. Movement of the target changes the coupling. This results in an impedance change at the terminals of the coil. Eddy-current sensors are usually complemented by an additional capacitor to create a resonant network that improves the sensitivity to target displacement. Fig. 1 illustrates the principle of operation. The sensor is excitated by a square-wave carrier. The output of the sensor is a complex voltage vector. If two sensors are applied to measure the displacement, the movement of the target results in a change of the differential output vector in amplitude and phase (see Fig. 2). Linearity and gain of the demodulator can be improved by an additional phase shifter . Parameter deviations of external L and C in the range of 5% will influence the transfer function for maximum target displacements. Reliable operation for all possible parameter deviations requires an excitation below the lowest possible resonant frequency. However, the choice of the excitation frequency is a tradeoff between linearity and sufficient sensor output swing, because low signal levels require a better noise performance of the readout circuitry. The process of demodulation also influences the choice of the excitation frequency. The sensor is usually excited by a square-wave carrier. High-order harmonics will be attenuated

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I. INTRODUCTION AGNETIC bearings are designed to support rotating machinery elements without coming into contact with the rotor. The rotor is suspended in a magnetic field which is generated by the bearing. This principle of operation incorporates several advantages for applications in medicine. The ability to apply forces through walls of a pump casing makes it ideal for hermetically sealed and sterile systems. But applications in biomedicine, especially fully implanted devices, limit the available power for the device. This power is needed almost completely for the bearing and the motor itself. The space limitations require major parts of the electronic units to be integrated onto a single chip, especially sense and control circuits. Position control is not trivial for such a highly nonlinear system. The sensing of the rotor position is therefore critical for the operation. If such a bearing is used in a blood pump, position control becomes even more important, since a high percentage of fragile blood cells must survive the pumping process for reduced haemolysis. Furthermore, blood cells must not stick together, in order to prevent malfunction or, worse, the development of a thrombosis later on. This means that the levels and duration of shear stress on the blood must be minimized, which requires the adjustment to be smooth and precise. Position control requires two-dimensional (2-D) rotor
Manuscript received November 1, 2001; revised February 4, 2002. The authors are with the Integrated Systems Laboratory, Swiss Federal Institute of Technology (ETH), CH-8092 Zrich, Switzerland (e-mail: oberle@iis.ee.ethz.ch). Publisher Item Identifier S 0018-9200(02)05865-1.

0018-9200/02$17.00 2002 IEEE

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Fig. 1. Conventional system architecture for an eddy-current position sensing device; discrete solution for one channel.

Fig. 2. Measured differential complex output voltage vector for source resistance of R k (x in millimeters). indicates rotation of coordinate systems due to additional phase shift of the demodulating carrier.

= 4

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by the bandpass characteristic of the eddy-current sensor. To achieve a resolution of 10 bit or more, one will need to integrate additional filtering before and after the demodulation. However, every additional filter means additional power consumption. Thus, a different concept is needed to fulfill the requirements. III. THE NOVEL SYSTEM CONCEPT The application of eddy current sensors to extract position information in magnetic bearings has been discussed in the previous section. Applications of these devices in biomedicine, especially for implantation, limit the available power for the magnetic bearings as well as the space for the sensors and the electronic control units. This power is almost totally needed for the motor itself. The miniaturization of the entire device reduces size and mass of the rotor/impeller assembly, as well. To achieve the same flow performance, it is necessary to increase the angular speed. On the other hand, as the distance between rotor and shaft decreases, a faster response of the control loop as well as an improved resolution for stable and smooth operation is required. Two-dimensional rotor displacement information therefore needs up to 10-bit resolution for smooth bearing operation. Fig. 3 shows a simplified view of a magnetic bearing with 2-D position sensing. Limitations in space require small sensor coils with diameters of less than 6 mm and sensor-to-rotor distances of up to 3 mm, which means a loss of sensitivity over the full displacement range. The measured displacement-to-frequency ratio of the full range is below 10%, which is too low

Fig. 3. Use of two pairs of eddy-current sensors for 2-D position sensing in a magnetic bearing. (a) General assembly. (b) Single sensor response to target displacement. (c) resonant sensor network.

for frequency measurements. The rotor displacement is therefore converted into a differential voltage by driving the resonant circuitry at a fixed frequency of 312.5 kHz, which is below the worst-case minimum resonant frequency of 318 kHz. The displacement is measured differentially by pairs of eddy-current sensors [Fig. 3(a) and (c)], since bearing stability does not require exact measurements of the absolute rotor position. This eliminates temperature dependency almost completely, assuming similar temperature coefficients for all sensors in the assembly, and improves the linearity of the displacement feedback around the operating point of the rotor. Power consumption is the most important driving factor in the design of the sensing system. The analysis of a state-of-the-art two-channel eddy-current sensing device reveals that most of the power can be saved by an improved excitation concept, including the eddy-current sensor. In general, a lower supply voltage is a very common but effective way to cut down the power consumption. However, this approach reduces the dynamic range of the sensor signals, making high-resolution signal processing more difficult. Increasing the source resistance of the low-ohmic eddy-current sensors also improves the power characteristics. Again, the dynamic input signal range will decrease, which makes additional circuitry a necessity to read out and amplify the sensor signals prior to their demodulation. Fig. 4 shows a block diagram of the novel system. All sensors are excited by an approximated sine wave. This makes

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Fig. 4. Simplified block diagram of the eddy-current excitation and sensing system. Fig. 5. Simplified schematic of the SC sine-wave generator. Clock phases are indicated with AAZ and 14. TABLE I CAPACITOR VALUES FOR THE SC SINE-WAVE GENERATOR (IN PICOFARADS)

additional filtering to prevent intermodulation unnecessary, since the already low harmonics will be sufficiently attenuated by the sensor. Each of the channels represents one dimension of the position detector. The target standoff is measured by the difference signal of a pair of sensors. A novel fully balanced quadruple difference instrumentation amplifier has been developed to read out each pair of sensors and to amplify the equivalent differential displacement voltage with a single building block. The signals are demodulated and digitized by modulator before being decimated a 12-bit third-order and read out via the DSP interface. All clocks and phases are derived from a 5-MHz system master clock, except for the serial interface which is driven by an independent clock. The sampling frequency excitation frequency is 1/16 and the is 1/4 of the master frequency. The fully differential system architecture and the excitation by an approximated sine wave reduce distortion and keep the dynamic range sufficiently high. The combination with the modulator avoids the implementation of additional chosen power-consuming filters and mixers and reduces the number of building blocks by a factor of two. IV. CIRCUIT IMPLEMENTATION OF THE EDDY-CURRENT SENSING DEVICE A. Sine-Wave Excitation Circuitry The overall system performance requires a signal generator with reduced total harmonic distortion to prevent the need for additional filtering, and low complexity to minimize power consumption. This can be accomplished by a combination of low excitation voltage, an increased output resistance , and by the filter characteristic of the sensor. , as discussed The choice of a larger source resistance in the previous section, reduces the driving requirements of the excitation circuitry. The implementation of a low-noise instrumentation amplifier close to the sensors is another step. Lower excitation amplitudes are possible since low-level sensor signals can be read out due to the improved noise rejection and the increased sensitivity of the front end. The degradation of the dynamic range is compensated by the fully differential signal processing which increases the dynamic range by 6 dB. Altogether, the power consumption of this building block

alone can be improved by more than a factor of 20 through excitation voltage and a source resistor of a 350-mV 2 2k . The bandpass filter characteristic of the resonant sensor circuitry, as shown in Fig. 3(b), enables the approximation of a sine wave. A less complex sine-wave generator can be integrated because high-order harmonics of the excitation frequency are attenuated by the sensor itself. A simple square wave is equivalent to a sine wave sampled at Nyquist frequency. Increasing the number of samples per sine-wave period improves the approximation. This also increases circuit complexity and power consumption, but improves the spectral characteristic of the output signal more efficiently. Approximations with eight or more samples per period fulfill the required minimum attenuation of the third harmonic at 937.5 kHz. The signal replicas created by sampling are high enough to be sufficiently attenuated by the resonant sensor. However, the simulated signal-to-noise-plus-distortion ratio (SNDR) of the waveforms is degraded through limited component matching and nonlinearities of the circuit itself. Therefore, a sine-wave approximation with sixteen samples has been chosen for the final implementation, to achieve a reliable performance for the prototype of the eddy-current sensing kHz is generdevice. The excitation frequency of ated by a 5-MHz switched-capacitor (SC) sine-wave generator. Fig. 5 shows a simplified schematic of the circuitry. It includes a fully differential SC integrator with varying coefficients to approximate the sine wave, a passive sample-and-hold stage ( ), and an output buffer to drive the low-ohmic eddy-current sensors. The values of the various capacitors are listed in Table I. The amplitude is controlled by the reference voltage at the generator input. The capacitors , , , , have been chosen to approximate one quarter of a and sine wave within four integration steps. The integrator gain is

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Fig. 6.

Simulated output signal and switching phases of the 312.5-kHz sine-wave generator. Clock frequency of the switches is 5 MHz.

defined by the ratio of , with ranging from to , and varies from 0.383, 0.707, and 0.924, to 1.0. Fig. 6 shows the simulated waveform signal and describes the principle of operation through additional clock phase information. Up- and down-integration is performed by changing the order of the input switching, or phases 3 and 4, respectively, compared to phases 1 and 2 in Fig. 5. The autozero switch (AZ) in the feedback sets the output to ground and prevents drifting of the 312.5-kHz sine wave. Additional correlated double sampling (CDS) has been implemented for offset cancellation [2][4]. Node serves as a virtual ground, and its voltage is (1) , node only sees the difference of the inputThrough of the amplifier and the noise that referred noise voltage was previously sampled. The second term represents the virtual ground error during the active phase 2, assuming a finite opamp gain . The reduction of LF noise is best described by the suppression factor , which is given by
Fig. 7. Measured output spectrum of the eddy-current sensor excited by the 312.5-kHz sine wave. The measurement is compared with a simulated sensor spectrum under square-wave excitation.

with for phase 2 for phase 1. (5)

(2) with for phase 2 for phase 1 ranging from to . is the with input capacitance of the operational amplifier (opamp). The chosen CDS topology prevents the output of the amplifier from switching back to ground during the offset compensation phase, which is an important means to ease the driving requirements of the implemented high-speed opamp. The output current of the amplifier can be further reduced by lower effective capacitances, which are (4) (3)

and are the different capacitances during phases 1 and 2 of the SC common-mode feedback (CMFB) amplifier. The differential excitation of the sensors improves the distortion and keeps the common-mode output swing below 100 mV. The fully integrated approach leads to significantly reduced noise susceptibility due to the proximity of eddy-current sensors and readout circuitry. Consequently, excitation signals of less than 500 mV can be used, resulting in a power reduction of more than an order of magnitude compared to the existing discrete solution. The clock frequency of the SC sine-wave generator is 5 MHz. A fast settling of the output signals requires a sufficiently high unity-gain frequency and a single pole settling behavior of the opamp, whereas accurate settling requires a high dc gain. The SC circuitry is therefore driven by a fully balanced regulated cascode amplifier [5], [6]. The power consumption of the 50-MHz opamp is 1.3 mW, of which about 15% is due to the regulating opamps. Finally, two-stage amplifiers with Miller frequency compensation [7] have been designed for the output buffers to drive the low-ohmic eddy-current sensors. Fig. 7 shows the measured spectrum at the sensor output when excited by the integrated sine-wave generator. The results are compared

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Fig. 8. Principle of operation of the quadruple difference amplifier.

Fig. 9. Top level schematic of the quadruple difference amplifier.

with a simulated square-wave excitation, and demonstrate the excellent attenuation of high-order harmonics. This is especially important with respect to the input-referred transfer function of the digital decimation filter, indicated by the grey bars. It is obvious that square-wave excitation would cause will be severe problems, because all signals at aliased to the baseband. The measured SNDR is more than 58 dB up to 2 MHz. The third harmonic is attenuated by more than 60 dB compared to the fundamental wave at 312.5 kHz, which is sufficiently low to prevent annoying intermodulation products. B. Quadruple Difference Amplifier Differential sensor operation (see Fig. 3) results in two pairs of differential signals per axis. The realization by conventional two-, three-, or four-opamp readout circuits would require a combination of several amplifiers at the expense of power. According to the system requirements, which already have been discussed in detail, it is necessary to achieve an SNDR of more than 60 dB and a unity-gain frequency of about 10 MHz for

proper operation. Finally, power consumption should be as low as 1 mW for cost containment. This can only be accomplished if the number of output stages, which drive low-ohmic loads, is small. The ideal topology would have several high-ohmic input stages, fully differential signal processing, and only one differential output stage. The concept of the differential difference amplifier [8] meets most of these requirements, but has so far been limited to two differential input ports. This has been solved with a novel concept, called the quadruple difference amplifier (QDA). It is possible to read out the difference of two differential signals by doubling the amplifiers differential input ports. Fig. 8 illustrates the principle of operation. The basic concept of the QDA includes four high-impedance differential inputs and only one low-impedance output. The differential , , and two times input voltages are designated ; the output voltage is referred to as . The operation performed by an ideal QDA can be stated as with (6)

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The input voltage generates a differ, which is converted into ential output current a voltage by the output stage of the first amplifier and finally buffered by a second gain stage K. Fig. 9 shows the simplified schematic of the integrated QDA. The circuit is based on a folded-cascode transconductance amplifier with four differential input stages and one differential Miller output stage [7]. Although the difference of the two pairs of differential input and is virtually zero, the input voltages voltages do not have the property of a virtual short circuit, which exists in standard opamp feedback circuits. The input pairs are likely to show large signal behavior. This depends on the drain , and the ratio of current, the overdrive voltage the MOS transistors at the input [9]. Assuming operation in the strong inversion region, the large-signal transfer characteristic is given by
Fig. 10. Measured transfer function of the quadruple differential instrumentation amplifier with resistive feedback network.

(7) . The bias current of the differential input with . For , the characteristic pair is equal to of the transconductance is linear. In order to obtain better than . Due to the improved 0.1% linearity, sensor excitation and signal processing, it is possible to generate lower-level sensor signals of less than 25 mV. Fig. 10 shows the measured transfer function of the 19-dB 11-MHz QDA with resistive feedback, called the quadruple difference instrumentation amplifier (QDIA). The phase margin is more than 80 . The equivalent input noise voltage of the complete amplifier is less than 6 V for a bandwidth of 10 kHz. The overall power consumption of a single QDIA is 0.7 mW at a 2.7-V supply. C. Demodulation and A/D Conversion -modulation technique incorporates several The advantages for the given application. A large oversampling ratio in combination with the preprocessed sensor excitation and the limited bandwidth of the QDIA removes the need for additional antialiasing filters. Furthermore, the device can contain an inherent demodulator at the input, such as modulator [10], the third-order IF-sampling single-bit making an additional demodulator stage unnecessary. Thus, the required 10-bit effective signal resolution can be achieved with limited complexity and low power consumption. Important design parameters are oversampling rate (OSR), modulator, and the quantizaarchitecture and order of the tion levels. The OSR is limited by the predefined master clock of the overall system and by the need to save power. The minimum OSR is defined by the achievable SNDR and by the lowest clock frequency to successfully demodulate the eddy-current sensor signals, which is twice the excitation frequency. A common way to improve the signal-to-noise ratio (SNR) at low OSR is modulator. This improves the to increase the order of the overall noise transfer function (NTF) of the device, but makes a stable operation more difficult, since a cascade of several integrator stages is needed.
CAPACITOR VALUES SINGLE-BIT

TABLE II

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FOR THE THIRD-ORDER IF-SAMPLING MODULATOR (IN PICOFARADS)

The maximum signal-to-quantization-noise ratio (SQNR) achievable by modulators of order as a function of OSR is described in [11]. The analysis is based on the application of an ideal brick-wall decimation filter. In the given application, a modulator third-order IF-sampling single-bit feedforward is most favorable. The achievable SQNR is more than 86 dB for an OSR of 62.5. This corresponds to a sampling of a 10-kHz-wide eddy-current sensor signal at 1.25-MHz sampling frequency. For a second-order modulator, the quantization noise would have been too high, whereas an order of four or higher would have led to an increased circuit complexity and a lower stable input signal range. Coherent demodulation of ) with almost zero the desired signal at 312.5 kHz ( overhead can be achieved by sampling at 1.25 MHz. Fig. 11 shows the corresponding block diagram of the modulator. In order to minimize the in-band quantization noise, an inverse Chebyshev filter has been chosen as the NTF [10]. Fig. 12 modulator. The shows the final schematic of the third-order values of the various capacitors are listed in Table II. The inputs either are connected directly or are cross coupled, resulting in a sequence. multiplication of the samples with a This improves the gain of the modulator by 3 dB, compared to sequence. The phase of the excitation a standard can be configured with respect to the demodulation phase to account for phase shifts of the sensors and the front end. The modulator has a feedforward structure with one feedback coefficient resulting in an additional zero in the NTF at (8)

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Fig. 11.

Block diagram of the

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Fig. 12.

Schematic diagram of the

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180- W regulated cascode amplifier [6] has been integrated. modulator has been Noise and offset performance of the improved by applying the well-known chopper technique [4] for the amplifier in the first integrator stage. The output spectrum of demodulator and converter in Fig. 14 has been measured together with the QDA. It shows the additional zero at 10 kHz of the NTF. The measured SNDR of more than 65 dB proves that the circuitry achieves the required performance. D. Decimation Filter and DSP Interface converters in control It is not very common to use loops. The expected delay of the required decimation filter threatens the stability of the control loop. This characteristic leads to constraints on the impulse response length and on the transition slope. Fig. 15 shows the simplified block diagram of the implemented finite-impulse response (FIR) filter with DSP interface. The digital decimation filter consists of a fourth-order comb filter with a decimation ratio of 12 and one FIR stage of order 23 [12]. This arrangement results in a relatively wide transition band, but it restricts the delay between the effective sampling point and the availability of the sample at the interface to around 130 s. The additional zero in the modulator NTF allows the use of such a wide transition band without severe quantization noise leakage. The filter itself makes use of clock gating wherever possible to reduce power consumption. The influence of digital switching

Fig. 13. Influence of the additional zero on the noise transfer function of the modulator.

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which is near the upper edge of the signal bandwidth. Fig. 13 illustrates the influence of the additional zero on the NTF. This improves the overall SNDR of the modulator by 3 dB, and enables the use of wide transition band filters of lower complexity without severe quantization noise leakage. To drive modulator, a 15-MHz the SC integrator stages of the

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Fig. 14. Output spectrum of the demodulating converter including signal preamplification by the quadruple difference amplifier.

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Fig. 16. Measured output spectrum of complete readout unit including input amplifier, demodulation, modulator, and decimation filter.

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Fig. 15. Simplified block diagram of the implemented decimation filter and DSP interface.

noise on the sensitive analog parts is reduced by restricting the main part of the switching activity to less sensitive phases in the analog part. In measurements, no difference can be seen -modulator noise floor between operation with an in the activated or deactivated digital part. Figs. 16 and 17 show the measured performance of the complete readout unit. The maximum SNDR of 65 dB in Fig. 17 corresponds well with the expected 67 dB of the implemented decimation filter. The DSP interface is an externally clocked general serial interface. The serial clock is independent of the main system clock and can be anywhere from 0 to 20 MHz. To avoid corrupted output values due to the asynchronous interface between the filter and the DSP interface part, updating of the transfer registers in the filter is disabled during the critical phase of the transfer. The interface allows simultaneous sampling and separate readout of the two channels or direct readout of any channel. Furthermore, the chip is configured via this interface. V. SYSTEM-ON-CHIP AND BEARING ASSEMBLY Fig. 18 shows the die photo of the chip (without the quadruple instrumentation amplifier), which measures 3.5 4 mm . Key measured performance parameters are summarized in Table III. The chip has been integrated in a 0.6- m CMOS technology. The quadruple differential instrumentation amplifier has been integrated on a separate test IC, but, in the future, will be included into the system. The eddy-current sensing device will be part of a control loop to adjust a magnetic bearing. It is important to prove the concept in the testbed of an actual bearing assembly. Fig. 19 shows a setup with the magnetic

Fig. 17. Measured performance of readout unit including demodulation, modulator, and decimation filter.

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Fig. 18. Chip micrograph of the eddy-current sensing SOC (QDIA on a second test chip). TABLE III PERFORMANCE SUMMARY OF THE EDDY-CURRENT SENSING SYSTEM-ON-CHIP

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Fig. 21. Power consumption reduction by novel architecture to less than 10% of that of the original device. Fig. 19. Photograph of the test assembly to measure the static performance of the eddy-current sensing SOC together with the magnetic bearing.

VI. CONCLUSION Future applications of magnetic bearings in medicine require a different system design approach to achieve better compromises between size, power consumption, and cost. This is especially important for implanted systems, where the power budget is tight and IC design of the complete mixed-signal SOC is a challenging task. This paper presents a low-power excitation and data acquisition SOC in a standard 0.6- m CMOS technology for eddy-current position sensing in magnetic bearing applications in biomedicine. The need to reduce the power consumption at a required resolution of 10 bit led to the design of a novel eddy-current sensing architecture. The sensor excitation with approximated sine waves, the differential signal acquisition by a quadruple differential instrumentation amplifier, and, finally, the A/D conversion through a third-order IF-sampling modulator avoids an additional antialiasing filter single-bit without degradation in dynamic range or resolution. Fig. 21 shows that the early analysis of the critical building blocks and the combination of different functions into a single device can reduce the power consumption to a value of almost 10 mW. This is less than a 1/15 the power consumption of the original device. Thus, integrated systems-on-chip provide an attractive solution for future fully implantable devices for life-support systems. ACKNOWLEDGMENT The authors are grateful to Dr. Th. Gempp of Levitronix for providing specifications, Dr. H.-G. Reiter of the EEK (ETH Zrich) for the mechanical measurement setup, and to U. Anliker for the analysis of alternative system implementations during his diploma thesis. REFERENCES
[1] S. D. Welsby and T. Hirz, True position measurement with eddy current technology, Sensors, vol. 14, no. 11, 1998. [2] W.-H. Ki and G. C. Temes, Offset-compensated switched-capacitor integrators, in Proc. IEEE Int. Symp. Circuits and Systems, New Orleans, LA, May 1990, pp. 28292832. [3] K. Nagaraj, J. Vlach, T. R. Viswanathan, and K. Singhal, Switchedcapacitor integrator with reduced sensitivity to amplifier gain, Electron. Lett., vol. 22, pp. 11031105, Oct. 1986. [4] C. C. Enz and G. C. Temes, Circuit techniques for reducing the effects of opamp imperfections: Autozeroing, correlated double sampling, and chopper stabilization, Proc. IEEE, vol. 84, pp. 15841614, Nov. 1996.

Fig. 20. Measured static transfer curve of the assembled system; error versus rotor position.

bearing and the eddy-current test printed circuit board. The sensor coils have a diameter of less than 6 mm each and are placed opposite to each other. The presented setup has been developed to measure the static sensorrotor displacement resolution and linearity. The rotor itself is moved by a microadjuster. Fig. 20 illustrates the measured transfer curve of the assembled system. The maximum deviation from the ideal transfer curve is less than 2%, and is determined by the inherent nonlinearity of the sensing principle. However, for the application, the resolution in the operating point (center position) is the most important parameter.

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[5] K. Bult and G. Geelen, A fast-settling CMOS op amp for SC circuits with 90-dB dc gain, IEEE J. Solid-State Circuits, vol. 25, pp. 13791384, Dec. 1990. [6] T. Burger and Q. Huang, On the optimum design of regulated cascode operational transconductance amplifiers, in Proc. Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug. 1998, pp. 203208. [7] K. R. Laker and W. Sansen, Design of Analog Integrated Circuits and Systems. New York: McGraw-Hill, 1994. [8] E. Sckinger, Theory and Monolithic CMOS Integration of a Differential Difference Amplifier. Konstanz, Germany: Hartung-Gorre Verlag, 1989, vol. 1. [9] W. Sansen, Distortion in elementary transistor circuits, IEEE Trans. Circuits Syst. II, vol. 46, pp. 315324, Mar. 1999. modulator for GSM appli[10] T. Burger and Q. Huang, A 3-V 2.8-mW cations, in Proc. IEEE Symp. VLSI Circuits, Honolulu, HI, June 1998, pp. 9091. [11] S. R. Norsworthy, R. Schreier, and G. C. Temes, Eds., DeltaSigma Data Converters: Theory, Design, Simulation. New York: IEEE Press, 1997. [12] R. Reutemann, P. Balmelli, and Q. Huang, A 33-mW 14-bit 2.5-MS/s converter in 0.25-m digital CMOS, in IEEE Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, 2002.

Robert Reutemann (S95) graduated from the Department of Electrical Engineering, Swiss Federal Institute of Technology (ETH), Zrich, Switzerland, in 1997, where he is currently working toward the Ph.D. degree. Since 1998, he has been with the Integrated Systems Laboratory at ETH Zrich as a Research and Teaching Assistant. His main research interests include low-power VLSI digitial signal processing implementations and mixed-signal integrated circuits.

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Jrgen Hertle (S99) was born in Germany in 1968. He received the M.S. degree in electrical engineering from the University Erlangen-Nrnberg, Germany, in 1997. He is currently working toward the Ph.D. degree at the Swiss Federal Institue of Technology (ETH), Zrich, Switzerland, From June 1997 to February 1998, he worked as a Research Assistant at the Fraunhofer Institute of Integrated Circuits, Erlangen, Germany. In March 1998, he joined the Integrated Systems Laboratory at the ETH Zrich as a Research and Teaching Assistant. His research interests include analog integrated circuits, and especially wide-band analog-to-digital converters using folding and interpolating.

Michael Oberle (S95) graduated from the Electrical Engineering Department of the University of Karlsruhe, Germany, in 1993. He received the Ph.D. degree from the Swiss Federal Institute of Technology (ETH), Zrich, Switzerland, in 2002. His general fields of research have been low-power low-voltage analog and mixed-signal integrated circuits for biomedical sensors, wireless telemetry, and space technology.

Qiuting Huang (S86M88SM96F02) graduated from the Department of Precision Instruments, Harbin Institute of Technology, Harbin, China, in 1982. He received the Ph.D. degree from the Katholieke Universiteit Leuven, Departement Elektrotechniek, ESAT-MICAS Laboratories, Heverlee, Belgium, in 1987. Between 1987 and 1992, he was a Lecturer at the University of East Anglia, Norwich, U.K. Since January 1993, he has been with the Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zrich, Switzerland, where he is Professor of Electronics. His general field of research is in radio frequency, analog, and mixed analogdigital integrated circuits and systems. His current research focuses on integrated circuits for both wired and wireless communications.