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  • Spice Example

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    Gaurav Saini
    69 views15 pages
    The document contains the results of several SPICE simulations analyzing MOSFET behavior. It examines how threshold voltage, drain current, and the channel length modulation effect are impacted by varying gate voltage, body bias, channel length, and drain voltage. The key findings are: 1) Threshold voltage was found to be around 0.4V and remained unchanged when drain voltage was increased. 2) Negative body bias increased the threshold voltage, decreasing drain current. 3) Channel length modulation caused drain current to depend on drain voltage in saturation, visible as a positive slope. This effect was greater with shorter channel lengths.

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    The document contains the results of several SPICE simulations analyzing MOSFET behavior. It examines how threshold voltage, drain current, and the channel length modulation effect are impacted by varying gate voltage, body bias, channel length, and drain voltage. The key findings are: 1) Threshold voltage was found to be around 0.4V and remained unchanged when drain voltage was increased. 2) Negative body bias increased the threshold voltage, decreasing drain current. 3) Channel length modulation caused drain current to depend on drain voltage in saturation, visible as a positive slope. This effect was greater with shorter channel lengths.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    69 views15 pages

    Spice Example

    Uploaded by

    Gaurav Saini
    The document contains the results of several SPICE simulations analyzing MOSFET behavior. It examines how threshold voltage, drain current, and the channel length modulation effect are impacted by varying gate voltage, body bias, channel length, and drain voltage. The key findings are: 1) Threshold voltage was found to be around 0.4V and remained unchanged when drain voltage was increased. 2) Negative body bias increased the threshold voltage, decreasing drain current. 3) Channel length modulation caused drain current to depend on drain voltage in saturation, visible as a positive slope. This effect was greater with shorter channel lengths.

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    Download as PDF, TXT or read online from Scribd
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    of 15

    Assignment 2

    Submitted by Gaurav Saini 124070012

    2.a).

    Program

    DC analysis .include tsmc_spice_180nm.txt Mn 1 2 0 4 cmosn L=0.18u W=20u Vds 3 0 dc 50m Vbs 4 0 dc 0 Vgs 2 0 dc 1.8 Vdummy 3 1 dc 0 .dc Vgs 0 1.8 0.1 *.control *run *plot i(Vdummy) *.endc .end

    Threshold Voltage is around 0.4 Volt.

    2.b).

    Program

    DC analysis .include tsmc_spice_180nm.txt Mn 1 2 0 4 cmosn L=0.18u W=20u Vds 3 0 dc 1.8 Vbs 4 0 dc 0 Vgs 2 0 dc 1.8 Vdummy 3 1 dc 0 .dc Vgs 0 1.8 0.1 *.control *run *plot i(Vdummy) *.endc .end

    There is no change in the value of threshold voltage.

    2.c.1).

    Program (comparison with 2.a)

    DC analysis .include tsmc_spice_180nm.txt Mn 1 2 0 4 cmosn L=0.18u W=20u Vds 3 0 dc 50m Vbs 4 0 dc -0.9 Vgs 2 0 dc 1.8 Vdummy 3 1 dc 0 .dc Vgs 0 1.8 0.1 *.control *run *plot i(Vdummy) *.endc .end

    Because of negative Vbs (body to source voltage), threshold voltage of the transistor increases. Hence according to the drain current formula, drain current decreases.

    2.c.2).

    Program (Comparison with 2.b)

    DC analysis .include tsmc_spice_180nm.txt Mn 1 2 0 4 cmosn L=0.18u W=20u Vds 3 0 dc 1.8 Vbs 4 0 dc -0.9 Vgs 2 0 dc 1.8 Vdummy 3 1 dc 0 .dc Vgs 0 1.8 0.1 *.control *run *plot i(Vdummy) *.endc .end

    Same reason for decrease in current as was for 2.c.1.

    2.d)

    Program

    DC analysis .include tsmc_spice_180nm.txt Mn 1 2 0 4 cmosn L=0.18u W=20u Vds 3 0 dc 1.8 Vbs 4 0 dc 0 Vgs 2 0 dc 1.8 Vdummy 3 1 dc 0 .dc Vds 0 1.8 0.1 *.control *run *plot i(Vdummy) *.endc .end

    The positive slope when the device is in saturation is because of the finite resistance between the drain to source terminal. This is also called channel length modulation effect. Because of small channel length current in saturation region depends on the drain to source voltage.

    3.a).

    Program

    DC analysis .include tsmc_spice_180nm.txt Mn1 1 2 3 0 cmosn L=0.18u W=1.8u Mn2 3 2 0 0 cmosn L=0.18u W=1.8u Vds 4 0 dc 1.8 Vgs 2 0 dc 1.8 Vdummy 4 1 dc 0 .dc Vds 0 1.8 0.1 *.control *run *plot i(Vdummy) *.endc .end

    3.b).

    Program

    DC analysis .include tsmc_spice_180nm.txt Mn 1 2 0 0 cmosn L=0.36u W=1.8u Vds 3 0 dc 1.8 Vgs 2 0 dc 1.8 Vdummy 3 1 dc 0 .dc Vds 0 1.8 0.1 *.control *run *plot i(Vdummy) *.endc .end

    Channel length modulation effect is less when we use channel length of larger size. In 3.b, length of channel is twice as compared to the transistor channel length in 3.a. So, channel length modulation effect is more in 3.a. Because of this effect, current in saturation region depends on the drain to source voltage. Hence, Id v/s Vds curve will have some finite slope which is also clearly visible in the output waveform. In case of 3.b, Id v/s Vds slope in saturation region is less.

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