IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO.

1, JANUARY 2002

25

Nanoscale CMOS Spacer FinFET for the Terabit Era

Yang-Kyu Choi, Tsu-Jae King, and Chenming Hu, Fellow, IEEE
AbstractA spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices. Index TermsChemical mechanical polishing (CMP), critical dimension (CD), double-gate, finFET, gate planarization, nanoscale CMOS, silicon-on-insulator (SOI), spacer etch, spacer lithography, thin-body, uniformity.

FinFETs. One drawback of a spacer technology is that it provides only one line width [6]. But by combining a conventional masking process and the spacer process in a novel manner, we overcome this limitation. Si-fin widths down to 6.5 nm have been successfully formed [7]. In this work, the spacer lithography process is used to fabricate planar, CMOS fully depleted double-gate CMOS FinFETs with feature sizes down to 40-nm width Si-fin and 60-nm gate length. II. DEVICE FABRICATION The starting material wafers were (100) SOI. A body doping cm . Any channel doping process concentration is was not used in this work. The SOI Si film was reduced from 100 nm to 50 nm by thermal oxidation and a pad oxide was thermally grown to a thickness of 4 nm to relieve the stress between the nitride hard mask and Si-fin. Silicon nitride was deposited to a thickness of 50 nm on the pad oxide to serve as a hard mask to protect the Si-fin during the subsequent gate poly-SiGe etch. Sacrificial Si Ge was deposited to a thickness of 200 nm by LPCVD on the nitride hard mask and patterned (to support the spacers) with optical lithography and plasma etching. All masking processes used in this work were performed with i-line optical lithography, because its throughput is much better than e-beam lithography and the spacer lithography technology does not require very high resolution lithography. nm) high temperature oxide (HTO) layer A thin ( was then deposited by LPCVD over the patterned sacrificial Si Ge layer. The thickness of HTO at the sidewalls of the sacrificial Si Ge structures determines the final fin width. An extremely small fin width, beyond the lithographic limit as well as very uniform fin width can therefore be obtained with this spacer lithography process. A subsequent anisotropic HTO etch removed the HTO film on top of the sacrificial structure to generate an even number of spacers Si Ge (fins). Fig. 1 shows that the spacer lithography process provides very low CD variation compared to e-beam lithography with SAL601 resist. Sacrificial Si Ge was removed with (5:1:1) H O NH OH H O at 75 C [8]. CD was measured after HTO spacer etching in spacer lithography and after e-beam lithography in conventional lithography. The thickness of the deposited HTO spacer was 40 nm. A negative CD bias nm) was observed and came from 75% step coverage of ( HTO film along the step height of sacrificial Si Ge . The final fin width became 40 nm after Si-fin etch due to the sloped profile of hard mask nitride and Si-fin. The final HTO spacer profile is shown in Fig. 2(a) and it was a ring-like structure. Optical lithography was then used to define large S/D contact pads as shown in Fig. 2(a). Therefore, the channel area was patterned with hard-mask HTO spacers for the Si-fins and

I. INTRODUCTION HIN-BODY SOI devices are promising for scaling CMOS devices into the nanoscale regime. One of the promising structures is the double-gate FinFET [1], [2] using a thin-body (Si-fin). The thin-body minimizes subsurface leakage paths between source and drain and allows for more aggressive gatelength scaling [3]. The original FinFET used a gate-last structure suffered from extra gate-to-source/drain overlap capacitance [1], [2] and a process which involved difficult steps such as sacrificial oxidation, gate spacer process, etc. In this work, we use a more conventional process flow to fabricate quasiplanar FinFETs [4]. Short-channel effects are suppressed by employing a thin-body layer (Si-fin width) that is approximately [2], [5]. This is clearly impossible to achalf of gate length is at complish with standard lithography technologies when the limit of lithography. Uniformity of fin width is especially critical for uniform device characteristics and a high density of Si-fins are required to achieve high-drive current with good layout-area efficiency. Spacer lithography process technology is attractive for overcoming the limits of conventional lithography techniques in terms of pattern fidelity, CD variation, and pattern density. Gate patterning using spacer lithography was reported [6]. The spacer lithography technology described in this paper can produce extremely narrow and uniform Si-fins in double-gate
Manuscript received August 10, 2001; revised September 21, 2001. This work was supported in part by the DARPA AME Program under Contract N66001-97-1-8910 sponsored by the SRC under Contract 2000-NJ-850. The review of this letter was arranged by Editor A. Chatterjee. The authors are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA (e-mail:ykchoi@eecs.berkeley.edu). Publisher Item Identifier S 0741-3106(02)00108-8.

07413106/02$17.00 2002 IEEE

26

IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 1, JANUARY 2002

Fig. 1. CD variations of two lithography technologies (spacer lithography versus conventional lithography) over a whole 4 in wafer. CD uniformity of the spacer technology is overwhelmingly better than e-beam lithography. The 40 nm, T = 50 nm) along inset is a TEM photograph of a Si-fin (W x-x direction in Fig. 2(b).

Fig. 3. Measured CMOS I-V characteristics of spacer FinFET (six fins were defined by spacer lithography). (a) subthreshold I -V characteristics and (b) I -V characteristics for L = 60 nm, W = 40 nm, and T = 2:5 nm. Current is normalized by channel width [2 T (fin height) (6 fins)] conservatively.

nm at 750 C for 12 min and in-situ-doped poly-Si Ge was deposited as a gate material. The Si Ge was planarized by CMP to provide wider process window for lithography and etch. The gate was patterned over the fin using conventional lithography and etching processes as shown in Figs. 2(b) and 2(c). Any gate Si Ge stringers and residues were not left after gate over etch as shown in Fig. 2(c). Source and drain cm were achieved with 30 KeV P implantation at for NMOS and 10 KeV B implantation at cm for PMOS after source and drain mask. Rapid thermal annealing was performed at 900 C and 1 min to activate S/D dopants and cure damages. Windows in the nitride hard mask were opened in the S/D contact regions. No metallization was used for the devices reported here. III. SPACER FINFET PERFORMANCES Fig. 3(a) and 3(b) show CMOS subthreshold and output current characteristic for devices with six fins defined by spacer lithography. NMOS drive current is 400 uA/um and PMOS drive V and V. NMOS current is 350 uA/um at is V and PMOS is V with N Si Ge and cm . Off-state current is 1.4 nA/um at the intersection point of NMOS and PMOS current and V as shown in Fig. 3(a). All currents are normalized with [fin height in Fig. 2(b)] per fin, which is a conservative definition of channel width (With the conventional definition of channel width in double-gate, NMOS current is 800 uA/um and PMOS current is 700 uA/um). The relatively low NMOS drive current is due to degraded electron mobility, likely caused by sidewall roughness of the Si-fin resulting from the dry etch process [9]. This degradation is more severe for NMOS than for PMOS because the inversion charge centroid for electrons is located closer to the SiO interface than for holes. Fig. 4(a) and Fig. 4(b) show subthreshold swing, drain induced barrier lowering (DIBL) and threshold voltage ( ) roll-off characteristics as a function of gate length. Short-channel effects are well down to 70 nm as expected for suppressed for nm and nm, which satisfies subthreshold swing mV/dec, mV/V, and V. For thinner

Fig. 2. (a) Spacer FinFET structure tilted SEM photograph of photo-resist profile for S/D contact pads and HTO spacer profile for narrow Si-fins, respectively, and (b) schematic diagram of spacer FinFET, and (c) SEM photograph of planarized gate profile over six fins defined by spacer lithography.

photo-resist for the S/D contact regions as shown in Fig. 2(a). One drawback of the spacer technique is that only one line width is provided. Variable fin widths can be achieved by using photo-resist to define the fins as well as the S/D contact pads [7]. In this work, spacers were used for the smallest features while the S/D contact pad mask was used to define wider fins. There were no ring-like structures because photo-resist covered the part of ring-shapes. After anisotropic Si-fin etch, the Si-channel areas were defined. A sacrificial oxide was grown to a thickness of 10 nm at 900 C in dry O ation step was used to remove etch damage. A 10-nm thermal oxide was grown for 12 min at 900 C in O . It was removed using diluted HF before gate oxidation and HTO spacers were also removed. The gate oxide with 2.5 nm gate oxide was grown to a thickness of 2.5

CHOI et al.: NANOSCALE CMOS SPACER FINFET FOR THE TERABIT ERA

27

comes from doubled fin density and another factor of two comes from the double gate structure. Sub-60-nm FinFETs are demonstrated and show excellent short-channel behavior. ACKNOWLEDGMENT The authors would like to thank the University of CaliforniaBerkeley Microlab staffs for their support in device fabrication. REFERENCES
[1] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, FinFET-A self-aligned double-gate MOSFET scalable to 20 nm, IEEE Trans. Electron Devices, vol. 47, pp. 23202325, Dec. 2000. [2] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Cang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, Sub 50-nm FinFET:PMOS, in IEDM Tech. Dig., 1999, pp. 6770. [3] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, Ultra-thin-body SOI MOSFET for deep-sub-tenth micron era, IEEE Electron Device Lett., vol. 21, pp. 254255, May 2000. [4] N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W. Lee, T.-J. King, J. Bokor, and C. Hu, Quasi-planar NMOS FinFETs with sub-100 nm gate lengths, in 59th Device Res. Conf., 2001, pp. 2627. [5] L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, Gate length scaling and threshold voltage control of double-gate MOSFETs, in IEDM Tech. Dig., 2000, pp. 719722. [6] J. T. Horstmann, U. Hilleringmann, and K. F. Goser, Matching analysis of deposition defined 50-nm MOSFETs, IEEE Trans. Electron Devices, vol. 45, pp. 299306, Jan. 1998. [7] Y.-K. Choi, T.-J. King, and C. Hu, Spacer FinFET: Nano-scale CMOS technology for the terabit era, Int. Semiconduct. Device Res. Symp., pp. 543546, 2001. [8] F. S. Johnson, D. S. Miles, D. T. Grider, and J. J. Wortman, Selective chemical etching of polycrystalline SiGe alloys with respect to Si and SiO , J. Electron. Mater., vol. 21, pp. 805810, 1992. [9] C. J. Petti, J. P. McVittie, and J. D. Plummer, Characterization of surface mobility on the sidewalls of dry-etched trenches, in IEDM Tech. Dig., 1988, pp. 104107.

Fig. 4. Short-channel characteristics of spacer FinFETs with W 40 nm and T = 2:5 nm. (a) subthreshold swing (V = 1:0 V) and DIBL (b) threshold voltage (V = 1:0 V) roll-off characteristics.

, more aggressive gate length scaling can be allowed in a given body thickness; i.e., scale length can be reduced. Shortchannel effects of PMOS are slightly worse than for NMOS because boron diffusivity in PMOS S/D is larger than phosphorus diffusivity in NMOS S/D for the same RTA condition. IV. CONCLUSION A spacer lithography technology is applied to the fabrication of planar, fully depleted CMOS FinFETs for the first time. It provides a minimum feature size beyond the lithographic limit, better CD uniformity, and twice the fin density. In principle, a FinFET based on this technology produces four times the drive current of a conventional bulk-CMOS device as a factor of two