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Exhibit A

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GREGORY P. STONE (SBN 078329) gregory.stone@mto.com KATHERINE K. HUANG (SBN 219798) katherine.huang@mto.com PETER E. GRATZINGER (SBN 228764) peter.gratzinger@mto.com KEITH R.D. HAMILTON (SBN 252115) keith.hamilton@mto.com DAVID H. PENNINGTON (SBN 272238) david.pennington@mto.com MUNGER, TOLLES & OLSON LLP 355 South Grand Avenue, 35th Floor Los Angeles, CA 90071-1560 Telephone: (213) 683-9100 Facsmile: (213) 687-3702 PETER A. DETRE (SBN 182619) peter.detre@mto.com MUNGER, TOLLES & OLSON LLP 560 Mission Street, 27th Floor San Francisco, CA 94105 Telephone: (415) 512-4000 Facsimile: (415) 512-4077 Attorneys for Plaintiff RAMBUS INC. UNITED STATES DISTRICT COURT NORTHERN DISTRICT OF CALIFORNIA SAN FRANCISCO DIVISION RAMBUS INC., Plaintiff, v. LSI CORPORATION, Defendant. RAMBUS INC., Plaintiff, v. STMICROELECTRONICS N.V.; STMICROELECTRONICS INC., Defendants. Case No. 3:10-cv-05446 RS [PROPOSED] RAMBUS INC.S RESPONSE TO DEFENDANTS SUR-REPLY CLAIM CONSTRUCTION BRIEF Date: Time: Judge: August 29, 2012 10:00 a.m. Hon. Richard Seeborg

Case No. 3:10-cv-05449 RS

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I.

INTRODUCTION In their sur-reply brief, Defendants seek to extend the Federal Circuits holding that a

memory device is not necessarily a single chip to terms at issue herecontroller/controller device, and synchronous DRAM devicethat the Federal Circuit did not address. As set forth below, these terms are properly construed as single chips, and the Federal Circuit opinion does not indicate otherwise. With respect to whether a memory device can include a controller, the court held that it cannot include a CPU or bus controller. In re Rambus, No. 2011-1247, slip op. at 15 (Fed. Cir. Aug. 15, 2012). Because a synchronous DRAM device is a particular type of memory device, the construction of this term should include the same limitation. II. CONTROLLER/CONTROLLER DEVICE Defendants concede that the terms controller and controller device were not considered by the Federal Circuit, but argue that the courts reasoning and analysis is relevant to the proper construction of those terms. Sur-reply at 2. Each term, however, should be construed on its own merits, and, in arriving at its conclusion that a memory device is not limited to a single chip, the Federal Circuit relied in part on considerations unique to that term. For example, the court considered claim differentiation arguments, slip op. at 11-12, unrelated to the terms controller or controller device. For the reasons stated in Rambuss opening and reply briefs, these terms should be construed as integrated circuit devices, i.e. single chips. III. SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY DEVICE A. A Synchronous DRAM Device is a single chip

Defendants effort to stretch the Federal Circuits decision regarding memory device to require that synchronous dynamic random access memory device be construed as including multi-chip devices cannot succeed. The Federal Circuit did not consider whether the latter, narrower term could encompass more than a single chip, and there was no occasion for it to do so: while the PTO examiner, the Board of Patent Appeals and Interferences (BPAI), and the Director of the PTO in his brief to the Federal Circuit maintained that a memory device is not a term of art and not necessarily limited to a single chip, they all agreed with Rambus that a DRAM device is a term of art referring to a single chip. For example, among its claim differentiation
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arguments to the Federal Circuit, the Director pointed to claims of U.S. Patent No. 5,841,715. Brief for Appellee-Director of the U.S.P.T.O., Aug. 5, 2011 (attached hereto as Ex. 1), at 33. While claim 1 of the 715 patent recites a memory device, dependent claim 3 provides that the [memory] device comprises a dynamic random access memory (DRAM) device. Id. (quoting 715 patent). The Director argued that [t]he use of the open-ended term comprising in claim 3 . . . implies that the memory device could encompass more than just a single DRAM chip, thereby suggesting that a memory device is not limited to a single chip. Id. (emphasis added). Thus, in making his argument, the Director interpreted the dynamic random access memory (DRAM) device of claim 3 as a single DRAM chip. Accord BPAI Decision on Appeal, No. 2010011178 (attached as Ex. I to Detre Decl. in support of Rambuss Opening Claim Construction Brief), at 29 (making similar claim differentiation argument); id. at 24, n.7 (quoting Examiners acknowledge[ment] that the memory devices such as ROM, SRAM, and DRAM are defined as being a single integrated memory chip.) (emphasis added). Further, contrary to Defendants argument, Sur-reply at 2, not every device term is entitled to a broad construction. Cf. Rambus Inc. v. Infineon Technologies, 318 F.3d 1081, 1091 (Fed. Cir. 2003) (construing integrated circuit device as a single chip); BPAI Decision on Appeal, No. 2011-013706 (attached hereto as Ex. 2), at 8 (construing synchronous semiconductor memory device as a single chip). In their sur-reply, Defendants rely on U.S. Patent No. 5,638,334. Sur-reply at 3. Defendants note that the Federal Circuit, in the course of discussing claim differentiation arguments, found that claim 6 of the 334 patent, which restricted the memory device of claim 1 to being formed on a single semiconductor substrate, could be viewed as limiting the broader term memory device to a single chip. Id. The Defendants find it significant that the Federal Circuit did not then turn to claim 7 of the 334 patent, which provides that the memory device [of claim 1] is a dynamic random access memory device, and state that it too is limited to a single chip. But nothing can be read into the fact that the court did not address claim 7. In that portion of the opinion, the Federal Circuit was addressing the claim differentiation argument made by the PTO, not cataloguing all of Rambuss patent claims that are, in its view, limited to a single chip. Slip op. at 11-12. And there would have been no reason for the PTO to refer to
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claim 7, because that claim does not support the claim differentiation argument it was making. There are various types of single-chip memory devices, including ROM, SRAM, and DRAM devices. See, e.g., 916 patent, col. 1:53-55 (referring to the most widely used Dynamic Random Access Memory (DRAM), Static RAM (SRAM) and Read Only Memory (ROM) devices); id., Fig. 2 (illustrating DRAM and ROM chips). Thus, even though a DRAM device is a single chip, the fact that claim 7 restricts a memory device to a DRAM device does not imply that a memory device is broader than a single chip; rather, the term memory device could simply encompass all single-chip memory devices, while claim 7 specifies that the memory device is a DRAM device, rather than an SRAM, ROM, or other type of single-chip memory device. B. A Synchronous DRAM Device cannot include a bus controller

Defendants argue in their sur-reply that, because the Federal Circuit held that a memory device could include some control functionality, the Court should reject that part of Rambuss proposed construction of synchronous dynamic random access memory device that specifies that such a device does not include a memory controller. Sur-reply at 3-4. The Federal Circuit was clear, however, that the construction of memory device should specify that such a device does not include a CPU or bus controller. Slip op. at 15 ([W]e construe a memory device as a component of a memory subsystem, not limited to a single chip, where the device may have a controller that, at least provides the logic necessary to receive and output specific data, but does not perform the control function of a CPU or bus controller.) (emphasis added). A synchronous DRAM device is a particular type of memory device; it follows that synchronous DRAM device should likewise be construed as not including a CPU or bus controller. Moreover, the Federal Circuit opinion provides examples of bus controllers that cannot be included in a memory device. First, the Federal Circuit considered the bus interface unit (BIU) in the prior art Jackson patent and found that because Rambus exclude[d] the function of Jacksons BIU during prosecution this prevents the memory device from containing a global bus controller or CPU. Slip. op. at 14-15. The prosecution history of the 918 patent makes clear the functionality that Rambus excluded and that the Federal Circuit relied on in finding that a memory device could not include a bus controller. During prosecution, the examiner had
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rejected Rambuss pending claims on the ground that the BIU, combined with conventional memory chips, met Rambuss claim limitations with Jacksons data length transfer information corresponding to the block size information in Rambuss claims. Rambus distinguished Jackson, pointing out that it was the BIU, not the memory devices, in Jackson that received the data length transfer information and the clock signal. Amendment, Jul. 23, 1999, at 10-11 (attached hereto as Ex. 3). The functionality that Rambus identified as distinguishing the BIU from a memory device was that the BIU (1) receives and decodes [the data length transfer information from the microprocessor] and, based thereon, generates and applies the addresses and control signals (i.e., OE\, RAS\, CAS\) necessary to obtain the number of bytes of data defined by data length transfer information, and (2) fetches the data returned from the memory, buffers and aligns that data, and then transfers it to the microprocessor synchronously with respect to an external clock signal. Id. Second, the Federal Circuit also found that the memory stick described in the patent specification is not a memory device. Slip op. at 9. Such a memory stick consists of a number of memory chips on a primary bus unit attached to a transceiver device. 916 patent, col. 19:51 - 20:35 & Fig. 9. The transceiver device connects the memory stick to a transceiver bus and is quite simple in function: the transceiver device detects request packets (specifying, for example, a read or write request) that are sent by master devices on the transceiver bus and transmits them to the memory chips on the primary bus unit, and transmits all the data required for the transaction between the primary bus unit and the transceiver bus. Id. Because it found that such a memory stick is not a memory device, the Federal Circuit must have concluded that the transceiver device described in the specification is a bus controller. Thus the construction of synchronous DRAM device should specify that it cannot include a CPU or bus controller, where the category of bus controllers includes any device with the functionality of the BIU in Jackson as set forth in the prosecution history of the 918 patent, or of the transceiver device in a memory stick described in the patent specification. IV. CONCLUSION Rambus respectfully submits that the Court should adopt its proposed claim constructions.
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DATED: August 27, 2012

MUNGER, TOLLES & OLSON LLP By: /s/ Peter A. Detre Peter A. Detre Attorneys for Plaintiff RAMBUS INC.

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