ANNEXURES

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ANNEXURE-1

DEFINITIONS AND EXPLANATIONS

Item
Analog Input Point Balanced transmission Bit Rate

Definition
Station equipment (Master or Remote) that inputs the analog quantity or an analog function. Type of data exchange, in which each station, master or slave may initiate a message with master or slave unit The number of bits transferred in a given time interval. Bits per second (BPS) are the measure of the rate at which bits are transmitted.

Channel

A single path for transmitting of electric signals, usually distinct from other parallel paths. A band of frequencies.

Clients Clients are computers that are connected to server based network. Controlled Stations Digital Input Point Ethernet Remote locations like Traction Sub Station. Switching post or Sub Sectioning Post carrying out switching operations. Station equipment (Master or Remote) that accepts a digital signal for the function of indication Ethernet is the most popular networking architecture and can be implemented in either star or bus topology. The data transmission rate normally is 10 Mbps. For fast Ethernet the date transmission rate is 100 Mbps. Frequency shift keying A form of modulation which encodes digital data by modulating the carrier frequency between two or more values. Graphic User Interface The process in which an application/program on the computer interacts with the user through pictures and other visual clues. Master station Networking Operating System Station which controls the communication sequence in a distributed system. A group of computers linked together to communicate with each other and share devices like hard disks, printers etc. Operating system is software that controls the computer and 60

its resources such as memory, hard disk as well as device connected to the computer such as computers printers scanners. Phase Shift keying Polling This form of keying encodes digital data by shifting phase. For example 180 degree could be 0 and 0 degree can be 1. The process by which a data acquisition system selectively requests data from one or more of its remote terminals. A remote terminal may be requested to respond with all, or a selected portion of the data available. Protocol Scan A strict procedure required initiating and maintaining communication. The process by which a data exchange initiated by the primary station. the network and its resources like shared printers, applications and disk space. Server Server is a computer that is dedicated to managing a network. It controls access to

ANNEXURE-2

DATA SHEETS
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A.2.1 LPC2378 A.2.2 MAX 3245 A.2.3 MAX 3070

A 2.1: LPC2378
Single-chip 16-bit/32-bit microcontroller; 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
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1. General description
The LPC2378 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 512kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. The LPC2378 is ideal for multipurpose serial communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), USB full speed device with 4kB of endpoint RAM, four UARTs, two CAN channels, an SPI interface, two Synchronous Serial Ports (SSP), three I2C interfaces, an I2S interface, and an External Memory Controller (EMC). This blend of serial communications interfaces combined with an on-chip 4 MHz internal oscillator, SRAM of 32kB, 16kB SRAM for Ethernet, 8kB SRAM for USB and general purpose use, together with 2kB battery powered SRAM make this device very well suited for communication gateways and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, PWM unit, a CAN control unit, and up to 104 fast GPIO lines with up to 50 edge and up to four level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.

2. Features

ARM7TDMI-S processor, running at up to 72MHz.

Up to 512kB on-chip flash program memory with In-System Programming (ISP) and In-

Application Programming (IAP) capabilities. Flash program memory is on the ARMlocal bus for high performance CPU access.

32kB of SRAM on the ARM local bus for high performance CPU access. 16kB SRAM for Ethernet interface. Can also be used as general purpose SRAM. 8kB SRAM for general purpose DMA use also accessible by the USB. Dual Advanced High-performance Bus (AHB) system that provides for simultaneous Ethernet

DMA, USB DMA, and program execution from on-chip flash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem.

EMC provides support for static devices such as flash and SRAM as well as off-chip memory Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts. General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial

mapped peripherals.

interfaces, the I2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port, as well as for memory-to-memory transfers.

Serial Interfaces Ethernet MAC with associated DMA controller. These functions reside on an independent

AHB bus.

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USB 2.0 full-speed device with on-chip PHY and associated DMA controller. Four UARTs with fractional baud rate generation, one with modem control I/O, one with

IrDA support, all with FIFO. CAN controller with two channels. SPI controller. Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the

SPI port, sharing its interrupt and pins. These can be used with the GPDMA controller. Three I2C-bus interfaces (one with open-drain and two with standard port pins). I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the Other peripherals: SD/MMC memory card interface. 104 General purpose I/O pins with conFigurable pull-up/down resistors. 10-bit ADC with input multiplexing among 8 pins. 10-bit DAC. One PWM/timer block with support for three-phase motor control. The PWM has two Real-Time Clock (RTC) with separate power pin, clock source can be the RTC oscillator or

GPDMA.

external count inputs. the APB clock.

2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of

the chip is powered off. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC

oscillator, or the APB clock. Standard ARM test/debug interface for compatibility with existing tools. Emulation trace module supports real-time trace. Single 3.3 V power supply (3.0 V to 3.6 V). Three reduced power modes: idle, sleep, and power-down. Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and

PORT2 can be used as edge sensitive interrupt sources. Processor wake-up from Power-down mode via any interrupt able to operate during Power-

down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt).

Two independent power domains allow fine tuning of power consumption based on needed

features Each peripheral has its own clock divider for further power saving. Brownout detect with separate thresholds for interrupt and forced reset. On-chip power-on reset.

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On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz. 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as the

system clock. When used as the CPU clock, does not allow CAN and USB to run. On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high

frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.

Boundary scan for simplified board testing. Versatile pin function selections allow more possibilities for using on-chip peripheral

functions.

3. Applications
Industrial control Medical systems Protocol converter Communications

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8. Limiting values
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Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) Parameter supply voltage (3.3 V) Conditions core and external rail Min 3.0 Max 3.6 Unit V

VDD(DCDC)(3V3) DC-to-DC converter supply voltage (3.3 V)

3.0

3.6

VDDA

analog 3.3 V pad supply voltage

0.5

+4.6

Vi(VBAT) Vi(VREF) VIA

input voltage on pin VBAT input voltage on pin VREF analog input voltage

for the RTC

0.5 0.5

+4.6 +4.6 +5.1

V V V

on ADC related pins

0.5

VI

input voltage

5 V tolerant I/O pins; only valid when the VDD(3V3) supply voltage is present

[2]

0.5

+6.0

other I/O pins [2][3]

0.5

VDD(3V3) +0.5

IDD ISS Tstg Ptot(pack)

supply current ground current storage temperature [5] total power dissipation (per package) based on Package heat transfer, not device power consumption

per supply pin

[4]

65 -

100 100 +150 1.5

mA mA C W

per ground pin [4]

Vesd

electrostatic discharge voltage

human body model; [6] all pins

2000

+2000

[1] The following applies to the Limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

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otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6 V. [4] The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k eries resistor s

A.2.2 RS-232 Transmitters

.

1A Supply Current, 1Mbps, 3.0V to 5.5V, RS-232 Transceivers with AutoShutdown Plus
The transmitters are inverting level translators that convert CMOS-logic levels to 5.0V EIA/TIA-232 levels. The

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MAX3224/MAX3226/MAX3244

guarantee

250kbps

data

rate

(1Mbps

for

the

MAX3225/MAX3227/MAX3245) with worst-case loads of 3k n parallel with 1000pF, providing compatibility i with PC-to-PC communication software (such as LapLink ). Transmitters can be paralleled to drive multiple receivers. Figure 1 shows a complete system connection.When FORCEOFF is driven to ground or when the Auto-Shutdown Plus circuitry senses that all receiver and transmitter inputs are inactive for more than 30sec, the transmitters are disabled and the outputs go into a high impedancestate. When powered off or shut down, the outputs can be driven to 12V. The transmitter inputs do not have pull-up resistors. Connect unused inputs to GND or VCC.

Figure 1. Interface Under Control of PMU

Figure 2a) Older RS-232:Powered down UART draws current from active receiver output in shutdown

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Figure2 b) In shutdown R2OUTB is used to monitor external devices and R2OUT is three stated;eliminating a current path through the UARTs protection mode

Table 1. Output Control Truth Table

X = Dont care *INVALID connected to FORCEON **INVALID connected to FORCEON and FORCEOFF

RS-232 Receivers

The receivers convert RS-232 signals to CMOS-logic output levels. The MAX3224MAX3227 feature inverting outputs that always remain active (Table 1). The MAX3244/MAX3245 have inverting three-state outputs that are high impedance when shut down (FORCEOFF= GND) (Table 1). The MAX3244/MAX3245 feature an extra, always active, noninverting output, R2OUTB. R2OUTB output monitors receiver activity while the other receivers are high impedance,

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allowing Ring Indicator applications to be monitored without forward biasing other devices connected to the receiver outputs. This is ideal for systems where VCC is set to ground in shutdown to accommodate peripherals such as UARTs (Figure 2a, b). The MAX3224 MAX3227/MAX3244/MAX3245 feature an INVALID output that is enabled low when no valid RS-232 voltage levels have been detected on all receiver inputs. Because INVALID indicates the receiver inputs condition, it is independent of FORCEON and FORCEOFF states

AutoShutdown Plus Mode The MAX3224MAX3227/MAX3244/MAX3245 achieve a 1A supply current with Maxims AutoShutdown Plus feature, which operates when FORCEOFF is high and a FORCEON is low. When these devices do not sense a valid signal transition on any receiver and transmitter input for 30sec, the on-board charge pumps are shut down, reducing supply current to 1A. This occurs if the RS-232 cable is disconnected or if the connected By connecting FORCEON to INVALID, the MAX3224 MAX3227/MAX3244/MAX3245 shut down when no valid receiver level and no receiver or transmitter edge is detected for 30sec, and wake up when a valid receiver level or receiver or transmitter edge is detected.By connecting FORCEON and FORCEOFF to INVALID, the MAX3224MAX3227/MAX3244/MAX3245 shutdown when no valid receiver level is detected and wake up when a valid receiver level is detected (same functionality as AutoShutdown feature on MAX3221/MAX3223/MAX3243).A mouse or other system with AutoShutdown Plus may need time to wake up. Figure 5 shows a circuit that forces the transmitters on for 100ms, allowing enough time for the other system to realize that the MAX3244/MAX3245 is awake. If the other system outputs valid RS-232 signal transitions within that time, the RS-232 ports on both systems remain enabled.

MAX3070E - 3.3V, RS-485/RS-422 Transceivers

FEATURES:
3.3V Operation Electrostatic Discharge (ESD) Protection for RS-485 I/O Pins 15kV Human Body Model True Fail-Safe Receiver While Maintaining EIA/TIA-485 Compatibility Hot-Swap Input Structure on DE and RE Enhanced Slew-Rate Limiting Facilitates Error- Free Data Transmission Low-Current Shutdown Mode Allows Up to 256 Transceivers on the Bus Available in Industry-Standard 8-Pin SO Package

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General Description:
The MAX3070E 3.3V, 15kV ESD-protected, RS-485/RS-422 transceivers feature one driver and one receiver. These devices include fail-safe circuitry, guaranteeing a logichigh receiver output when receiver inputs are open or shorted. The receiver outputs a logic high if all transmitters on a terminated bus are disabled (high impedance). The MAX3070E includes a hot-swap capability to eliminate false transitions on the bus during power-up or hot insertion. The MAX3070E feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 250kbps.. The MAX3070E are intended for full-duplex communications. The MAX3070E transceivers draw 800A of supply current when unloaded or when fully loaded with the drivers disabled. All devices have a 1/8-unit load receiver input impedance, allowing up to 256 transceivers on the bus.

Applications Lighting Systems Industrial Control Telecom Security Systems Instrumentation

ABSOLUTE MAXIMUM RATINGS DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V 10%, TA =TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 3.3V and TA = +25C.) (Note 1) . (All voltages referenced to GND) Supply Voltage (VCC).............................................................+6V Control Input Voltage (RE, DE, SLR, H/F, TXP, RXP)......................................................-0.3V to +6V Driver Input Voltage (DI)...........................................-0.3V to +6V Driver Output Voltage (Z, Y, A, B) .............................-8V to +13V Receiver Input Voltage (A, B)....................................-8V to +13V Receiver Input Voltage Full Duplex (A, B) ..................................................-8V to +13V Receiver Output Voltage (RO)....................-0.3V to (VCC + 0.3V) Driver Output Current .....................................................250mA Continuous Power Dissipation (TA = +70C) 8-Pin SO (derate 5.88mW/C above +70C) .................471mW 8-Pin Plastic DIP (derate 9.09mW/C above +70C) .....727mW 14-Pin SO (derate 8.33mW/C above +70C) ...............667mW 14-Pin Plastic DIP (derate 10.0mW/C above +70C) ...800mW Operating Temperature Ranges MAX307_EE_ _ ................................................-40C to +85C MAX307_EA_ _ ..............................................-40C to +125C Junction Temperature......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
(Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

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absolute maximum rating conditions for extended periods may affect device reliability)

DC ELECTRICAL CHARACTERISTICS

(VCC = 3.3V 10%, TA =TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 3.3V and TA = +25C.) (Note 1)

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC = 3.3V 10%, TA =TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 3.3V and TA = +25C.) (Note 1)

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Note 1: All currents into the device are positive. All currents out of the device are negative. All voltages are referred to device ground, unless otherwise noted. Note 2: VOD and VOC are the changes in VOD and VOC, respectively, when the DI input changes state. Note 3: The short-circuit output current applies to peak current just prior to foldback current limiting. The short-circuit foldback output current applies during current limiting to allow a recovery from bus contention .

Detailed Description
The MAX3070EMAX3079E high-speed transceivers for RS-485/RS-422 communication contain one driver and one receiver. These devices feature fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted, or when they are connected to a terminated transmission line with all drivers disabled (see the Fail-Safe section). The MAX3070E also features a hotswap capability allowing line insertion without erroneous data transfer The MAX3070E reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 250kbps. All devices operate from a single 3.3V supply. Drivers are output short-circuit current limited. Thermal-shutdown circuitry protects drivers against excessive power dissipation. When activated, the thermal-shutdown circuitry places the driver outputs into a high-impedance state.

Receiver Input Filtering

The receivers of the MAX3070E when operating in 250kbps or 500kbps mode, incorporate input filtering in addition to input hysteresis. This filtering enhances noise immunity with differential signals that have very slow rise and fall times. Receiver propagation delay increases by 25% due to this filtering.

Fail-Safe

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The MAX3070E family guarantees a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver input threshold between -50mV and -200mV. If the differential receiver input voltage (A - B) is greater than or equal to -50mV, RO is logic high. If A - B is less than or equal to -200mV, RO is logic low. In the case of a terminated bus with all transmitters disabled, the receivers differential input voltage is pulled to 0V by the termination. With the receiver thresholds of the MAX3070E family, this results in a logic high with a 50mV minimum noise margin. Unlike previous fail-safe devices, the -50mV to -200mV threshold complies with the 200mV EIA/TIA-485 standard.

Hot-Swap Capability
When circuit boards are inserted into a hot, or powered, backplane, differential disturbances to the data bus can lead to data errors. Upon initial circuit board insertion, the data communication processor undergoes its own power-up sequence. During this period, the processors logic-output drivers are high impedance and are unable to drive the DE and RE inputs of these devices to a defined logic level. Leakage currents up to 10A from the high-impedance state of the processors logic drivers could cause standard CMOS enable inputs of a transceiver to drift to an incorrect logic level. Additionally, parasitic circuit board capacitance could cause coupling of VCC or GND to the enable inputs. Without the hot-swap capability, these factors could improperly enable the transceivers driver or receiver. When VCC rises, an internal pulldown circuit holds DE low and RE high. After the initial power-up sequence, the pulldown circuit becomes transparent, resetting the hot-swap tolerable input.

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