Test Fundamentals

VLSI Design: An Interdisciplinary Challenge

Boolean Algebra (George Boole, 1886) Logic Synthesis (Claude Shannon, 1936) Finite Automata and Sequential Machines (1950 -1960) Circuit Theory, Analog and Mixed Signal Design Evolution of computer systems and software techniques Graph Theory Quantum Mechanics Semiconductor Physics Semiconductor Devices (e.g., Transistors) VLSI Design Micro-electronics, IC Fabrication Technology Photolithography, MBE Synthesis, Testing, Verification Techniques

Physical Design

Electronic Design Automation (CAD Tools) Computational Geometry Design and Analysis of Algorithms

What is VLSI testing?

VLSI

testing

is

to

test

the

behavioral

correctness of a VLSI design, i.e., testing is defined to be the process by which a defect in the digital system can be exposed.

Why Testing is important?

Circuits are used in highly sophisticated applications A single failure may cause large deviation from the expected performance The world is rushing towards more and more precision in every level Example: 1995: Intel Pentium FP Bug Company took $450 M charge to cover replacement costs Some companies are spending millions of dollars every year in testing

Why Systems fail

Human Design errors
Manufacturing Defects : IC processing/packaging PCB assembly and wiring errors Installation errors Operational (field) failures
- Environment, Temperature, Humidity, Vibration Power supply fluctuations

Wear and Tear : friction, corrosion

Human operator errors

VLSI Design Cycle

Detection of Defects
Detection of defects may be done in three phases: Design verification involves ascertaining logical correctness and timing behavior of the circuit through simulation Manufacturing tests check for the specific types of defects produced during fabrication. Field test (day-to-day testing) detects the systems when the system is in the field.

Defect , Fault and Error

Defect: refers to a physical imperfection in the circuit or system Fault : an actual defect that occurs in digital circuit or device. When a vector is applied to the faulty circuit which produces an incorrect response, an error is said to have occurred.

Faults and Errors

If a line in a chip breaks, a fault has occurred. When this fault is exposed at the circuit outputs by some input vector, an error results. This error is manifested as an incorrect logic value at one or more of the circuit outputs.
Test Vectors CUT Response

Faults

A fault which can change the logic value on a line in the circuit from logic 0 to logic 1 or vice versa is called a logical fault.

if the fault causes some parameters of the circuit to change, such as the current drawn by the circuit, then it is termed parametric.

Faults

Faults are classified into 3 types: a) Transient: A fault is called transient if it is only present for a small duration. b) Intermittent: A fault is intermittent if it appears regularly but is not present continuously. c) Permanent: If a fault is present continuously, it is called permanent.

Transient Faults

have been the dominant cause of system failures. may be caused by -particle radiation, power supply fluctuation, etc. No permanent damage is done by these faults. are hard to detect because of their short duration. With the possibility of reduced voltage levels for VLSI and the resultant decrease in noise margins, system susceptibility to transient fault is likely to increase.

Intermittent faults

are also difficult to detect and locate. can be caused by - loose connections, - bad designs, - environmental effects like temperature and humidity variations.

Permanent faults

are the easiest to detect. are predominantly caused by - shorts and opens in VLSI circuits.

Fault Detection and Fault Location

Fault detection means the discovery of something wrong in a digital system or circuit. Fault location means the identification of the faults with components, functional modules, or subsystems, depending on the requirements. It is very difficult to locate a fault. Fault diagnosis includes both fault detection and fault location.

Verification vs. Test

Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods.

Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices.

Performed once prior to manufacturing. Responsible for quality of design.

Challenge
i1 i2 i3 . . . in . . . om o1 o2 o3

Apply all possible input patterns (2n) For n=50, a test equipment operating at 1 MHz will take about 9500 months!

Challenge
i1 i2 i3 . . . in . . . om o1 o2 o3

A subset of possible input patterns should be selected

Challenge

Challenge

So the solution is... Based on a Fault Model select a set of input vectors The patterns are called test vectors

Model Faults
Numerous

possible physical failures in a

large circuit Very difficult to detect a physical failure Many physical failures have the same effect on the logic We need to consider only the effect of physical failures on the logic Effects of physical failures are described at higher level : fault Model

Famous fault models Stuck-at Single and multiple Bridging - AND bridge and OR bridge Delay -Path delay, gate delay and Transition delay

Single Stuck-at Fault

Three properties define a single stuck-at fault
Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults

c
1 0

a b

d e f

s-a-0

j h i k

0(1) 1(0) 1

g
1

Test vector for h s-a-0 fault

Single stuck-at Fault

Assumption - Only one line is Faulty 2n possibilities

s-a-0 s-a-0 s-a-1 s-a-1 s-a-1 s-a-0

Single Stuck-At Faults

Test Vector 0 1 1 1 1/0 stuck-at-0 0 Faulty Response True Response

1/0

Assumptions:

Only one line is faulty. Faulty line permanently set to 0 or 1. Fault can be at an input or output of a gate.

Multiple stuck-at

Assumption: Several stuck-at faults can be simultaneously present 3n - 1 possibilities

s-a-0 s-a-1 s-a-1

26 possibilities

Bridging Faults
OR-bridging
A B A B

AND-bridging
A B

A B

Bridging Fault
Improper masking or etching Loose or excess bare wires Defective printed circuit boards Shorting of pins of a chip

Delay faults
Failures that cause logic circuits to malfunction at the desired clock rate are modeled as delay faults Types of delay faults: a) Path Delay Fault b) Gate Delay Fault c) Transition Fault

Path-Delay Fault
A circuit is said to have a path-delay fault, if the total delay along some path exceeds the system clock interval Detection of a path-delay fault requires a twopattern test
0 0 1 z 1 1 0

Gate-Delay-Fault

slow

* Disadvantage: Delay faults resulting from the sum of several small incremental delay defects may not be detected.

Transition Delay Fault

Two kinds of transition faults: slow-to-rise and slow-to-fall. Slow-to-rise (fall) transition fault temporarily behaves like a stuck-at-0 (1) fault. Testing of such faults requires two-pattern tests, each consisting of an initialization and a test vector.
t1 a b k 1 1 1 t2 0 1 1 a b k t3 1 1 1 t4 1 0 1 t5 1 1 1 t6 1 1 0 t7 1 1 1

Transistor (Switch) Faults

MOS transistor is considered an ideal switch and two types of faults are modeled:
Stuck-open -- a single transistor is permanently stuck in the open state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage.

Detection of a stuck-open fault requires two vectors Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ)

Stuck-open fault
A

permanent disconnection between source and drain of CMOS transistor is modeled as stuck-open fault.

In this faulty condition, a combinational circuit may behave as a sequential machine.

Vdd

Z
x1

Test
x2

Initialization vector (x1x2 : 11) Test vector (x1x2 : 10)

Stuck-open Fault in CMOS NAND gate

Design for Testability

Design the circuit in such a manner such that testing becomes fast, with high fault coverage and economical

Built In Self Testing (BIST)

It is a design technique in which parts of a circuit are used to test the circuit itself

X1 Xn

Test Pattern Generator

Circuit Under Test

Signature Analyzer

General Structure of a BIST technique

Built In Self Testing (BIST)

Test pattern generator (TPG) -generates and applies a sequence of test vectors to the circuit under test (CUT). Exhaustive pattern 2n pseudo exhaustive pattern: 2W where w is a set of n. Random patterns: generates random test patterns. Signature analyzer: The output responses of CUT are collected and compressed by signature analyzer (SA).