5.

2 CMOS logic gate design

-To achieve correct operation of integrated logic gates, we used to satisfy 1. functional specification 2. temporal(timing)constraint. (1).in CMOS, incorrect functions are caused by 1. incorrect or insufficient power supplies, or power supplies, or power supply noise. 2. noise on gate input (so we need noise margin) 3. faulty transistors 4. faulty connections to transistors 5. incorrect ratio in ratioed logic 6. charge sharing or incorrect clocking dynamic gates -In general, CMOS is tolerable to noise ->safeness good choice for modern system - level Ic designs (2). A fair portion of the design cycle may be spent in optimizing the speed of the design. tf(tr, td) k C Load eff VDD Where k is a constant

(a).

eff no. of transisto rs in parallel or serial

e.g. in 3-input nand gate = n , = effn p 3 effp - C load : (1). Size of transistors in the gate (self-loading) (2). Size and number of transistors to which the gate is connected. (3). The routing capacitance own the gate and other the gates it drives also, speed of gate will be affected by tr/tf of i/p -.speed->find the critical paths we can use timing analyze to find the critical paths (1).architecture level (pow instead of real multiplier)

(2). RTL/logic gates(carry look-ahead) (3). Ckt level (4). Layout level =>Most leveraged way is achieved by completing a (1).good architecture. (2). RTL/logic level (check pipelining, fan-in, fan-out etc).

5.2.1 fan-in & fan-out

(a).fan-in: number of inputs e.g.:4-input nand has a fan-in of 4 ,2-input nand gate has a fan-in of 2.(known) (b).fan-out: total number of gate inputs that are driven by a gate output. Default gate size=minimum sized inverter as unity. =>Fan-in & Fan-out will be affected by stage ratio and transistors in parallel or serial tr(rise time)for an m-input nand gate:
tr = Rp (m n Cd + C r + K C g ) n
. }

a b c

(1).Rp: effective resistance of a p-device in a unit inverter. (2).n: width multiplier of PMOS (3).k:fan-out (4).m:fan-in (5).Cg:gate capacitance of an unit . inverter. (6).Cd:drain capacitance (7).Cr:Routing capacitance.

Tr =

Rp n

( m n C r Cg + q(k) Cg + k Cg )
{ { {

Drain cap

Routing cap

fan-out

where

R: Cd/Cg: ratio of the intrinsic drain capacitance of an inverter to the gate Capacitance: q(k):Represent routing cap in terms of Cg

5.2.2
example: (spice simulation)
Wn = 6 , Ln = 1 W p = 12.3, L p = 1

Tinput-rise/fall =0.1ns -.Cl=0->1PF =>NAND is a better choice than NOR.

Example of an 8-input NAND gate construction Approach1:An 8-input NAND + an Inverter. Approach2:Two 4-input NAND +2-input NOR Approach3 : see figure

Trade off bwn Area & speed (power?)

Transistor sizing: stage ratio to drive large Cl (such as clock & global reset) Guideline: start with minimum sized devices then optimize

paths from a critical-path-timing analysis. Optimizing paths can be done at different levels - use nand structures where possible - place (big)inverters at high fan-out nodes if possible - Avoid the use of NOR structures in high-speed circuits(fan-in>4) fan-out is large) - use a fan-out below 5-10 - use minimum-sized gate on high fan-out nodes to minimize Cl presented to the driving gate. - Keep rising and falling edges sharp - When designing with power or area as a constraint, remember that large fan-in Complementary gates will always work given enough time.

5.4 CMOS Logic structures

5.4.1 CMOS complementary logic Two functiondeterming blocks nblock & p-block an transistors for an n-input logic gate.

5.4.3 Pseudo-NMOS logic

( ) Z = A ( B + C ) + (D E )
a

d e b c

(+1)

5.4.4 dynamic CMOS logic

x inputs n-logic block clk=0 clk clk precharge Z=

clk=1 evlauate

{ {

0,n-block short 1,n-block open clk=0,z=1(Cl is charged to vdd) clk=1,Z is conditionally evaluated clk is a single phase clock pull-up time is improved. pull-down time is increased due to the ground switch.

problems: (a). inputs can only change during the precharge phase and must be stable during the precharge phase -> charge sharing may corrupt the o/p mode voltage. (b).simple single-phase dynamic CMOS gates cannot be cascaded(some delay between N1&N2)

Evaluate precharge

Old value = n2-logic is short New value = n2-logic is open

5.4.5 clocked CMOS logic C 2 MOS

5.4.6 pass-transistor logic

Vi Vj
F = P1 (V1 ) + P2 (V 2 ) + + Pn (V n )
Pi = control _ signals V i = pass _ signals V i {0 ,1 , X i , X i , Z }

F = i PiVi

example1: use pass-transistor logic to design a 2-input xnor gate

(a).Truth table

(b).Pass-network Karnaugh map

(c).Logic function

use A:control signal B:passed signal

F = A ( B) + A ( B) (d) implementation
(a)Complementary (b)NMOS (b) Cross-coupled

example2:use pass-transistor to construct boolean function

(a).Truth Table

(b)Implementation:

the apparent advantages of pass-transistor networks in cmos should be studied carefully.(e.g: how to achieve good logic levels) -5.4.7 CMOS domino logic (1).during preharge(clk=0),PZ=1 ,and inverter o/p=0 (2)transistors in subsequent logic blocks will be turned off during he precharge phase

(3).each gate in sequence can make at most one transition(1 to 0)=>can be used in cascaded logic gates

limitations: (1).each gate must be buffered (an advantage ,too) (2)only non-inverting structures are possible (3)common in dynamic CMOS-charge sharing charging sharing in dynamic CMOS

C 2 C 7 = low A0 = low A15 = high when clk = 1 Q in C1 is dumped into C 2 C7 Q in C1

Vn 1 =

C1 V DD ( C i ) + C1
i= 2 7

IF C1 = 3 C 2 & C 2 = C 3 = C 4 = C 5 = C 6 = C 7 then Vn1 = 3C 2 V = 0 .33V DD = 1 .65V turn onthe inverter 6C 2 + 3C 2 DD

sol: (a) place clocked NMOS at the bottom (b) provide immediate nodes with (c) their own precharging transistors

5.4.8 NP domino logic(Zipper CMOS)

.will turn off next stages

during pre-charging .Advantage of D. CMOS (1). Smaller area (2). C , speed (3)glitch free if design carefully

5.5 clocking strategies

(a) FSM (b) Pipelined system

5.5.2

.setup time: the time before the clock edge that the D input has to be stable .hold time: the time after the clock edge that the Dinput has to main stable .clock-to-Q delay(Tq):the delay from the positive clock input to the new value of the Q output. latches (a).negative levelsensitive latch (b)positive level-sensitive latch (c)positive edge-triggered register(master-slave) (d).operation of the master-slave register (e)CMOS circuit implementation.

Keep Q Keep D value

RS latch R(reset)=active Q->0 S(set)=active Q->1 Two implementations: Nand gate Nor gate

Introduction to VLSI

Analog Ic design (Prof Wang) Vlsi system Design() 1.During summer Have VLSI cad tools 2.Implement a Small IC Computer organization

Testing(Prof Su) Digital signal Processing (DSP) (Prof Chang) 1.filter 2.FFT 3.Finite-word length effect

Digital IC Design(Pro f *.Jou)

CPU Design 1.Control unit 2.ALU Design

(1).adder design (2).multiplier design (3)division unit.

Digital communication (by qT)

Communication ic design(by ql )

Latches
T-Register

D Q
clk

( )

system timing(in pipelined system) (a) Tc Tg + Td + Ts in a edgetriggered system (b) Level-sensitive system (1)Tda < Tc1 Tga Tsb ( 2)Tdb < Tco Tqb Tsc Tc1 = clk = 1 Tc 0 = clk = 0

(c).is frequently used

 Asynchronously preset/reset registers (fig. 5.57)

Dynamic single clock latches (fig. 5.58)

5.5.8 Single-phase logic structures (1) Improve speed (2) Reduce area (3) Reduce dynamic power consumption (Example : N-P Dynamic CMOS Logic) Pipelined Structure: #CLK sections are precharged. #(-CLK) sections are evaluated when CLK=0 CLK=1

Basic rules : (1)During precharge : logic blocks must be switched off (Avoid internal (2)During evaluation : the internal inputs can make only one transition races)

5.510 Two-phase clocking 1. Two forms of clock skew : (1) clock overlap (2) slow rise/fall time 2. Two-phase dynamic register