I2C-bus Elements SASESASE March 2010

Alix Maldonado -Technical Marketing Manager Product Line System Management Business Line Interface Products

Agenda
I2C-bus Protocol Electrical Characteristics Measurements with an Oscilloscope Resources Questions

I2C - Protocol
IIC - Inter-Integrated Circuit g

Logic

I2C-bus
VCC

This means: Decreased number of wires (reduced PCB area) Reduced number of chip p p pins Remove glue logic Clip many devices on to the bus Modular design: Time-to-Market

Invented by NXP! (Philips Semiconductors) I2C-bus developed in the late 1970s for Philips consumer products (e.g. TVs) Worldwide industry standard and used by all major IC manufacturers
3

I2C - Protocol
Hardware architecture
VDD
Pull up resistors SDA SCL

Clock out

Data out

Clock out

Data out

Clock in Device 1

Data in

Clock in Device 2

Data in

2 wire bus: SDA: Serial Data Line SCL: Serial Clock Line Open-drain or open-collector output stages: wired-AND function

I2C - Protocol
Hardware architecture (2)
Master2 Slave2

VDD
SDA SCL

Master1

Slave1

Multiple master Multiple slave Bi-directional Master-transmitter Master-receiver Slave-transmitter Slave-receiver Data collision is taken care off
5

I2C - Protocol
Addressing / device selection
Each device is addressed individually by software New devices or functions can be easily clipped" on to an existing bus! 112 different addresses max with the 7-bit format (others reserved); additional 1024 with ( ) 10-bit format Address allocation coordinated by the I2C-bus committee Programmable pins means that several of the same devices can share the same bus Unique address per device: f fully fixed or with a programmable part through hardware f pin's) 10-bit format use a 2 byte message: 1111 0A9A8R/W + A7A6A5A4A3A2A1A0
VDD
SDA SCL
Master1 Slave1 Address register A6 A5 A4 A3 A2 A1 A0

Fixed 1 0 0 Hardware Programmable

VDD

I2C - Protocol
Communication
Communication must start with: START condition Start bit is always followed by slave address Slave address is followed by a READ or NOT WRITE bit Sl dd i f ll db NOT-WRITE

Master Slave Master or Slave

The receiving device (either master or slave) must send an ACKNOWLEDGE bit Communication must start with: STOP condition
START SLAVE ADDRESS[7] R/W ACK DATA[8] ACK STOP

Example: Transmit (0 = Write)

START SLAVE ADDRESS[7] 0 ACK DATA[8] ACK DATA[8] ACK STOP

Receive (1 = Read)
START SLAVE ADDRESS[7] 1 ACK DATA[8] ACK DATA[8] ACK STOP

I2C - Protocol
START & STOP conditions
Start condition - a HIGH to LOW transition on the SDA line while SCL is HIGH Stop condition - a LOW to HIGH transition on the SDA line while SCL is HIGH

START Timing Diagram

START condition is a high to low transition on the SDA line while SCL is high

START

Slave Address

R/W

ACK

DATA

ACK

DATA

RENACK START/ STOP

STOP Timing Diagram

STOP condition is a low to high transition on the SDA line while SCL is high

START

Slave Address

R/W

ACK

DATA

ACK

DATA

RENACK START/ STOP

10

RE-START Timing Diagram

RESTART condition is a high to low transition on the SDA line while SCL i diti i hi h t l t iti th li hil is high, exactly the same as the START

START

Slave Address

R/W

ACK

DATA

ACK

DATA

RENACK START/ STOP

11

I2C - Protocol
Bit transfer
During data transfer, SDA must be stable when SCL is High

12

I2C - Protocol
Data transfer
Each byte has to be followed by an acknowledge bit Number of data bytes transmitted per transfer is unrestricted If a slave cant receive or transmit another complete byte of data, it can hold the clock line SCL LOW (clock stretching) to force the master into a wait state

13

I2C - Protocol
Acknowledge / NOT-Acknowledge

I2C specification: Data transfer with acknowledge is obligatory. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the d i th HIGH period of thi clock pulse. i d f this l k l Scenarios with a NOT-acknowledge (NACK) (SDA staying HIGH): 1. A receiver with the address is not present in the I2C bus. 2. 2 The receiver is performing real-time tasks and it cannot process the received I2C real time information. 3. The receiver is the master and wants to take control of SDA line again in order to generate a STOP command. The slave transmitter MUST then release the SDA line when it sees the NACK so the master can send the STOP command command.
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I2C - Protocol
Arbitration procedure p
VDD
SDA

Two or more masters may generate a START condition at the same time Arbitration is done on SDA while SCL is HIGH Slaves are not i Sl involved l d

DATA1 SDA Master 1

DATA2 SDA Master 2

Summary: The master that first sends a 1 while the other sends a 0 loses control (arbitration)

15

I2C - Protocol
Clock synchronization during the arbitration procedure y g p
VDD
SCL

Internal counters of masters count the LOW and HIGH times (TL1, TH1) and (TL2, TH2)
CLK2 SCL Master 2

CLK1 SCL Master 1

TL1

TH1

Wired-AND SCL connection: TL= longest TL= max (TL1, TL2 ,TLn) TH= shortest TH= min (TH1, TH2,THn) T

TL2

TH2

TL

TH

16

I2C - Protocol
Modes

Standard Mode Bitrate (kBit/s) Address (bits) Capacitive Bus Load (pF) Sink current (mA) 0 100 7 (10) 400 3

Fast Mode 0 400 7 (10) 400 3

Fast Mode Plus (FM+) 0 1000 7 (10) 550 20

High Speed Mode 0 1700 7 (10) 400 3 0 3400 7 (10) 100 3

Fast mode Plus (FM+):

Increased bandwidth Increased transmission distance (at reduced bandwidth: >> 550 pF bus load)

17

I2C - Protocol
Modes: Electrical specification
Standard Mode Bitrate (kBit/s) Address (bits) Capacitive Bus Load (pF) Sink current (mA) Trise: Rise time (ns) 0 100 7 (10) 400 3 1000 Fast Mode 0 400 7 (10) 400 3 300 Fast Mode Plus (FM+) 0 1000 7 (10) 4000 20 120 High Speed Mode 0 1700 7 (10) 400 3 160 0 3400 7 (10) 100 3 80

trise Vcc VIH Vbus (V) VIL VOL gnd t1 t2 0.4 V @ 3 mA sink current t (s) 0.3 0 3 * VDD

0.7 * VDD

0.4 0 4 V @ 20 mA sink current (FM+)

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I2C - Protocol
Summary y
START STOP HIGH to LOW transition on SDA while SCL is HIGH LOW to HIGH transition on SDA while SCL is HIGH 8-bit word, MSB first (Address, Control, Data): - Must be stable when SCL is HIGH - Can change only when SCL is LOW - Number of bytes transmitted is unrestricted Done on each 9th clock pulse d i th HIGH period h l k l during the i d -D - The transmitter releases the bus - SDA goes HIGH - The receiver pulls DOWN the bus line - SDA goes LOW - Generated by the Master(s) - Maximum speed: ( p (100, 400, 1000, 3400 kHz) but NO min ) - A receiver can hold SCL low when performing another function (transmitter in a Wait state) - A master can slow down the clock for slow devices - Master can start a transfer only if the bus is free - Several masters can start a transfer at the same time - A bit ti is d Arbitration i done on SDA li line - Master that lost the arbitration must stop sending data

DATA

ACKNOWLEDGE

CLOCK

ARBITRATION

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START and STOP Conditions

Question: Q estion What is wrong with this fig re? rong ith figure?

20

Data Transfer

Data

Acknowledge

During data transfer SDA must be stable when SCL is High transfer, Each byte has to be followed by an acknowledge bit Number of bytes transmitted per transfer is unrestricted If a slave cant receive or transmit another complete byte of data, it can hold the clock line SCL LOW to force the master into a wait state
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I2C-bus Slave Address (1)

Two formats of I2C slave address: 7-bit or 10-bit address 7-bit Slave address is most popular, allows up 111(27 = 128 devices reserved ) 128 17

10-bit slave address may accommodate up to 210 = 1024 devices on the same bus Devices that supports either 7 bit or 10 bit address may co exist on the same 7-bit 10-bit address, co-exist bus
Reserved Addresses

START

Slave Address

R/W

ACK

DATA

ACK

DATA

RENACK START/ STOP

ACK/

22

I2C-bus Slave Address (2)

controller t ll SCL SDA A0 A1 A2 I/O A/D D/A LCD RTC controller t ll II

10100 1 1 1 0 1 0 A2A1A0R/W
Fixed Hardware Selectable

EEPROM

Each device is addressed individually by software Unique address per device: fully fi d or with a programmable part dd d i f ll fixed ith bl t U i through hardware pin(s) Programmable pins mean that several of the same devices can share the same bus Address allocation coordinated by the I2C-bus committee

New devices or functions can be easily clipped on to an existing bus!

112 different addresses max with the 7-bit format (others reserved) 10-bit format use a 2 byte message: 1111 0A9A8R/W + A7A6A5A4A3A2A1A0 10 bit
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I2C Slave Address 7bit Format

Consist of fixed address and hardware selectable address (optional), a total of 7-bit R/W bit is sometimes included as part of the address, and is called read or write address) p , )

S X X X X A2A1A0 R/W ACK

Fixed Hardware Selectable pins Only the addressed slave device acknowledges 7-bit address

R/W bit is included result in: odd address is always the read address, even address is always the write address

1100000W
START Slave Address R/W ACK DATA ACK

DATA

RENACK START/ STOP

ACK/

24

I2C Slave Address 10bit Format

Consist of fixed command, 11110 and 10-bit address (fixed or hardware selectable) A write operation takes up two bytes

1 1 1 1 0 A9A8 0 ACKA7A6A5A4A3A2A1A0ACK C
Command Write Any 10-bit address slave devices may acknowledge Only the addressed slave device acknowledges

A read operation requires a two byte for write followed by a 1 byte read write,

1 1 1 1 0 A9A8 0 ACKA7A6A5A4A3A2A1A0ACK Sr 1 1 1 1 0 A9A8 1 ACK

Write operation p Any 10-bit address slave devices may acknowledge Command

Only the addressed slave device acknowledges

25

1st Clock Timing Diagram

First clock cycle is clock cycle after the START bit START

First Clock
26

SCL, Serial Clock Timing Diagram

Falling edge of SCL signals the requirement to provide data on SDA Rising edge of SCL signals the need to hold that data bit g g g Clock period (T) = tCYCLE = 1/fSCL = tLOW + tHIGH + tf + tr

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Key numbers to keep in mind

Standard Mode Bit Rate (kb/s) Max Load (pF) Rise time (ns) Noise filter (ns) 0 to 100 400 1000 Fast Mode 0 to 400 400 300 50 Fast F t Mode Plus High Hi h Speed Mode 0 to 3400 100 80 10

0 to 1000 0 to 1700 550 120 10 400 160 10

Rise Time

VDD VIH

0.7xVDD

VIL VOL GND

0.4 V @ 3 mA Sink Current 0.4 V @ 30 mA Sink Current (Fm+)

0.3xVDD

28

SDA, Serial Data Timing Diagram

Normal data transition occurs when SCL is low Data is evaluated when SCL is high g
SDA data changing state SDA evaluated

29

Acknowledge (ACK)
Acknowledge bit occurs on the 9th SCL clock pulse The transmitter and receiver behave as follows:
1. Transmitter releases SDA line after the 8th clock pulse 2. Receiver acknowledges by pulling SDA low on the 9th clock pulse 3. Transfer is aborted if SDA does not go low ( ACK) g (no )
HIGH

No ACK

SDA SCL
8th SCL

ACK
LOW

9th SCL

30

Acknowledge Example

31

Not Acknowledge (NACK)

Three Scenarios where there is no acknowledge taking place 1. The receiver being addressed is not p g present on the I2C bus 2. The receiver is busy (cannot process the receiving information) 3. The master receiver wants to take control of SDA line
HIGH

NACK

SDA SCL
8th SCL

ACK
LOW

9th SCL

32

Not Acknowledge Example

33

Clock Stretch
A clock stretch is defined as the SCL line being pulled low stretched longer than its intended clock low period Why a device stretches the clock?
A master performs clock stretch when it needs to slow down the clock in order to accommodate a slower slave device A slave performs clock stretch when it needs to perform other function

Data is DONT CARE when the clock is low

SDA SCL

DONT CARE

Clock stretch

34

Multi-master Synchronization/Arbitration S h i ti /A bit ti

35

Clock Synchronization & Bus Arbitration

Multi-master environment requires clock synchronization and data arbitration Masters synchronize on clock line
Result in new clock frequency = longest low + shortest high

Masters arbitrate on data line

Result in the losing master stop sending data Losing master can continue to send SCL until the end the byte Data is not corrupted
VCC Rpu

Master#2

Master#1

Slave Address#2

Slave Address#1

36

Clock Synchronization Timing Diagram

LOW period determined by the longest clock low period HIGH period determined by shortest clock high period
Ma s ter 1 CL K 1 S CL Vdd Ma s ter 2 CL K 2

1 2

4 3

37

Arbitration Timing Diagram

Two or more masters may generate a START condition at the same time Arbitration is done on SDA while SCL is high - Slaves are not involved
Master 1 loses arbitration DATA1 SDA

Start command

38

Bus Recovery Method

Problem: Typical case is when a master fails during reading the slave device The SDA line is stuck low because the slave is stuck in the transmitter mode Solution Three methods to recover the bus:
1) Use a hardware reset pin to reset the slave device ( ) p (assuming the device g has a reset pin) 2) Use a hardware self-timeout function such as SMBus timeout 3) Use an I2C-bus recovery sequence to leave the Slave-Transmitter mode ) y q

39

I2C-bus Recovery Sequence

An I2C-bus recovery sequence is done as follows:
1) Send 9 clock pulses on SCL line while the master keeps the SDA line high until the Slave Transmitter releases it including the time for the ACK Slave-Transmitter operation. Keeping SDA high during the ACK means that the MasterReceiver does not acknowledge the previous received byte 2) The Slave-Transmitter then goes in an idle state (mandatory when no acknowledge is received) 3) The master then sends a STOP command to initialize the bus
Slave releases SDA line Slave held the line low Slave becomes idle

40

Multi Master Mode - Clock Synchronization

Master 1
CLK 2 TL2, TH2

Vdd

Master 2
CLK 1 TL1, TH1

T1 TL1 TH1

T2
TL2 TH2

SCL TL, TH
Count Wait State TL1 TL2 still counting
Counting TL1 done

Count TH1

CLK1
0 Count TL2

Internal Counters count the Low and High times (TL1, TH1) and (TL2, TH2)

CLK2
0

Count TH2

Reset Counter High TH2 Start Counting TL2 3

3 2 4 4 1
Counting TH1 done Start Counting TL1 SCL goes Low TH = TH1

SCL
0

Counting TL2 done Start Counting TH2 SCL goes High Start Counting TH1

1
Counting TH1 done Start Counting TL1 SCL goes Low TL = TL2

TL = longest TL = max (TL1, TL2 ,TLn ) TH = shortest TH = min (TH1, TH2,THn ) T

41

Multi Master Mode - Arbitration

Two or more masters may generate a START condition at the same time Arbitration is done on SDA while SCL is HIGH - Slaves are not involved
Master 2 loses arbitration because DATA2 SDA

DATA1
0

1 1

DATA2
0 0 0

SDA

SCL
0

START

SUMMARY: the master that sends a 1 while the other sends a 0 loses the arbitration
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I2C-bus El I2C b Electrical Characteristics i l Ch i i

Subject / Department / Author 43

SDA/SCL Driver Architecture

SDA and SCL are open drain/collector
Required pull-up resistors to pull the line to logic 1

Clock stretch is possible when a device is busy

Requires pull-up resistors 2k to 10 k k

SCL

Open drain structure and bidirectional for SDA and/or SCL

10 pF Max
44

Key Electrical Parameters

Standard Mode Bit Rate (kb/s) Max Load (pF) Rise time (ns) Noise filter (ns) 0 t 100 to 40 0 1000 Fast Mode 0 t 400 to 400 300 50 Fast Mode Plus High Speed Mode 0 t 3400 to 100 80 10

0 t 1000 0 t 1700 to to 560 120 10 400 160 10

Rise Time

VDD VIH

70%VDD

VIL VOL GND

0.4 V @ 3 mA Sink Current

30%VDD

45

Calculating Pull-up Resistors

1) RMIN < RPU < RMAX 2) RMIN = (VDDMAX - VOLMAX) / IOLMAX
VDDMAX 3.6 V 5.5 V VOLMAX 0.4 V 0.4 V RMIN IOLMAX = 3mA 1.1 k 1.7 k IOLMAX = 6mA* 533 850 IOLMAX = 30mA** 106 170 Glossary
*With a buffer; **Fast mode Plus With Fast-mode
Master#1
Slave Address#2 Slave Address#1 VCC Rpu

RPU
Master#2

RPU: RMIN: RMAX: CMAX 400 pF 400 pF 560 pF RMAX 2.96 k 885 252

Pull-up resistor p Minimum pull-up resistor Maximum pull-up resistor

3) RMAX * CMAX = 1.18*tr

MODE Standard Fast Mode Fast Mode Plus Frequency 100 kHz 400 kHz 1000 kHz tr 1000 ns 300 ns 120 ns

VDDMAX: Maximum supply rail VOLMAX: Maximum output voltage low IOLMAX: Maximum sink current CMAX: tr: Maximum load capacitance Rise time

46

How to calculate I2C Pull-up Resistors?

Minimum value
There is a minimum resistor value determined by the IC spec limit of 3 mA. R = (Vddmax Volmax)/ 0.003A Example: using a 50 5 V bus: R = (5 5V 0 4V)/ 0.003A = 1.7 k 50.5 (5.5V 0.4V)/ 0 003A 1 7

Maximum value
Determined by the IC-bus rise time requirements: I C bus V(t1) = 0.3*Vdd = Vdd (11/et1/RC); then t1 = 0.3566749*RC V(t2) = 0.7*Vdd = Vdd (11/et2/RC); then t2 = 1.2039729*RC t = t2t1 = 0.8472979*RC t2 t1 0 8472979*RC For standard-mode IC-bus: t = rise time = 1000ns (1 s) so RC = 1180.2 ns Example: at a bus load of 400 pF: Rmax = 2.95 k For fast-mode: pF: IC-bus rise time = 300 ns @ 400 p Rmax = 885
47

How Do You Derive Rise Time for I2C-bus

IC-bus rise time is determined as in the following :
1) 2) 3)

V(t1) = 0.3*VDD = VDD (11/et1/RC) V(t2) = 0.7*VDD = VDD (11/et2/RC) Subtract EQ1 from EQ2 R*C = 1 18*t rise time 1.18*t
Rise Time

t1 = 0.3566749*RC ( EQ1) t2 = 1.2039729*RC ( EQ2)

t rise time = t2t1 = 0.8472979*RC or

V(t2) 70%VDD

VDD V(t1) VOL

t1

0.4 V @ 3 mA Sink Current

t2

30%VDD
Time

48

Effects of Pull-up Resistors

Minimum pull-up resistor limits the maximum current sink that affects the voltage output low (VOL).
Increasing pull-up resistor above RMIN leads to decreasing VOL and higher noise margin Decreasing pull up resistor below RMIN leads to increasing VOL and lower pull-up noise margin

Maximum pull-up resistor affects the rise time and speed p p p

Increasing pull-up resistor above RMAX leads to slower/possible rise time violation or lower speed pull up Decreasing pull-up resistor below RMAX leads to faster rise time and speed

49

Measurements using an Oscilloscope

50

Using Cursors to make measurements

Allows one to make quick measurements i k t for V and t Handy in making rough rise time measurements for I2C-bus

51

Effects of Pull-up Resistors

Rise time for SDA and SCL lines using 9K pull up resistors

52

Effects of Pull-up Resistors

Rise time for SDA and SCL lines using 2.2K pull up resistors

53

Effects of Pull-up Resistors

Side by side comparison of the difference in rise time using two different pull-up resistor values

54

Effects of Pull-up Resistors

Rise time for SDA and SCL lines using 100K pull up resistors Slow rise time, no stable logic high state.

55

Probing your I2C-bus

56

Passive Probe Basics

Passive probes make an attenuator circuit with the probe impedance and scope impedance

Probe 9 M Attenuation ratio 1 M /(9 M +1M) ( ) = 1/10

Scope 1 M

57

Importance of Oscilloscope Coupling

Signal is attenuated too much if the coupling is set incorrectly

Attenuation ratio 50 /(9M +50 ) 50 = 1/180,001

Probe P b 9M

Scope 50

Most modern passive probes have a probe sense pin that mates with a probe sense ring on the oscilloscope this automatically sets the correct coupling and attenuation factor

58

Scope/Probe Impedance Matching

Passive probes have an adjustment that allows the user to tweak the impedance of the passive probe to match the impedance of the scope it is connected to, this low frequency adjustment results in improved pulse shapes on the oscilloscope display

59

Passive Probe Adjustment

All oscilloscopes have a Cal Out which provides a clean square wave for passive probe adjustment and compensation Adjusting the capacitor in the probe allows the probe to be tuned for that scope and resulting in the good pulse shape shown below

60

Importance of ground lead length while probing

Not having proper ground connection, shows distorted signal

Pulse measured with 10 passive Probe

A: Without Ground Lead B: 50 cm Ground Lead C 0 C: 10 cm G Ground Lead D: BNC Direct Cable Connection (true signal shape)

61

Exercise 1
Verify understanding of the IC bus p y g protocol

Subject / Department / Author 62

I2C-bus Building Blocks

AD/DA Converter I/O `Expander` LED Blinker/ Dimmer Color Mixing LED Driver Bus Buffer, Voltage Translator, Extender
IC in hardware or software emulation 8

DIP Switch

Other Slave

VCC4

VCC5

VCC0 VCC2
Multiplexer& Switch Master Selector

C C
Temperature Sensor

Functions with I2C I2C Bus Architecture Devices Custom I2C hardware or software emulated Other hardware

VCC1

Bus Controller C

I2C
EEPROM LCD Driver

Real Time Clock / Calendar

VCC3
Bridge

SPI UART

63

Which tools to help you win ? y

I2C Demoboards
Demo and Evaluation Boards

65

Evaluation/Demo Board List

OM# OM6270 OM6271 OM6272 OM6273 OM6274 OM6275 OM6276 OM6277 OM6278 OM6279 OM6281 OM6276 OM6285 OM6290 OM10088 Description SPI/I2C to UART Bridge Demoboard (SC16IS750) SPI to I2C Master Bridge Demoboard (SC18IS600) UART to I2C Master Bridge Demoboard (SC18IM700) SPI/I2C to Dual UART/IRDA/GPIO Demoboard (SC16IS752) I2C to SPI Master Bridge Demoboard (SC18IS602) I2C 2005-1 Demo Board (15 I2C devices w/USB control & GUI) PCA9633 Demo Board (Four Color PWM LED Control with Microcontroller) PCA9564 Eval Board (I2C Master) I2C 2002-1A Eval Board (11 I2C devices w/printer port control & GUI) LED Dimmer Demo Board PCA9698 Demo Board (Advanced 40-bit GPIO with PCA9530 LED blinker) PCA9633 Demo Board (Four Color PWM LED Control) I2C 2002-1A Eval Board (without/printer p control & GUI) ( p port ) I2C bus LCD driver evaluation board PCF8562 LCD Segment Display

More information: www ics nxp com/support/tools/interface www.ics.nxp.com/support/tools/interface

NXP Bridge IC Demo Board Kits

I2C/SPI slave to UART UART to I2C master SC16IS7xx SC18IM700 SPI to I2C master t t SC18IS600 I2C t SPI master to t SC18IS602

Kits i l d Kit include

Sample code: RS232, RS485, and IrDA User Manual

Kits i l d Kit include

Sample code: RS232 and NXP I2C devices User Manual

Kits include
Sample code: SPI and NXP I2C devices User Manual

Kits include
Sample code: I2C and NXP SPI devices User Manual

y Key Benefit
Easy interface to I2C/SPI host and IrDA, RS232/RS485, and GPIO devices. Selectable I2C or SPIbus interface

Key Benefit y
Easy interface to UART host and various I2C and GPIO devices. On-board I2C EEPROM and I2C LED Dimmer

Key Benefit y
Easy interface to SPI host and various I2C and GPIO devices. On-board I2C EEPROM and I2C LED Dimmer

Key Benefit y
Easy interface to I2C host and SPI and GPIO devices. Up to 4 SPI chip selects

Up to 5Mbps!
OM6270 SC16IS750 OM6273 SC16IS752

OM6271

OM6272

OM6274

Experience the variety of IC peripherals with the latest IC Training Board g

Fifteen different IC devices on one board allows easy experimentation and training.
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Train on many IC peripherals using parallel printer port to PC

Eleven different IC devices on one board allows easy experimentation and training (LM75A, P82B96/PCA9600, PCA9501, PCA9515, PCA9543, PCA9550, PCA9551, PCA9554, PCA9555, PCA9561, PCF8582C-2) Add Extra I/O Ports, Temperature Sensors, LED Drivers, I C Bus Switching IC IC Bus adapter uses parallel printer port for connection to full version (all devices and addresses operational) of Graphics Interface for Windows PC/Laptop www.ics.nxp.com/support/boards/i2c20021/ Target Board plus parallel printer port control (100 kHz) & GUI #OM6278 Target Board only #OM6285

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LCD Glass Glass

COG is an option i ti

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Access I2C Discussion Forum from > www.nxp.com/i2c CONTACT link on every Product Information Page www.nxp.com/support www nxp com/support Send e-mail directly to pp @ p I2C.Support@nxp.com
75

I2C Device Data Sheets, IBIS models Application Notes and Other Information
Product family descriptions line cards cross reference data sheets

Link to app notes models user guides PLL design software datasheets

www.nxp.com/i2c or www.nxp.com/i2clogic

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Interface Products Internet Support

General: http://www.nxp.com/support I2C Control: http://www.nxp.com/i2c I2C.Support@nxp.com (E-mail Support) http://forums.nxp.com/forums http://forums nxp com/forums (Forum)

All other Interface Products http://www.ics.nxp.com/interface/ Interface.Support@nxp.com

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Questions?

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