943/U0280

Physical Design for Nanometer ICs

Yao-Wen Chang ywchang@cc.ee.ntu.edu.tw http://cc.ee.ntu.edu.tw/~ywchang Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Spring 2012

Administrative Matters
Time/Location: Tuesdays 2:20pm--5:30pm; BL-114 Instructor: Yao-Wen Chang E-mail: ywchang@cc.ee.ntu.edu.tw URL: http://cc ee ntu edu tw/~ywchang http://cc.ee.ntu.edu.tw/ ywchang Office: BL-401. (Tel) 3366-3412/3366-3556; (Fax) 2364-1972 Office Hours: Thursdays 5:306:30pm; other times by appointment Teaching Assistant: Shao-Yun Fang (yuko703@eda.ee.ntu.edu.tw) Prerequisites: data structures, algorithms & logic design Required Text: Either of the following two books:

Wang, Chang, Wang Chang and Cheng (Ed ) Electronic Design Automation: (Ed.), Synthesis, Verification, and Test, Morgan Kaufmann, 2009 Sait and Youssef, VLSI Physical Design Automation: Theory and Practice, World Scientific Publishing Co., 1999

References: Selected reading materials from recent publications

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Teaching Assistant

Shao-Yun Fang
( ( GIEE ) ) yuko703@eda.ee.ntu.edu.tw Office: BL-406 Tel: 23635251 # 6406 Office hours: 12:30-1:30 pm Mondays 3rd -year Ph.D. student

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Course Objectives

Study techniques/algorithms for physical design

(converting a circuit description into a geometric description) and their comparisons Study nanometer process/electrical effects and their impacts on the development of physical design tools Study problem-solving (-finding) techniques!!! solution S1 S2 S3 S4 S5 P1 P2 P3 P4
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P5 P6

problem
4

Course Contents
VLSI design flow/styles and technology roadmap Physical design processes

Partitioning Floorplanning Placement Routing (global, detailed, clock, and power/ground routing) Post-layout optimization

Signal/power integrity: crosstalk, IR drop Timing issues: timing modeling & optimization,
performance-driven design

Design methodology: large-scale design, interconnectcentric design flow buffer/wiring planning. flow, planning

Design for manufacturability & reliability: process

variation, antenna effect, redundant via, optical proximity correction (OPC), chemical mechanical polishing (CMP), multiple pattering, e-beam, EUV, electromigration, thermal issues, etc.
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Grading Policy

Grading:

Homework assignments + quizzes: 25% Programming assignments + lab: 25% One in class open book open note exam: 30% (June 19) in-class open-book, open-note Final project + presentation + demo: 20% (due June 26) A 1-page project proposal is due in-class on May 22 Could be research work, implementation, and/or literature survey Teamwork is permitted (1--3 persons; preferably 2 persons) Bonus for class participation p p

Homework: 20% per day penalty for late submission WWW: http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD/pd.html Academic Honesty: Avoiding cheating at all cost
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Unit 1: Introduction

Course contents:

Introduction to VLSI design flow/styles Introduction to physical design automation Semiconductor technology roadmap W&C&C: Chapter 1 S&Y: Chapter 1

Readings

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IC Design & Manufacturing Process

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From Wafer to Chip

8-inch vs. 1-inch ignot

Apple A4 die with dual ARM cores

8-inch wafer

Wafer dicing

Wire bonding

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chips
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IC Design Considerations

Several conflicting considerations:

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Complexity: large number of devices/transistors Power: low-power consumption Performance: hi h P f high-speed requirements d i t Cost: die area, packaging, testing, etc. Time-to-market: about a 15% gain for early birds Others: reliability, manufacturability, testability, etc.
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Moores Law: Driving Technology Advances

Logic capacity doubles per IC at a regular interval (say, 18 months).

G. Moore: Logic capacity doubles per IC every two years (1975). D. House: Computer performance doubles every 18 months (1975)
4Gb
Itanium 2

Intel uP

4004

8086

80386

PentiumPro

Pentium 4

Itanium 2

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Design Productivity Crisis

10,000M 1,000M 100M 10M 1M 0.1M 0.01M 1980 1985 1990 1995 100,000K 10,000K

Human factors may limit design more than technology. y g gy Keys to solve the productivity crisis: CAD (tool &
methodology), hierarchical design, abstraction, IP reuse, platform-based design, etc.
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Logic transis stors per chip

Productivity in transistors y per sta aff-month

58%/yr compound p y growth rate complexity g

Complexity limiter

1,000K 100K 10K

21%/yr compound 1K productivity growth rate

2000 2005 2010

0.1K

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Old (1997) Technology Roadmap for Semiconductors

Source: International Technology Roadmap for Semiconductors (easier to

see the past & trend with the older version; for more recent update, see http://www.itrs.net/). Deep submicron technology: node (feature size) < 0.25 m. Nanometer Technology: node < 100 nm. 28 nm technology was in production in 2011.

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Nanometer Design Challenges

Intel Core i7-2600: feature size 32 nm, P frequency

3.4 GHz, die size 81 mm2, P transistor count per chip 382M, wiring level 10+ layers, supply voltage 1.3 V, power consumption 95 W (full load)

Feature size : sub-wavelength lithography (impacts of process variation)? reliability? noise? wire coupling? Frequency , dimension : interconnect delay? electromagnetic field effects? timing closure? Chip complexity : large-scale system design et odo ogy methodology? Supply voltage : signal integrity (noise, IR drop, etc)? Wiring level : manufacturability? yield? 3D layout? Power consumption/density : power & thermal issues?
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Design Complexity Increases Dramatically!!

Mixed-size Placement

Routing & interconnect

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Power/Thermal Is Another Big Problem!!

Power density increases exponentially!

1000

Power doubles every 4 years 5-year projection: 200W total, 125 W/cm2 !
Nuclear Reactor
Pentium 4

Rocket Nozzle

Watts/cm 2

100

Hot plate
10

Pentium III Pentium II

i386 i486
1
1.5 1 0.7

Pentium Pro Pentium

P=VI: 75W @ 1.5V = 50 A!

0.18 0.13 0.1 0.07

0.5

0.35

0.25

Fred Pollack, New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies, 1999 Micro32 Conference keynote. Courtesy Avi Mendelson, Intel.
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Interconnect Dominates Circuit Performance!!

70 60 50

Worst-case interconnect delay due to crosstalk

Delay (ps)

40 30 20 10

Interconnect delay

Gate delay
650 500 350 250 180 150 100 70 (nm)

Technology Node

Source: Synopsys

In 0.18m wire-to-wire capacitance dominates (CW >>CS)

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CS

CW
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Lithography System

Immersion

R: resolution; k1: resolution constant; : wavelength NA: numerical aperture = f(lens, refraction index)
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R = k1/NA

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Sub-wavelength Lithography Causes Problems!!

Printed feature size is smaller than the wavelength of the light
shining through the mask

ArF (Argon Floride)

157nm is not feasible!

Numerical T h l i N i l Technologies

227nm @ 0.85NA 136nm

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114nm
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91nm

68nm 19

Reliability Becomes a 1st-Order Effect!!

Manufacturability and reliability with 10-layer metal?
m5
m4

+ ++ + +++

m3
m2 m1

sgd

Si substrate

sgd

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10

Traditional VLSI Design Cycles

1. 2. 3. 4. 4 5. 6. 7.
System specification Functional design Logic synthesis Circuit design Ci it d i Physical design Fabrication Packaging Other tasks involved: verification, simulation, testing, etc. Design metrics: area, speed, power dissipation, manufacturability, reliability, testability, design time, etc. Design revolution: interconnect (not gate) delay dominates circuit performance in deep submicron era.

Interconnects are determined in physical design. Shall consider interconnections in early design stages.
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Traditional VLSI Design Cycle

& verification

& verification

& simulation

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Traditional VLSI Design Flow (Cont'd)

design

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Physical Design (PD)

physical design

fabrication

PD converts a circuit description into a geometric description. The description is used to manufacture a chip. Physical design cycle:
1. Partitioning 2. Floorplanning 3. Placement 4. Routing (clock, power/ground, signal nets) 5. Post-layout optimization (buffering, sizing, etc.) Others: circuit extraction, timing verification and design rule checking
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Physical Design Flow

B*-tree based floorplanning system

A routing system
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Floorplan Examples
Pentium 4

PowerPC 604

Intel Pentium 4

A floorplan with interconnections

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Placement Examples
ISPD98 ibm01

842K movable cells 646 fixed macros 868K nets

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12,752 cells, 247 macros Amax/Amin = 8416

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Routing Example
0.18um technology, two layers, pitch = 1 um, 8109 nets.

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Design Styles

Power

Others

Structure ASIC

FPGA SPLD

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SSI/SPLD Design Style

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Full-Custom Design Style

Designers can control the shape of all mask patterns.

transistors.

Designers can specify the design up to the level of individual

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Terminology

Cell: a logic block used to build larger circuits. Pin: a wire (metal or polysilicon) to which another
external wire can be connected. N Nets: a collection of pins which must b electrically ll i f i hi h be l i ll connected. Netlist: a list of all nets in a circuit.
nets

pin

cells

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Standard-Cell Design Style

Selects pre-designed p g
cells (typically, of the same height) to implement logic

Over-the-cell routing is pervasive in modern designs

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Standard Cell Example

Courtesy of Newton/Pister, UC-Berkeley

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Gate Array Design Style

Prefabricates a transistor array Needs wiring customization to implement logic

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Structured ASIC
A structured ASIC consists of predefined metal and via layers, as
well as a few of them for customization.

The predefined layers support power distribution and local

communications among the building blocks of the device. Advantages: fewer masks (lower cost); easier physical extraction and analysis. Popular for engineering change orders (ECOs)

A structured ASIC (M5 & M6 can be customized)

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Faradays 3MPCA structured ASIC (M4--M6 can be customized)

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FPGA Design Style

Logic and
interconnects are both prefabricated.

Illustrated by a
symmetric arraybased fieldprogrammable bl gate array (FPGA)

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Array-Based FPGA Examples

Lucent Technologies 15K ORCA FPGA, 1995 0.5 um 3LM CMOS 2 45 M Transistors 2.45 1600 Flip-flops 25K bit user RAM 320 I/Os

Fujitsus Dynamically Programmable Gate Array (DPGA), 2002

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FPGA Design Process

Illustrated by a symmetric array-based FPGA No fabrication is needed

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Comparisons of Design Styles

Full custom Cell size Cell type Cell placement Interconnection variable variable variable variable Standard Cell fixed height variable in row variable Full custom Fabrication time Packing density Unit cost (large quantity) Unit cost (small quantity) Easy design & simulation Easy design change Timing simulation accuracy Chip speed
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Gate array fixed fixed fixed variable Standard Cell

Structure ASIC fixed fixed fixed variable/fixed Gate array

FPGA fixed programmable fixed programmable FPGA

Structure ASIC

--+++ +++

-++ ++

+ + +

++ -

+++ -----

-------+++

---++
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+ + + + -

+++ ++ +++ ++ --40

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Design Style Trade-offs

10
4

full custom semicustom

10 Turnaround Time (Days) 2 10

10 SSI 1 1 10

SPLD

CPLD

FPGA

optimal solution 10
2

10

10

10

10

10

10

Logic capacity (Gates)

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