Protocol-Aware ATE: Complement or Competitor for Structural Testing?

Stephen Sunter LogicVision (Canada), Inc. Ottawa, Canada

Introduction Functional testing in production has been an enticing approach for many years because it is intuitively the way a function should be tested to ensure highest quality. For complex ICs, the tester hardware complexity, poor fault coverage, and lack of diagnosability of functional testing have led to its use primarily for design validation and characterization, and, in some cases, as a top-up test applied after all other tests. This in turn has reduced the need for these testers (reportedly this may account for ATE sales decreasing to 3% from 5% of silicon investment). Structural testing has been demonstrated in the last decade to permit use of simpler, lower-cost tester hardware, while delivering higher fault coverage and test results that facilitate quicker diagnosis of manufacturing problems. This paradigm shift has been the most significant evolution of digital ATE in the last 20 years: less ATE complexity means lower cost, simpler use, and higher reliability. For mixed-signal functions, structural testing must be done at the right level of the design hierarchy. Testing individual transistors or capacitors is impractical, too timeconsuming, and often useless because high-level performance is not the sum of lower level performances. Testing at too high a level is too complex and not sufficiently diagnostic. Is Protocol-Aware ATE for Functional Testing? Protocol-aware ATE sounds like functional testing by another name. However, ATE that can directly implement JTAG instructions is clearly intended to make structural testing via JTAG test access simpler to implement. Some testers already provide support for this protocol. Slightly higher level protocols, such as I2C and MDIO, are used both for test and functional access. These lowlevel communications protocols are fairly simple, and there is not a large number of such protocols in common use. The difference between a structural test and a functional test of protocol logic is minimal in terms of fault coverage, and most design/test engineers write simple translation scripts to create WGL or STIL test patterns in these protocols. Therefore, providing this level of protocol awareness in ATE provides minimal value in terms of time-to-market. A significantly higher-level protocol is used in highspeed serial data communications standards, such as PCI Express, Serial ATA, Fibre Channel, SONET, etc.. Some of these standards also use coding (8B10B, 64B66B, CRC) and byte insertion/deletion. This type of functionality can be separated in two for testing: the mixed-signal serializer/

deserializer (SerDes) circuitry and the purely digital bit/byte re-ordering circuitry. The first can be tested using parametric structural test approaches and the latter can be tested using conventional scan-based structural tests. For high-level protocols, using ATE to emulate a memory or perform system-level testing is clearly functional testing, and the difference between a structural and functional test of the protocol logic becomes significant; more so for the functionality that is accessed via these protocols. The higher complexity of these protocols increases the time-to-market value of this capability being embedded in ATE (though it is likely that some companies already automate the creation of patterns in these protocols). However, whether this approach can improve quality is definitely debatable. For IC designs in processes at 90 nm and below, manufacturing evidence shows that performance faults are becoming more prevalent than in earlier technologies. And diagnosis is becoming more complex due to the finer dimensions, large number of levels, higher switching speeds, lower power rail voltages, and more complex packaging. Therefore, the need for structural tests in production is increasing, and protocol-aware ATE wont help improve quality. An increasing number of failures can be traced to application conditions, such as power rail quality, I/O timing marginality, and temperature gradients, across the IC, SiP, and board. More ICs will need to be diagnosed in situ because after the device is removed from the application environment everything is different. Since diagnostic tests will need to be run while the IC is in the faulty system, the need for system emulation in the ATE seems questionable. Conclusion Protocol-aware testing is functional test posing as a structural test by including low-level protocols in addition to high-level protocols. Therefore, it is a complement to structural testing. It will likely provide minimal time-tomarket acceleration for low-level protocols, and minimal test quality improvement for high-level protocols. As simplification for design validation and characterization, it is enticing, but the size of this market may not be large enough to justify ATE vendors investing effort in many complex protocols, which will make the ATE cost high. Small form-factor testers would require almost the same ATE-vendor development investment but with customers expecting lower prices, hence delivering lower profits to the vendors.

Panel 5.2 INTERNATIONAL TEST CONFERENCE 1-4244-1128-9/07/$25.00 2007 IEEE