Are Power Planes Necessary for High Speed Signaling ?

Suzanne L. Huh* and Madhavan Swaminathan+ *Intel Corporation, Folsom, CA +School of Electrical and Computer Engineering Georgia Tech, Atlanta, GA Sponsored by

OUTLINE
High Speed Signaling Challenges Interaction between Signal and Power Distribution Return Path Discontinuities Cause and Effect Role of Power and Ground Planes Power Transmission Line for Distributing Power Constant Current Pseudo-Balanced Constant Voltage Summary and Conclusions

TECHNOLOGY TREND
*
Processor with integrated memory controller Memory

Processor-memory mismatch
CPU Frequency Dram Speeds

**

The performance of processor-memory interface is dictated by: Chip-to-chip communication speed 1)memory speed Bus width 2)channel bandwidth
* http://www.apple.com/macpro/features/processor.html; ** http://www.drdobbs.com/high-performance-computing/194500234

Relative performance

SYSTEM-LEVEL ELECTRICAL CHALLENGES

Signaling in a digital system

Reliably passing data through a channel that can degrade the signal
Reducing power supply noise needs to be achieved to enhance the channel speed in a modern digital system as well as minimize Return Path Discontinuity effects

DESIGN OF POWER DELIVERY NETWORK

Most popular design approach
Achieve a low-impedance path from the power supply to the die
I avg = Pavg

VDD
Vripple I avg

ZPDN < Ztarget

V (noise voltage) < Vtarget

ZPDN() ZPDN > Ztarget V = Imax ZT > Vtarget ZT() ZPDN < Ztarget V = Imax ZT < Vtarget Freq(Hz)

Z target =

PCB power delivery network

POWER DELIVERY NETWORK

Signal current

Return current

Cavity modes

Cavity modes

Return Path Discontinuity (RPD)

Maybe new methods for PDN design are required in the future !

POWER TRANSMISSION LINE

* *

*PTL : Power Transmission Line

Transmission lines replace the power plane to convey power reduce the layer count remove the effect of cavity mode resonance Both the power and signal transmission lines are referenced to the same ground plane prevent the RPD
* A. E. Engin and M. Swaminathan, Power Transmission Lines: A New Interconnect Design to Eliminate Simultaneous Switching Noise, in Proc. ECTC, pp. 1139-1143, 2008

POWER TRANSMISSION LINE CONCEPT

High Impedance Power Distribution Closed current loop

Signal Current

Return Current

DOES THE POWER TRANSMISSION LINE CONCEPT REALLY WORK ?

Dynamic DC drop on PDN due to source termination

IR drop

data_in=0
Vdd

data_in=1
Vdd

Vdd

No current
S. Huh, M. Swaminathan, and D. Keezer, Constant Current Power Transmission Line based Power Delivery Network for Single-Ended Signaling, IEEE Transactions on Electromagnetic Compatibility, 2011

DOES MISMATCH CREATE PROBLEMS ?

Impedance mismatch in PTL

20

Line congestion issue

Using one PTL per driver will double the # of lines on PCB

PRACTICAL ISSUES ?
Varying DC Level on PDN when extended to multi-bit I/Os
IR drop

IPTL

I1 I2
Case 1 2 Low 3 Low High Low Data Pattern data1_tx High High data2_tx High Low IPTL data1_tx 1V I1 1.25V I2 0 0 Eye Height drop DC over PTL data2_tx I1RS 1V 0 I2RS 1.25V 0

LETS RETHINK THE CONCEPT CONSTANT CURRENT PTL (CCPTL) TO THE RESCUE Constant Current PTL (CCPTL)*
Dummy path

data_in=0
IR drop IR drop

data_in=1

* S. Huh, M. Swaminathan, and D. Keezer, Constant Current Power Transmission Line based Power Delivery Network for SingleEnded Signaling, IEEE Transactions on Electromagnetic Compatibility, 2011

DOES CCPTL WORK ?

Constant current through PTL

Constant IR drop over PTL

Continuously charged PTL

Constant voltage at TxPwr node

No mismatch effect

DOES CCPTL WORK ONLY IN THEORY ? A SIMPLE TEST VEHICLE TO ILLUSTRATE THE CONCEPT
Power-plane-based test vehicle
Via to ground plane Via to power plane Driver 2.6-long

Dummy path

PTL-based test vehicle

Via to ground plane Power transmission line

1.25oz Port1 1.0oz Port4

Signal Layer
Port3 Port2 0.012"

Driver

2.6-long

Ground Plane

Dummy path

Modeling in frequency domain

MODELING AND SIMULATION

Converted to Macromodel
1.5Gbps

SPICE simulation setup

1st resonant frequency = 750MHz

Power-plane-based TV

PTL-based TV

Eye height improves by 19.6% Jitter improves by 58%

MEASUREMENT SETUP
Measurement setup

1.5Gbps

Dummy path

Dummy path is implemented outside the off-the-shelf chip. AC coupling capacitor is used to suppress the DC current flow. to provide bias for the oscilloscope. The supply voltage of 3.47V was used for the PTL-based TV, while 2.5V was used for the plane-based TV.

Signal generator output

MEASUREMENT RESULTS
Eye height Power plane CCPTL Improvement 430mV 495mV 15.1% P-P jitter 39.1ps 24.9ps 36.3%

Plane-based TV

CCPTL-based TV

RMS AND PEAK-PEAK JITTER COMPARISON

PTL: Both RMS and P-P Jitters have relatively monotonic behavior. Power plane: Both RMS and P-P Jitters have non-monotonic behavior, showing similarity to the insertion loss of the signal line.

CCPTL IMPLEMENTATION USING CMOS 0.18UM PROCESS

Output buffer Pre-driver 1 clock reset PRBS Generator 1 Control Signal Generator Dummy Path

Power Plane

CCPTL
25 3.109V
Dummy Path data_in

Z=25

36u/ 0.35u 50 data_in 18u/ 0.35u

Z0=50 50

Power plane

CCPTL

MEASUREMENT COMPARISON
200 Mbps Power Plane 500 Mbps

CCPTL
Eye height improvement of 34% Eye height improvement of 55% Jitter improvement of 35% Jitter improvement of 52%

Static power consumption

PDN type Power Plane CCPTL PBPTL Eye height VDD/2 VDD/2 VDD/2 4 bit HHHH 4 4 3 0.0625 HHHL 3 4 3 0.25 HHLL 2 4 3 0.375 HLLL 1 4 3 0.25

WHAT ABOUT POWER ?

LLLL 0 4 3 0.0625 Expectation of Power 2 4 3 Power penalty 100% 50%

Probability

*Assumption: Four bits provide 16 data patterns, each of which has an equal probability. When one output buffer draws current from the power supply, power of 1 is consumed. For the PBPTL scheme, 4b/6b encoder is used to generate the balanced data with three 1s and three 0s.

The same amount of dynamic power is consumed regardless of the PDN type.
N 1 bit 2 bit 4 bit 5 bit Plane P1 P2 P4 P5 CCPTL 2P1 2P2 2P4 2P5 PBPTL 2P2 1.5P4 1.4P5 M 2 bit 4 bit 6 bit 7 bit

The power consumption doubles when using the CCPTL regardless of the bit number. The overhead decreases with the increase of bit number when using the PBPTL scheme.

PSEUDO BALANCED POWER TRANSMISSION LINE (PBPTL)

Pseudo Balanced PTL (PBPTL) *
Encode 4bit PRBS 6bit balanced Data : # of 1s = 3, # of 0s = 3 6bits are 5bits transmitted through the interconnects

PTL
1bit is discarded: balancing bit

Pseudo-Balanced Signaling

Pseudo Balanced PTL

Expected Advantages The coupling between the PDN and signal network is removed. The current through the PTL is constant at all times. The dynamic dc drop is removed. The PTL is kept fully charged.
* S. Huh, M. Swaminathan, D. Keezer; Pseudo-Balanced Signaling Using Power Transmission Line for Parallel Links, in Proc. IEEE EMC, 2011 * S. Huh, M. Swaminathan, D. Keezer; Design of Power Delivery Networks using Power Transmission Line for Multiple I/Os using PseudoBalanced Signaling, in Proc. IEEE EPEPES, 2011.

CODING CONCEPT FOR PBPTL

Constant number of 1s and 0s

Original Data
OR1 OR2 OR3 OR4 0 0 0 1 1 0 0 1

Encoded Data
EN1 EN2 EN3 EN4 EN5 EN6 0 1 1 0 0 1 0 1 1 0 1 0

After encoding, the number of 1s is 3 the number of 0s is 3 4-bit data information is mapped onto 24 balanced symbols.

PBPTL SIGNALING SCHEME

Original Data
OR1 0 0 OR2 0 1 OR3 1 0 OR4 0 1 EN1 0 1 EN2 1 0

Encoded Data
EN3 0 1 EN4 0 1 EN5 1 0 EN6 1 0

3I constant current through the PTL

PBPTL TEST VEHICLE

Power-plane-based test vehicle

PTL-based test vehicle

MEASUREMENT SETUP

Automatic test equipment is used. to feed 6-bit encoded data to drivers to supply power & ground The output of the 4th channel is connected the oscilloscope. to maximize the crosstalk effect on the waveform to maintain the same ISI effect before and after encoding

MEASURED EYE DIAGRAMS

Power Plane PBPTL w/o termination PBPTL w/ termination PRBS Data

200mV

707ps 598mV

200mV

643ps 775mV

200mV 620.7ps 773mV

-9.1%
835ps 835ps

-3.5%
835ps

-16.4% +0.8%

-10.5% -3%

Balanced Data Pseudo-Balanced Data

-23.9% -21.6%

200mV 691.7ps 693.3ps 732mV 724mV 590mV 592mV

200mV 537.8ps 542ps

801mV 795mV

200mV 555.7ps 539.3ps

809mV 809mV

-22.2% -21.8%
835ps

-0.5%
835ps

835ps

MEASUREMENT SUMMARY

Based on measurements, using the PBPTL scheme improves the eye height by 34.8% on average. reduces p-p jitter by 10.5% on average.

PBPTL IMPLEMENTATION USING CMOS 0.18UM PROCESS

To synchronize 6 outputs from the encoder

Power Plane Power Plane

PBPT L PBPTL
Z=25 Z=25 3.109V

3.109V 32u/ 0.35u 50 data1_in 16u/ 0.35u 50

Z0=50 data1_in

42u/ 0.35u 50 20u/ 0.35u

Z0=50 50

Power plane PBPTL

MEASUREMENT RESULTS
200 Mbps Power Plane 500 Mbps

PBPTL

Eye height improvement of 35%

Eye height improvement of 35% Jitter improvement of 23%

ALTERNATE APPROACH
Power Plane
To remove the RPD issue and the cavity resonance

Power Transmission Line

To remove the dynamic DC drop and the mismatch issue

Constant Current PTL

To reduce the power penalty

Pseudo Balanced PTL

To reduce the power penalty further

Constant Voltage PTL*

*S. Huh, D. Chung and M. Swaminathan; "Near Zero SSN Power Delivery Networks Using Constant Voltage Power Transmission Lines, in Proc. IEEE EDAPS, Dec. 2009

CONSTANT-VOLTAGE POWER TRANSMISSION LINE (CVPTL) CONCEPT

A possible solution for further reducing power: Constant-Voltage Power Transmission Line (CVPTL) Depending on the input data, a resistor path is selected to keep the impedance looking into the IC power supply node (Zpwr) constant
Rpath[0n000]

Rs Vs + -

Rpath[0n001]

Zpwr Vdd

Z0,PTL

Rpath[0n010]

Rpath[1n111]

data1

Z0,sig RL

data1_rx

data2

data2_rx

Z0,sig RL

CV-PTL & CC-PTL POWER CONSUMPTION COMPARISON

Simulation of 2-bit CV-PTL and CC-PTL topologies under same conditions multiple times
Pow er Savings (%) over CC-PTL 40 Power savings (%) over CC-PTL 35 30 25 20 15 10

Pow er Savings (%) over CC-PTL 40

35

30

Power savings (%)

5 0 0 100 200 300 400 500 600 700 800 900 1000 Num ber of 11s in input data
Pow er Savings (%) over CC-PTL 40 35

25

20

15

Power savings (%)

30 25 20 15 10 5 0 0 200 400 600 800 1000 1200 Num ber of 00s in input data

10

0 0 100 200 300 400 Number of 01s or 10s in input data 500 600

SUMMARY AND CONCLUSIONS

Power and Ground Planes induce Return Path Discontinuities (RPD) on Signal Lines RPDs create reduced eye height and increased jitter due to cavity resonances These can be eliminated by replacing the power plane using Power Transmission Line (PTL) Using Constant Current, Pseudo-balanced and Constant Voltage methods, the PTL concept can be used to reduce power supply noise Theory and Measurements indicate ~35% improvement in eye height and jitter compared to the use of power planes PTL results are very promising and could help eliminate capacitors as well (not covered in this presentation) Remember: PTL is a High Impedance Power Distribution Network (not Low Impedance)