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Adv Digital Design
By Dr. Shoab Ahmed Khan

shoab@avaz.com
Fall 2002
Coding Guide Lines

Engineering Education Trust Center for Advanced Studies in Engineering 5-A Constitution Avenue, Software Technology Park. Islamabad, Pakistan.
The art of algorithm to architecture mapping
Guidelines for writing efficient RTL-level Verilog HDL code
Naming Conventions
Rule:
All names (signals, variables, modules) in lowercase, parameters and macros in uppercase characters.
Use a single underscore ('_') to separate parts of a name, don't use it as first or last character.
Example:
BAD: parameter width = 16; input [width-1:0] DataIn; BETTER: parameter WIDTH = 16; input [WIDTH-1:0] data_in;
Adv. Digital Design By Dr. Shoab A. Khan
Active low signals
Rule: Active low signals must end with '_n'.
Clk and res_n
Rule: All synchronous modules must use

an asynchronous active-low reset called "res_n" a clock signal called "clk".
Explanation:
The names of clock and reset signals should be the same throughout the whole design. If multiple clocks are needed, they should use "clk" as common suffix, e.g. "bus_clk". An asynchronous active-low reset is the most common supported type of reset found in today's cell libraries.
always@(posedge clk or negedge res_n) if(!res_n)
Names
Use meaningful names for variables, signals, modules, FSM states, etc. Don't use reserved HDL keywords, either Verilog or VHDL.
Explanation:
This makes the HDL code much more readable.
Common pre-/suffixes like 'addr', 'ctrl', 'en', 'data', 'val', etc. help a lot to understand the functionality of a design.
Example: BAD:
wire w1; reg dff6; // state names s0, s1, s2, ...
BETTER:
wire addr_bus_en; reg bus_data_val; // state names IDLE, RUN, WAIT, ...
Comments Rule:
Use comments for modules and every major code block to describe the functionality.
Explanation:
This enables other designers to understand your logic in a reasonable amount of time.
Example:
/* - describe the functionality of the module - I/O constraints */ module top (...); /* implements comb/seq logic for ... */ always @(...) ...
FSM Implementation Style
Rule:
Prefer Moore machines over Mealy FSMs.
Explanation:
Mealy machines have the disadvantage that the outputs depend on the inputs, which means you have asynchronous paths in your design.
Design Methodology
Rule:
Find the right balance for your design hierarchy.
Explanation:
Too large modules (with hundreds of lines of HDL code) may become un-managable and lead to unacceptable tool run times. Too small modules (with just a few gates) prevent synthesis tools from finding an optimal implementation for your logic.
Registered Outputs
Rule:
All major functional blocks must have registered outputs.
Explanation:
It avoids asynchronous paths running through several functional blocks. Synthesis tools have a much easier job to meet timing goals, when designs stick to this rule.
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Combinational Logic
Rule: Use continuous assignments only for small equations, always blocks for larger logic. Use only blocking assignments for combinational logic. Explanation: Continuous assignments spread over multiple lines of code (e.g. using if-then-else) become unreadable. Example: 2-4 decoder using an always block 2-1 MUX using a cont. assignment always @(din) begin : decode case (din) 2'b00: dout = 4'b0001; 2'b01: dout = 4'b0010; 2'b10: dout = 4'b0100; 2'b11: dout = 4'b1000; default: dout = 4'bxxxx; endcase end assign out = (sel == 1'b0) ? a : b;
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Sequential Logic Rule:

Use always blocks with non-blocking assignments for sequential logic. Specify asynchronous behavior first, followed by the normal operation.
Explanation:
Asynchronous behavior must be specified at the beginning of an if-then-else statement to be recognized correctly by synthesis tools, followed by the normal operation of the cell.
Example:
8-bit counter with parallel load always @(posedge clk or negedge res_n) begin : main if(res_n == 1'b0) // asynch. reset cnt <= 8'h00; else if (load == 1'b1) cnt <= load_data; else cnt <= cnt + 1; end
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Assignment Use blocking assignments to model combinational logic within an always block.
Rule:
Use non-blocking assignments to implement sequential logic.
Rule:
Do not mix blocking and non-blocking assignments in the same always block.
Rule:
Do not make assignments to the same variable from more than one always block.
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Sensitivity List Rule:

Include all signals in the sensivity list of an always block describing combinational logic, that are interpreted (read) within the block (signals on RHS of assignments, signals in conditions, etc.).
Explanation:
This rule ensures that no unwanted latches are inferred during synthesis. Why do they appear? Because the goal of the synthesis tool is a functional equivalent gate-level implementation of your RTL code. So if your sensitivity list misses one signal, a simulator will not trigger the always block on its transition. That means, a transition of one of the inputs to the combinational logic block does not result in an updated output value. To match this behavior, the synthesis tool has to insert a latch.
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Example
Example: 2-1 multiplexer resulting in an inferred latch

always @(a or sel) // incomplete sensivity list begin : mux case (sel) 1'b0: y = a; 1'b1: y = b; // <- b appears on the RHS, default: y = 1'bx; // but is not in the sensivity list! endcase end
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Rule:
Label all begin...end statement blocks.
Explanation:
This can help you to locate design parts during debugging. Use short but meaningful names, like in all examples in this guide.
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Case
Rule:
If no priority is required, make sure that the different cases are mutually exclusive.
Explanation:
The synthesis tools checks for overlapping cases when it parses the HDL code. If it finds some, the resulting logic uses a priority scheme. This chained logic is significantly slower than full parallel logic, which is otherwise build.
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Implement a 4-2 encoder Two ways to implement a 4-2 encoder

BAD: always @(din) begin : encode casex (din) 4'bxxx1: dout = 2'b00; // highest priority! 4'bxx1x: dout = 2'b01; 4'bx1xx: dout = 2'b10; 4'b1xxx: dout = 2'b11; // lowest priority! default: dout = 2'bxx; endcase end
Sometimes it's a good idea to use casex and x's to specify "don't care" bits. But here all the cases overlap and you end up with priority logic during synthesis!
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Example
BETTER:
always @(din) begin : encode case (din) 4'b0001: dout = 2'b00; 4'b0010: dout = 2'b01; 4'b0100: dout = 2'b10; 4'b1000: dout = 2'b11; default: dout = 2'bxx; endcase end
At first, this might look like it results in more logic. But now all cases are mutually exclusive and the synthesis tool is allowed to use a parallel implementation for your logic, which is significantly smaller and faster!
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Avoid Latch
Rule:
Always cover all input patterns, either by specifying them or using a default case.
If possible, assign "don't care" to the output for the default case.
Explanation:
If not all possible cases are specified and no default case is given, the synthesis tool infers latches to hold the output value during the uncovered terms.
Assigning an 'x' is interpreted by a synthesis tool as "don't care", which gives room for further logic optimization. 20
If-Then-Else Statements
Rule:
Avoid long if-then-else chains.
Explanation:
Large if-then-else chains are hard to overlook. There is also again the pitfall of ending up with priority logic, when multiple conditions within one statement overlap. One should better use a case statement with mutually exclusive cases.
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Example: The same 4-2 encoder as above, now with if-then-else

BAD: always @(din) begin : encode if (din[0] == 1'b1) dout = 2'b00; else if (din[1] == 1'b1) dout = 2'b01; else if (din[2] == 1'b1) dout = 2'b10; else if (din[3] == 1'b1) dout = 2'b11; else dout = 2'bxx; end 22
Port Declarations
A consistent port declaration order can improve the reusability of your designs. Rule:
List ports in the following order: outputs, clocks/resets, inputs.
Explanation:
This complies to the method defined for Verilog primitives. Also define one port per line inside a module for better readability.
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Port Declarations
Rule:
Use connection by name when instantiating a submodule.
Explanation:
Following this rule, it is explicitly specified, which signal should connect to which port. Connection by order can introduce errors, when the port order inside the sub-module changes.
Example: BAD:
my_submod instance1(data_out, core_clk, data_in);
BETTER:
my_submod instance1(.dout(data_out), .clk(core_clk), .din(data_in));
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D Type Flip Flops:
Two things to note about inferring flip flops: Non blocking signal assignment (<=) should always be used The sensitivity list must have the keyword posedge or negedge. (also for resets)
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D-type flip flop reg q; always @ (posedge clk) q <= d;
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D type flip flop with asynchronous reset reg q; always @ (posedge clk or posedge reset) if (reset) q <= 1'b0; else q <= d;
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D type flip flop with synchronous reset reg q; always @ (posedge clk) if (reset) q <= 1'b0; else q <= d;
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D type flip flop with gated clock reg q; wire gtd_clk = enable && clk; always @ (posedge gtd_clk) q <= d;
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Data enabled D type flip flop
reg q; always @ (posedge clk) if (enable) q <= d;
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Negative edge triggered D type flip flop
reg q; always @ (negedge clk) q <= d;
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Latch
reg q; always @ (q or enable) if (enable) q = d;
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Multiplexers
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Two input multiplexer (using if else)
reg y; always @ (a or b or select) if (select) y = a; else y = b;
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Two input multiplexer (using ternary operator ?:)
wire t = (select ? a : b);
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Two input multiplexer (using case statement)
reg w; // mux version 3 always @ (a or b or select) case (select) 1'b1 : w = a; default : w = b; endcase
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Two input multiplexer (using default assignment and if)
reg p; // mux version 4 always @ (a or b or select) begin p = b; if (select) p = a; end
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Three input multiplexer with no priority (using case)

reg s; always @ (a or b or c or select2) begin case (select2) // synopsys parallel_case 2'b00: s = a; 2'b01: s = b; default: s = c; endcase end
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Comparator (using assign)
module comparator1 (a,b,c); input a; input b; output c; assign c = (a == b); endmodule
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The Role of HDLs and Synthesis in Design
Implementation Technologies Design Flows
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Implementation Technologies
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Synthesis Design Flow
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General Coding Style Guidelines
Unintentional Latch Inference

For if, set default value beforehand or specify value for else. For case, set default value beforehand or use default in case or If you know for sure some cases will not occur use compiler directive // synopsys full case
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Separating Combinational and Sequential Assignments
FSM Outputs
Sequential (Registered) - Can include in clocked always Cominational (Not Registered) - Use asynchronous always for outputs If Mealy, depend on inputs as well as state Place inputs in this case in sensitivity list
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Design Partitioning for Synthesis
Strategies
Partition for design reuse Keep related combinational logic together Avoid glue logic, particularly at top level Register block outputs Partition by design goal Partition by compile technique Keep sharable resources together Place large SRAMs and DRAMS at top core level Size blocks based on available computational resources
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Design Reuse
Partition so that existing designs can be used in your design To permit future reuse:
Define and document interface thoroughly Standardized interface Parameterize the code
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Keeping Related Combinational Logic Together
Reasons:
Default DC cannot move logic across hierarchical boundaries Logic optimization cannot cross block boundaries
Group related combinational logic & destination register together

Improves logic optimization potential Enables sequential optimization
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Avoid Glue Logic
Glue Logic
Small amounts of logic added to correct interface mismatch or add missing functionality
Eliminating glue logic

Improves logic optimization potential Reduces compile time At top level, simplifies floor-planning
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Register module outputs
If module outputs are not registered:

long, complex inter-module delay paths can exist
Example
Simulation speed is slower due to sensitivity lists that contain more than clock & reset
Example
Drive strengths on inputs to modules differ

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Register module outputs (continued)
Negatives
Registering outputs may add clock periods to system delays for function execution Registering outputs may severely restrict module boundary locations
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Partition by Design Goal
Design Goals
Area minimization Delay minimization
By partitioning on design goals:

Allows area constraints on logic without timing issues Allows timing constraints on logic without area issues Reduces optimization effort
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Partition by Compile Technique
Compile Techniques
Forcing Structure (factoring) Forcing Flattening (2-level logic)
Examples:
XOR-heavy error detection and correction Circuits should be structured Random logic should be flattened Therefore, should not be together in module
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Keep Sharable Resources Together
Only resources within the same always can be shared.
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Keep UDRs with the Logic They Drive
If duplication to meet timing constraints is necessary, can do it Delay may be reduced by reducing the fanout on a given UDR by duplicating it
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Isolating Special Functions
Includes pads, I/O drivers, clock generation, boundary scan, and asynchronous modules The external interface should be at the top level and not placed in modules Special functions that tie to the interface should be at the next hierarchical level down Asynchronous functions should be separate modules at an appropriate level of the hierarchy Example: Figure 3-10 DCUG
55
Place large SRAMs, DRAMS & ROMs at top core level
Relates to physical design interaction with synthesis Large memory structures need to be placed in the floorplan independently of logic Floorplanning is needed to do accurate timing analysis and control Example
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Size blocks based on computational resources
Large blocks permit optimization flexibility Large block my overwhelm workstation in terms of memory, swap space or processing throughput Large blocks my cause excessive compile times Thus, need to select workable intermediate size for blocks
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Partitioning for Synthesis
Register all outputs.
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Partitioning for Synthesis
Separate modules that have different designs

Critical logic Non Critical
Preferred way
Critical logic Non Critical
area
Control
Synthesized data for time
Synthesized for area
59
Avoid Asynchronous Logic
You might be able to convert asynch
synch
If required partition asynchronous logic in separate module If delay required you may use buffers
A0 A1 A2
For generating a pulse
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Merging Resources
Resource sharing off
If ( cnt ) z = a+b else z = c+d
+
a c
better way using one adder
b d
Select operands
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Eliminate glue logic at the top level
In top level you must use only instantiations

Bad Design
move this inside Instantiation of modules
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Coding for synthesis
Simulation Algorithmic Behavioral level FPGA
RTL
for synthesis
FPGA Concerned with this one
RTL device
Behavioral
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Inter Register
Use register for sequential logic Dont use initial statement

Use reset
64
Avoid latches
Avoid combinational loopback.

Combinational cloud Combinational cloud
Combinational cloud
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Adv Digital Design

By Dr. Shoab Ahmed Khan

Coding Guide Lines

The art of algorithm to architecture mapping

Guidelines for writing efficient RTL-level Verilog HDL code

Adv. Digital Design By Dr. Shoab A. Khan

Active low signals

Rule: Active low signals must end with '_n'.

Adv. Digital Design By Dr. Shoab A. Khan

Clk and res_n

Rule: All synchronous modules must use

Adv. Digital Design By Dr. Shoab A. Khan

FSM Implementation Style

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Sequential Logic Rule:

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Sensitivity List Rule:

Adv. Digital Design By Dr. Shoab A. Khan

Example: 2-1 multiplexer resulting in an inferred latch

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Implement a 4-2 encoder Two ways to implement a 4-2 encoder

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Example: The same 4-2 encoder as above, now with if-then-else

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

D Type Flip Flops:

Adv. Digital Design By Dr. Shoab A. Khan

D-type flip flop reg q; always @ (posedge clk) q <= d;

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Data enabled D type flip flop

reg q; always @ (posedge clk) if (enable) q <= d;

Adv. Digital Design By Dr. Shoab A. Khan

Negative edge triggered D type flip flop

reg q; always @ (negedge clk) q <= d;

Adv. Digital Design By Dr. Shoab A. Khan

reg q; always @ (q or enable) if (enable) q = d;

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Two input multiplexer (using if else)

reg y; always @ (a or b or select) if (select) y = a; else y = b;

Adv. Digital Design By Dr. Shoab A. Khan

Two input multiplexer (using ternary operator ?:)

wire t = (select ? a : b);

Adv. Digital Design By Dr. Shoab A. Khan

Two input multiplexer (using case statement)

Adv. Digital Design By Dr. Shoab A. Khan

Two input multiplexer (using default assignment and if)

reg p; // mux version 4 always @ (a or b or select) begin p = b; if (select) p = a; end

Adv. Digital Design By Dr. Shoab A. Khan

Three input multiplexer with no priority (using case)

Adv. Digital Design By Dr. Shoab A. Khan

Comparator (using assign)