Synopsis Work:

Relevance The fast Fourier transform (FFT) algorithm has been widely used in many discrete-time signal processing systems. Especially in recent years, many advanced communication systems including digital audio broadcasting (DAB), digital video broadcasting (DVB), wireless networks, or high-speed digital subscriber line (ADSL) systems all require a core FFT module to process the orthogonal frequency division multiplexing (OFDM) function. Therefore, how to design an efficient dedicated FFT circuit especially for the emerging OFDM applications is a very important issue. When a good designer designs architecture, the ultimate aim of he is to reduce the hardware complexity, reduce the power consumption, increase speed of operation i.e. reduce the propagation delay and increase the throughput. Designer should take all the constraints above into account while designing the architecture. Present Theories Much research has been carried out on designing pipelined architectures for computation of FFT of signals. Various algorithms have been developed to reduce the computational complexity, of which Cooley-Tukey radix-2 FFT is very popular. On the basic radix-2 FFT approach algorithms radix-4, split-radix and radix- 2^2 have been developed. In the literature based on these algorithms there are some standard architectures, Radix-2multi-path delay commutator (R2MDC) is one of the most classical approaches for pipelined implementation of radix-2 FFT. Efficient usage of the storage buffer in R2MDC leads to the Radix-2 Single-path delay feedback (R2SDF) architecture with reduced memory. Several parallel architectures for FFT have been proposed in the literature, architectures are developed for a specific -point FFT. A formal method of developing these architectures from the algorithms is not well established. Further, most of these hardware architectures are not fully utilized and require high hardware complexity. In the era of high speed digital communications, high throughput and low power designs are required to meet the speed and power requirements while keeping the hardware overhead to a minimum. Few pipelined architectures for real valued signals have been proposed based on the Brunn algorithm. However, these are not widely used. Several
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algorithms have been proposed for computation of RFFT. These approaches are based on removing redundancies of the FFT when input is real. These can be efficiently used in a digital signal processor compared to a specialized hardware implementation. Problem Definition FFT architecture design and implementation with low hardware complexity FFT plays a critical role in modern digital communications such as digital video broadcasting and orthogonal frequency division multiplexing (OFDM) systems. The applications like Digital video broadcasting orthogonal frequency division (OFDM) multiplexing where very high throughput rates and continuous data flow are essential (higher than tens of millions of samples per Second), the use of pipeline or parallel pipelined architectures are almost imperative. Proposed Work In this project I am going to design and implement FFT architecture with low hardware complexity in Xilinx using pipelining, parallel processing and folding transformation as per requirement. The design part consists of design of Cooley-Tukey radix-2 algorithm for FFT calculation. There are two main types of Cooley-Tukey radix-2 algorithm, decimation in frequency (DIF) and decimation in time (DIT). I am going to design one of them. Challenges 1. Implementation of butterfly structure 2. Multiplication by Twiddle factor 3. Interconnection 4. Design of delay control logic 5. Register minimization 6. Pipelining and parallel processing Advantages 1. Low hardware complexity. 2. Increase in sample rate. 3. Reduction in power consumption.
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Plan of Action

Task Literature Survey Finalizing Topic Collecting all required data Synopsis submission Design of 1st stage of FFT Design of 2nd stage of FFT Complete FFT implementation and verification

July12

Aug12

Sept12

DP 1st

DP 2nd

DP 3rd

DP 4th

Comparison Parameter A comparison will be made between the previous pipelined architectures and the proposed ones for the case of computing an N-point FFT. The comparison will be based on number of required multipliers, adders, delay elements, throughput and control. ,

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References
Papers: 1. Manohar Ayinala, Michael Brown, Keshab K. Parhi, Pipelined Parallel FFT Architectures via Folding Transformation, IEEE Trans. On very large scale integration systems, vol. 20, no. 6, pp. 1068-1081 June 2012 2. M. Garrido, K. K. Parhi, and J. Grajal, A pipelined FFT architecture for real-valued signals, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 12, pp. 26342643, Dec. 2009 3. Yun-Nan Chang, An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design, IEEE Trans. on Circuits and Systemsii: express briefs, vol. 55, no. 12, pp. 1234-1238, Dec. 2008 4. Chao Cheng, Keshab K. Parhi, High-Throughput VLSI Architecture for FFT Computation, IEEE Trans. on Circuits and Systemsii: express briefs, vol. 54, no. 10, pp. 863-867, oct. 2007 5. Wei-Hsin Chang, Truong Nguyen, An OFDM-Specified Lossless FFT Architecture, IEEE Trans. on Circuits and Systemsi: regular papers, vol. 53, no. 6, pp. 1235-1243, June 2006 6. Yun-Nan Chang, Keshab K. Parhi, An Efficient Pipelined FFT Architecture IEEE Trans. on Circuits and Systemsii: analog and digital signal processing, vol. 50, no. 6,pp. 322-326, June 2003 7. Malcolm D. Macleod, Multiplierless Winograd and Prime Factor FFT Implementation, IEEE Signal processing letters, vol. 11, no. 9,pp. 740-743 Sept. 2004 8. Hao Xiao, An Pan, Yun Chen, and Xiaoyang Zeng, Low-Cost Reconfigurable VLSI Architecture for Fast Fourier Transform, IEEE Signal processing letters

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Websites: [1] www.ieeexplore.org [2] www.wikipedia.org [3] www.xilinx.com

1. Facilities Available Library, VLSI Lab, Internet etc. 2. Softwares Required Xilinx ISE Design Suite 13.2, 3. Expected Date of Completion July, 2013.

Prof. B.G. Patil (Guide)

Mr. Tanaji U. Kamble (Student)

Dr. [Mrs.] S.S.Deshpande (H.O.D)

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