Combinational Logic Gates

Combinational vs. Sequential

Combinational

Sequential

Combinational Circuits: At any time t, F(in) is constant for a given input combination in

Sequential Circuits: out = F(In, InPrevious)

Static vs. Dynamic

Combinational CMOS
VDD In1 In2 InN In1 In2 InN PMOS only F(In1,In2,InN) PDN PUN

NMOS only

Only one of the network is conducting at any given time (except during switching)

Combinational CMOS
VDD In1 In2 InN In1 In2 InN PDN PUN PMOS only F(In1,In2,InN) NMOS only

Why Static CMOS:

Good performance

Great robustness against noise

No static power

Strong 0's and 1's

VDD 0
D

VDD
S

CL

Strong 0

Strong 0's and 1's

VDD
D

VDD

VGS

0 VDD - VTn CL

Weak 1

Strong 0's and 1's

VDD
S

0 VDD CL

Strong 1

Strong 0's and 1's

VGS VDD |VTp|
S

CL

Weak 0

Strong 0's and 1's

PUN VDD
S

VDD
D

VDD
D

0 VDD CL

VGS

0 VDD - VTn CL

PDN
D

VDD 0
VDD
S

VGS

VDD |VTp|
S

CL

CL

NMOS cannot propagate strong 1's

PMOS cannot propagate strong 0's

Threshold drop

Strong 0's and 1's

Strong 0's and 1's

Logic Rules

Complex Functions
B A

PUN and PDN are dual networks CMOS is naturally inverting

C D

OUT = D + A (B + C) A D B C

Complex (active low) function can be achieved with just one PDN and one PUN

Voltage Transfer Characteristic

Noise Margin for NMOS inverter

Voltage Transfer Characteristic

Case 1: (blue) both A & B change from 0 to 1 simultaneously

Has the biggest noise margin

Voltage Transfer Characteristic

Case 2: (Green) Hold A at 1, change B from 0 to 1

Only one PMOS is conducting, therefore PDN is stronger

Voltage Transfer Characteristic

Case 3: (Red)
Hold B at 1, change A from 0 to 1 PDN slightly weaker than in case 2, due to body effect

Voltage Transfer Characteristic

Conclusion: Noise margins are input pattern dependent

Propagation Delay

Simplified RC model of a NAND gate

Propagation delay: Time it takes to get to 50% of required output value, or 0.69 x time_constant

Propagation Delay

Case 1
A: 1 0, B: 1 0

Pull-up path delay

0.69 x Rp/2 x CL

Propagation Delay

Case 2
A: 1 1, B: 1 0

Pull-up path delay

0.69 x Rp x CL

Propagation Delay

Case 3
A: 0 1, B: 0 1

Pull-down path delay

0.69 x 2RN x CL

Propagation Delay

Conclusion

Adjust transistor size according to worst case scenario (here double the size of the NMOS transistors)

Propagation Delay

CMOS Problem: Large Fan-in

As the fan-in grows the propagation delay deteriorates rapidly

1.Many PMOS transistors in a NAND gate PUN will add up to a large total capacitance 2.The series connection will get longer longer path delay

CMOS Problem: Large Fan-in

A quadratic relationship

Dealing with Large Fan-in

1) Increase the sizes of all transistors

Consequence: a decrease in resistance, but an increase in capacitance Only effective when dealing with large fan-out loads

Dealing with Large Fan-in

2) Progressive transistor sizing

Avoids the accumulation of capacitance Boosts the speed of the most critical transistors Difficult to do efficiently on the layout level

Dealing with Large Fan-in

3) Input reordering

Dealing with Large Fan-in

4) Logic Restructuring

Power Consumption

Two types

Dynamic: dominant Static: negligible but significant in < 65nm

Physics reminder

P = V . I = dE / dt E = V.i(t).dt = V C.(dV/dt).dt = CV dV = CV2

Dynamic Power Consumption

Occurs only when output switches Two causes

a) Charging and discharging of capacitances

b) Direct path current

Dynamic Power Consumption

Charging and discharging of capacitances E = CLVDD2

P = CLVDD2f

Famous equation for describing dynamic power dissipation

With switching probability (): P = CLVDD2f (0<<1)

Dynamic Power Consumption

Direct path current (short circuit current)

Pdp = CSCVDD2f CSC = tscIpeak/VDD tsc is the time the devices are conducting
Usually combined with charge/discharge current by adding Csc to CL

Static Power Consumption

Power dissipation in steady state Due to leakage current in reverse bias diodes inside the transistor

Pstatic = IstaticVDD

Dynamic Power Consumption

How to decrease power dissipation? Pdyn = CLVDD2f Totol Power Consumption: Pdynamic + Pstatic

Static Logic Design Styles

CMOS Complementary PUN and PDN Ratioed Logic PUN is one PMOS

Pseudo-NMOS

Differential Cascade Voltage Swing Logic (DCVSL)

Pass Transistor Logic Trans. as pass gates

Pseudo NMOS

Ratioed because ratio of trans. width determines output voltage. Bad performance, noise margins, and power dissipation. Good area saving.

Pseudo NMOS

Used for high fan-in gates

Differential Cascade Voltage Swing Logic (DCVSL)

Provides complementary (differential) outputs, very fast, but has high dynamic power and requires tedious wiring.

Pass Transistor Logic

Very fast
Suffers from threshold drops

Transmission Gates

Connect source and drain of PMOS and NMOS

Let the NMOS take care of propagating the 0, PMOS the 1.

Strong 0's and 1's

Transmission Gates

This circuit still would not work. Why?

XOR Gate (8 transistors)

Another XOR Gate (6 transistors)

Transmission Gates

What does this circuit do?

4-to-1 Multiplexer

Transmission Gate

Suffers from relatively high resistance and propagation delay when placed in series Use sparingly

Glitching

Causes excessive power consumption

Glitching