Sub-envelope modulation method to reduce total harmonic distortion of AC/AC matrix converters

F.L. Luo and Z.Y. Pan Abstract: An AC/AC matrix converter is an array of power semiconductor switches that connects directly a three-phase AC source to another three-phase load. It can convert an AC power source with certain voltage and frequency to another AC load with variable voltage and variable frequency directly without a DC-link and bulk energy storage component. Classical modulation methods such as the Venturini method and the space vector modulation method using AC-network maximum-envelope modulation, implement matrix conversion successfully. However, they also cause very high total harmonic distortion (THD). A novel approach, the sub-envelope modulation (SEM) method, is presented to reduce THD of matrix converters effectively. The approach is extended to an improved version of matrix converters and the THD can be reduced further. The algorithm of the SEM method is described in detail. Simulation and experimental results are also presented to verify the feasibility of the SEM approach. The results will be very helpful for industry applications.

Introduction

An AC/AC matrix converter [13] is an array of power semiconductor switches that connects directly a three-phase AC source to another three-phase load. This converter has several attractive features that have been investigated in recent decades. It can convert an AC power source with certain voltage and frequency to another AC load with variable voltage and variable frequency directly without a DC-link and bulk energy storage component. It eliminates large energy storage components, i.e. bulk inductor or electrolytic capacitors. The structure of a classical 3 3 matrix converter is shown in Fig. 1. The semiconductor switches are marked SJk, which means the switch is connected between input phase J and output phase k, where J {A, B, C}, k {a, b, c}. All the switches SJk in the matrix converters require a bidirectional-switch capability of blocking voltage and conducting current in both directions. Unfortunately, there are no such devices available now, so discrete devices need to be used to construct suitable switch cells. One option is the diode bridge bidirectional switch cell arrangement, which consists of an insulated gate bipolar transistor (IGBT) (or other full control power semiconductor switches) at the centre of a single-phase diode bridge [4]. The main advantage is that both current directions are carried by the same switching device, therefore, only one gate driver is required per switch cell. Device power losses are relatively high since there are three devices in each conduction path. The current direction through the switch cell cannot be controlled. This is a disadvantage since many
r The Institution of Engineering and Technology 2006 IEE Proceedings online no. 20060015 doi:10.1049/ip-epa:20060015 Paper rst received 21st December 2005 and in nal revised form 31st May 2006 The authors are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Block S1-B1c-108, Nanyang Avenue, Singapore 639798 E-mail: eluo@ntu.edu.sg

advanced commutation methods require the current direction of the switch cell to be controllable. The common emitter bidirectional switch cell arrangement consists of two IGBTs, and another scheme is two diodes. The diodes provide the reverse blocking capability. There are several advantages using this arrangement when compared to the diode bridge bidirectional switch cell. First, it is possible to control the current direction independently. Secondly, conduction power losses are also reduced since only two devices carry the current. Thirdly, each bidirectional switch cell requires an isolated power supply for the gate drive. The switch cell can be connected in common collector mode. The conduction power losses are the same as that of the common emitter conguration. An often-quoted advantage of this method is that only six isolated power supplies are needed to supply the gate driver [5]. Therefore, the common collector conguration is generally preferred for creating the matrix converter bidirectional switch cells. Normally, the matrix converter is fed by a three-phase voltage source and, for this reason, the input terminals

Fig. 1

Structure of conventional matrix converter

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should not be in short-circuit (rule 1). On the other hand, the load has typically an inductive nature and, for this reason, an output phase must never be in open-circuit (rule 2). Reliable current commutation between switches in matrix converters is more difcult to achieve than in conventional voltage source inverters (VSI) since there are no natural freewheeling paths [1]. The commutation has to be actively controlled at all times with respect to the two basic rules. These rules can be visualised by considering just two switch cells and one output phase of a matrix converter. It is important that no two bidirectional switches are switched on at any one time, as shown in Fig. 2a. This would result in line-to-line short-circuiting and the destruction of the converter owing to rush current. Also, the bidirectional switches for each output phase should not all be turned off at any instant, as shown in Fig. 2b. This would result in the absence of a path for the inductive load current, causing rush voltage. These two considerations cause a conict since semiconductor devices cannot be switched instantaneously owing to propagation delays and nite switching times. There are some successful approaches to avoid these two cases: basic current commutation [1], current direction based commutation [68], relative voltage magnitude based commutation [911], and soft-switching techniques [1113].

SEM method

One commonly used modulation method for matrix converters is maximum envelope modulation, which is shown in Fig. 3a, i.e. the output phase voltage is pulsewidth modulated between maximum input phase and minimum input phase. The disadvantages are obvious: the magnitude of the output pulse is the difference between maximum input phase and minimum input phase, so the output pulse has high magnitude and narrow width. Therefore, there are many high-frequency components in the output voltage, and they will cause very high THD. Moreover, there is high dv/dt, which will induce severe EMI.

Fig. 3

Modulation method for conventional matrix converter

a Maximum envelope modulation method b SEM method

Fig. 2

Two cases that the matrix converter should avoid

a Short circuits on the matrix converter input lines b Open circuits on the matrix converter output lines

Classical modulation methods, such as the Venturini method [2, 3] and the space vector modulation (SVM) method [10] using AC-network maximum-envelope modulation, implement matrix conversion successfully. However, they also cause very high total harmonic distortion (THD). This paper presents a novel approach, the subenvelope modulation (SEM) method to reduce THD for matrix converters effectively. The approach is extended to an improved version of matrix converters and the THD can be reduced further. The algorithm of the SEM method is described in detail. Simulation and experimental results are also presented to verify the feasibility of SEM approach. The results will be very helpful in industry applications. In the following description, we assume:  The three phases of the AC input supply are balanced; input phase voltages are vA, vB and vC.  The frequency of the input AC supply is fi, corresponding angular speed is oi 2pfi.  The output phase voltages are va, vb and vc.  The output frequency is fo, corresponding angular speed is oo 2pfo.  The switching frequency is f, period is T. Usually, fcfi and fO.  Vdc is the imaginary DC-link voltage, corresponding to the maximum-envelope rectifying average voltage.
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In practice, using matrix converters, the three output phases can be connected to any input phases, so the output phase can be modulated between any two input phases. If the output phase is modulated between two adjacent input phases, as shown in Fig. 3b, the pulse magnitude of the output voltage can be low. Correspondingly, the highfrequency components of the output voltage can be reduced. Thus THD and dv/dt are also reduced. The input line current pulses are smaller and wider, and the THD of the input line current are also reduced. The approach is called the sub-envelope modulation (SEM) method. The structure of the matrix converter implementing the SEM method is shown in Figs. 4a and b. The matrix converter comprises 18 power semiconductor switches (nine switch cells) in Fig. 4a so that all the output phases can connect to any input phases with bidirectional current capability. The switches are marked with SKjr or SKjf, where K {A, B, C} is the input phase, j {a, b, c} is the output phase, r means the switch carries current from output to the input (reverse), and f means the switch carries the current from input to the output ( forward). It has been mentioned that the common collector switch cell has the advantage of requiring fewer isolated DC power supplies for the gate drives. The nine switch cells (18 switches) are in common collector conguration. The 18 switches can be divided into six switch groups: SAjr, SBjr, SCjr, SKaf, SKbf, SKcf. Each group comprises three common emitter switches and uses a common gate drive output DC oating power supply. The matrix converter comprises 24 power semiconductor switches (12 switch cells) in Fig. 4b so that all the output phases can connect to any input phases and neutral O with bidirectional current capability. The switches are marked with SKjr or SKjf, where K {A, B, C, O} is the input phase j {a, b, c} is the output phase. The 12 switch cells (24 switches) are in common collector conguration. The 24 switches can be divided into seven switch groups: SAjr, SBjr, SCjr, SOjr, SKaf, SKbf, SKcf. Each group comprises three or four common emitter switches and uses a common gate drive output DC oating power supply. The output waveform vcom of the comparator is shown in Fig. 4c.
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Fig. 4

Structure of matrix converter with SEM drive system

a Structure with nine cells b Structure with 12 cells c Output of the comparator

2.1 Measurement of input instantaneous voltage

It is required to know the instantaneous phase voltage of the AC supply. One approach is to measure the input voltage with three voltage sensors, as shown in Fig. 4a. If the AC supply is a balanced pure sinusoidal supply, one simple approach to get the instantaneous phase voltage is applicable, i.e. calculating the input voltage in real time.
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If the magnitude and timebase of the three-phase supply are known, the instantaneous phase voltage can be determined. Thus a three-phase transformer and a rectier are adopted. The turns ratio of the transformer is n : 1. The adoption of a transformer is to isolate the control circuit from the power stage. The scaled DC-link voltage Vdc/n can be obtained by a small rate rectier and an electrolytic capacitor. To obtain the timebase, a comparator is introduced. The input of the
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comparator can be either of two input phases (such as phase A and phase B). At the falling edge of vcom (such as t1), the instantaneous phase voltage of the AC supply can be obtained: 9 vA t1 Vm sin 5p=6 > > = 1 vB t1 Vm sin p=6 > > ; v t V sin p=2
C 1 m

p where Vm pVdc =3 3 and Vdc is the imaginary DC-link voltage. The frequency of AC power supply is called fi and the angular frequency oi 2pfi . Redening the initial time the instantaneous input voltage during one cycle (1/fi Ti) can be expressed as: 9 p vA t pVdc sin oi t 5p > 6 > 3 3 > > = pVdc sin o t p 2 vB t 3p i 6 3 > > > > p vC t pVdc sin oi t p ; 2 3 3 In a discrete system with sampling frequency f (sampling time T), the voltage sequence of the AC power supply can be obtained from (2): 9 p vA kT pVdc sin oi kT 5p > 6 > 3 3 > > = pVdc sin o kT p 3 vB kT 3p i 6 3 > > > > p vC kT pVdc sin oi kT p ; 2 3 3 With the help of signal vcom, the voltage sequence of the AC power supply can be calculated rigorously without error accumulation.

2.2

Modulation algorithm

An SEM example (only va is illustrated) is shown in Fig. 5a. The output is modulated between the two most adjacent input phases. The modulation rule of the example is given in Table 1. vhigh is the smallest voltage that is greater than vra (vra is reference voltage of output phase a), vlow is the largest one that is less than vra, i.e. ) vhigh minfvi jvi 4vra g; i a; b; c 4 vlow maxfvi jvi ovra g; i a; b; c Then output phase a is connected to the two most adjacent phases alternately and the duty cycle of PWM d can be determined: va vlow 5 d vhigh vlow Assume that the output frequency is fo, the magnitude of the reference output phase voltage is Vo, the angular frequency oo 2pfo , and the initial phase angle is f0 . The PWM switching frequency is f and the period is T. The modulation algorithm of the system can be accomplished by: Algorithm 1 Dene the variables hi, ho, and set their initial values to zero, i.e. hi 0; ho 0
Fig. 5 Maximum voltage ratio with and without common-mode voltage
a SEM waveforms for nine-switch cells matrix converter b Maximum voltage ratio of 50% without common-mode voltage c Maximum voltage ratio of 87% with common-mode voltage

Table 1: SEM rule of example in Fig. 5a

Time Modulation vhigh phase vlow Time Modulation vhigh phase vlow t1 vA vB t7t8 vB vC t1t2 vC vB t8t9 vC vA t2t3 vA vC vB vA t3t4 vA vB vC vB t4t5 vB vC vC vA t5t6 vA vC vA vB t6t7 vB vA vC vB

t9t10 t10t11 t11t12 t12t13 t13

Dene array vi[3] to store input phase voltage; Dene array order[3] to map vi to the input phase, and initialise the array with {1, 2, 3} representing {A, B, C};
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Do nothing until the rst falling edge of the signal vcom comes. When the rst falling edge comes, for every PWM
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cycle T, do the following loop: (a) Calculate AC power supply voltage vi [1] vA(kT ), vi [2] vB(kT), vi [3] vc (kT) according to (3): 9 vi 1 vA kT Vm sinyi 5p=6 > > = 6 vi 2 vB kT Vm sinyi p=6 > > ; vi 3 vC kT Vm sinyi p=2 p where Vm pVdc =3 3 is the magnitude of input phase voltage which is measured from the transformer. If the AC power supply is measured by three voltage sensors, this step can be ignored. (b) Sort the voltages vi [1], vi [2], vi [3] in descending order: (i) If vi [1] o vi [2], then exchange vi [1] and vi [2], also exchange order[1] and order[2]; else do nothing; (ii) If vi [1] o vi [3], then exchange vi [1] and vi [3], also exchange order[1] and order[3]; else do nothing; (iii) If vi [2] o vi [3], then exchange vi [2] and vi [3], also exchange order[2] and order[3]; else do nothing; Thus the condition vi [1] Z vi [2] Z vi [3] is satised, then the variable order will also map the input phases. (c) Calculate three output voltage va, vb, vc using the following equation: 9 va Vo sinyo f0 > = 7 vb Vo sinyo 2p=3 f0 > ; vc Vo sinyo 4p=3 f0 where Vo is the magnitude of reference output phase voltage, f0 is the initial phase angle. (d) For the value of va do the following: (i) If va Z vi [2], it means that va is between vi [1] and vi [2], then output phase a is modulated between input phase order[1] and order[2], and the PWM duty cycle d is va vi 2 8 d vi 1 vi 2 (ii) Else means that va is between vi [2] and vi [3], then output phase a is modulated between input phase order[2] and order[3], and PWM duty cycle d is d va vi 3 vi 2 vi 3 9

The output phase voltage is:

9 va t qVm sinoo t > = vb t qVm sinoo t 2p=3 > ; vc t qVm sinoo t 4p=3

11

where q is the voltage ratio of the output voltage (voltage transfer gain, usually q o 1). The direct phase voltage modulation from (11) has a maximum voltage ratio of 50%,as shown in Fig. 5b. An improvement in voltage ratio p to 3=2 (or 87%) is possible [15, 16] by adding commonmode voltages to the target outputs as ! 9 sin3oo t sin3oi t > > p va t qVm sinoo t > > 6 > 2 3 > !> sin3oo t sin3oi t = p vb t qVm sinoo t 2p=3 > 6 2 3 > !> > > sin3oo t sin3oi t > > ; p vc t qVm sinoo t 4p=3 6 2 3 12 The common-mode voltages have no effect on the output line-to-line voltages, but allow the target outputs to t within the input voltage envelope with a value of up to 87%, as shown in Fig. 5c. The improvement in voltage ratio is achieved by redistributing the null output states of the converter (all output lines connected to the same input line) and is analogous to the similar well-established technique in conventional DC-link PWM converters. It should be noted that a voltage ratio of 87% is the intrinsic maximum for any modulation method. Venturini provides a rigorous proof of this fact in [14] and [15]. To increase the voltage ratio, (7) in Algorithm 1 should be changed to p 9 vco sin3yo =6 sin3yi =2 3 > > > = va Vo sinyo f0 vco 13 vb Vo sinyo 2p=3 f0 vco > > > ; vc Vo sinyo 4p=3 f0 vco

2.4

24-switch matrix converter

From Fig. 5a, if the reference voltage is greater than zero and the three-phase four-wire supply system is available, the output is modulated between two positive phases or neutral point and one positive phase, and the THD can then be further reduced. The structure of a 24-switch matrix converter is shown in Fig. 4b. The modulation is shown in Fig. 6. The modulation rule of the example is shown in

(e) Do a similar procedure as (d) for vb and vc. ( f ) Increase hi by oi T . (g) Add ho with oo T , if ho is greater than 2p, then subtract 2p from ho. (h) Wait for the next PWM cycle and repeat (a)(g). Meanwhile, if falling edge of the signal vcom comes, set variable hi to zero.

2.3

Improvement of voltage ratio

Assume that the input AC supply phase voltage is: 9 vA t Vm sinoi t > = vB t Vm sinoi t 2p=3 > ; vC t Vm sinoi t 4p=3
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10
Fig. 6 SEM waveforms for 12-switch cell matrix converter
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Table 2. The modulation algorithm is similar to Algorithm 1 except for procedure (d). Algorithm 2 Dene the variable hi, ho, and set their initial value to zero, i.e. hi 0 ho 0

Dene array order[3] to map vi to the input phase, and initialise the array with {1, 2, 3}, representing {A, B, C}; Dene variables vhigh and vlow to store the voltages that have been modulated; Do nothing until the rst falling edge of the signal vcom comes. When the rst falling edge comes, for every PWM cycle T, do the following loop: (a), (b) and (c) are the same as those in Algorithm 1. (d) For the value of va do the following: (i) If va Z vi [2], it means that va is between vi [1] and vi [2], then store the vi [1] to vhigh, store vi[2] to vlow. (ii) Else means that va is between vi [2] and vi [3], then store the vi [2] to vhigh, store vi [3] to vlow. (iii) If va 4 0 and vlow o 0, then store the vlow with zero. It means that va is modulated between neutral point and lower positive phase which is higher than va. (iv) Else do nothing. It means that va is modulated between two positive phases. (v) If va o 0 and vhigh 4 0, then store the vhigh with zero. It means that va is modulated between neutral point one higher negative phase which is lower than va.

Dene array vi [3] to store input phase voltage;

Table 2: Modulation rule of example in Fig. 6 of 24-switch matrix converter
Time Modulation vhigh phase vlow Time Modulation vhigh phase vlow t1 vA 0 t7t8 0 vC t1t2 vC 0 t8t9 vC 0 t2t3 vA vC vB 0 t3t4 vA 0 vC vB t4t5 0 vC vC 0 t5t6 vA vC 0 vB t6t7 0 vA

t9t10 t10t11 t11t12 t12

Fig. 7

Simulations results with enhance ratio modulation

a Phase voltage with modulation I b Phase voltage with modulation II c Phase voltage with modulation III d Lineline voltage with modulation I e Lineline voltage with modulation II f Lineline voltage with modulation III g FFT Fig. 7d (THD 43.4%) h FFT Fig. 7e (THD 23.6%) i FFT Fig. 7f (THD 15.8%)
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(vi) Else do nothing. It means that va is modulated between two negative phases. (vii) Calculate the PWM duty cycle d d va vlow vhigh vlow 14

(e), ( f ), (g) and (h) are also the same as those in Algorithm 1. 3 Simulation and experimental results

The simulation and experimental results are based on threephase voltage modulation methods:  Modulation I: maximum envelop modulation for conventional nine-switch cell matrix converter.  Modulation II: SEM method for conventional nineswitch cell matrix converter.  Modulation III: SEM method for 12-switch cell matrix converter. With improved modulation ratio, the voltage ratio can reach about 87%. The simulation results of the phase voltage, lineline voltage and FFT of the lineline voltage with modulation IIII are shown in Fig. 7. The input phase voltage is 240 V (RMS value, the same for the following), frequency is 50 Hz; output phase voltage is 207 V, frequency 100 Hz. Switching frequency is 2 kHz. The THDs under the three different modulation methods are 43.4, 23.6 and 15.8%, respectively. The simulation result of THD as a function of modulation index with modulation methods IIII (output frequency 130 Hz) is shown in Fig. 8. To verify the feasibility of the proposed scheme, a 12-switch cell matrix converter was built. The modulation algorithm was implemented by a DSP TMS320F2407,

which is specialy designed for power electronics and electric drives. The digital-signal-processor (DSP) comprises dual 10-bits 16-channel analogue-to-digital converter (ADC), PWM generator, digital I/O and other modules. So the DSP can measure input voltages, generate three required PWM signals for three output phases and indicate to a peripheral circuit which phases are to be modulated. The peripheral circuit is to generate gate signal for matrix converter (include current commutation), which is built up by GAL PLD, logic gate, monostable ipops and so on. A 15 A/1200 V 1MBH15-120 IGBT was adopted as the main switch. A photo-coupled gate driver, TLP250, was used to implement the gate drive circuit. This gate driver provides a peak output current of 1.5A. It also isolates the input signal from the output and thus common-mode noise is reduced.

Fig. 8

Simulation result of THD against modulation index

Fig. 9 Experimental waveforms of output lineline voltage (top, 400 V/div.), phase current (middle, 8 A/div.) and FFT of line-line voltage (bottom, 20 dB/div., 5 kHz/div.) under various modulation methods
a Modulation method I (output frequency 130Hz; lineline voltage 360V; THD 38.5%) b Modulation method II (output frequency 130Hz; lineline voltage 360V; THD 18.8%) c Modulation method III (output frequency 130Hz; lineline voltage 360V; THD 14.3%) d Modulation method III (output frequency 35Hz; lineline voltage 252V; THD 12.9%)
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magnitude of the lineline voltage is 252 V. Experimental waveforms of input line current (phases A and B) and their FFT under modulation I with THD 32.9% and modulation III with THD 12.2% are shown in Fig. 10. The THD of input line current with modulation III is also reduced. 4 Conclusions

AC/AC matrix converters have been popular since the 1980s. Unfortunately, classical modulation methods, such as the Venturini method and the SVM method using AC-network maximum-envelope modulation, cause very high THD. A novel approach, the SEM method for conventional nine-switch cell matrix converter, has been successfully created. The corresponding THD is reduced signicantly. The approach has been extended to the 12-switch cell matrix converter and the THD can be further reduced. The modulation algorithm has been described in detail. Simulation and experimental results have also been presented to verify the feasibility of this novel modulation approach. The results will be very helpful in industry applications. 5 References

Fig. 10 Experimental waveforms of input line current (top, 8 A/div.) and FFT of line current (bottom, 20 dB/div., 5 kHz/div.) under modulation I and III
a Modulation method I, THD 32.9% b Modulation method III, THD 12.2%

The phase voltage of the AC power supply is 240 V, lineline voltage is around 415 V, and frequency fi is 50 Hz. Switching frequency f is 10 kHz. Modulation methods IIII can be implemented by the same hardware only by changing the software of the DSP. A 2.2 kW three-phase induction motor was connected to the output of the matrix converter as load. Experimental waveforms of output lineline voltage, phase current of the induction motor and FFT of the lineline voltage under modulation methods IIII are shown in Fig. 9. All the voltage signals are measured by a differential probe with a gain of 20, the voltage scale is 400 V/div., current scale is 8 A/div., the magnitude scale of the FFT waveform is 20 dB/div., frequency scale is 5 kHz/div. Figure 9a shows the results implementing modulation I with THD 38.5%, output p frequency fO is 130 Hz, the voltage ratio d is 3=2, and the magnitude of the output lineline voltage is 360 V. The experimental results implementing modulation II and III with the same frequency and magnitude are shown in Fig. 9b with THD 18.8% and Fig. 9c with THD 14.3%, respectively. From the Figures we can see that the output under the SEM method has lower THD than that of the maximum envelope modulation. If the method is applied to the 12-switch cells matrix converter, the THD can be further reduced. Figure 9 d with THD 12.9% is also with modulation III, output frequency is 35 Hz, and the

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