B-1

Appendix B: Reduction of Digital Logic

Principles of Computer Architecture

Miles Murdocca and Vincent Heuring

Appendix B: Reduction of Digital Logic

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

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Appendix B: Reduction of Digital Logic

Chapter Contents
B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction of Two-Level Expressions B.3 State Reduction

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

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Appendix B: Reduction of Digital Logic

Reduction (Simplification) of Boolean Expressions

It is usually possible to simplify the canonical SOP (or POS) forms. A smaller Boolean equation generally translates to a lower gate count in the target circuit. We cover three methods: algebraic reduction, Karnaugh map reduction, and tabular (Quine-McCluskey) reduction.

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-4

Appendix B: Reduction of Digital Logic

Reduced Majority Function Circuit

Compared with the AND-OR circuit for the unreduced majority function, the inverter for C has been eliminated, one AND gate has been eliminated, and one AND gate has only two inputs instead of three inputs. Can the function by reduced further? How do we go about it? A B C
Unreduced
A B C

Reduced

ABC

ABC F AB C ABC

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-5

Appendix B: Reduction of Digital Logic

The Algebraic Method

Consider the majority function, F. We apply the algebraic method to reduce F to its minimal two-level form:
F = ABC + ABC + ABC + ABC F = ABC + ABC + AB(C + C ) F = ABC + ABC + AB(1) F = ABC + ABC + AB F = ABC + ABC + AB + ABC F = ABC + AC( B + B) + AB F = ABC + AC + AB F = ABC + AC + AB + ABC F = BC( A + A) + AC + AB F = BC + AC + AB Distributive Property Complement Property Identity Property Idempotence Identity Property Complement and Identity Idempotence Distributive Complement and Identity
1999 M. Murdocca and V. Heuring

Principles of Computer Architecture by M. Murdocca and V. Heuring

B-6

Appendix B: Reduction of Digital Logic

The Algebraic Method

This majority circuit is functionally equivalent to the previous majority circuit, but this one is in its minimal two-level form:

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-7

Appendix B: Reduction of Digital Logic

Karnaugh Maps: Venn Diagram Representation of Majority Function

Each distinct region in the Universe represents a minterm. This diagram can be transformed into a Karnaugh Map.

ABC ABC ABC ABC

ABC

ABC ABC ABC B C

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-8

Appendix B: Reduction of Digital Logic

K-Map for Majority Function

Place a 1 in each cell that corresponds to that minterm. Cells on the outer edge of the map wrap around

Minterm Index 0 1 2 3 4 5 6 7

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 0 0 0 1 0 1 1 1

AB C 0
00 0-side

00

01
1

11 1

10

1-side

1 balance tips to the left or 1 A

right depending on whether there are more 0s or 1s.

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-9

Appendix B: Reduction of Digital Logic

Adjacency Groupings for Majority Function

AB C 0 1 1 00 01 11 1 1 1 10

F = BC + AC + AB
Principles of Computer Architecture by M. Murdocca and V. Heuring
1999 M. Murdocca and V. Heuring

B-10

Appendix B: Reduction of Digital Logic

Minimized AND-OR Majority Circuit

A B C

F = BC + AC + AB The K-map approach yields the same minimal two-level form as the algebraic approach.
Principles of Computer Architecture by M. Murdocca and V. Heuring
1999 M. Murdocca and V. Heuring

B-11

Appendix B: Reduction of Digital Logic

K-Map Groupings
Minimal grouping is on the left, non-minimal (but logically equivalent) grouping is on the right. To obtain minimal grouping, create smallest groups first.
AB 00 CD 00 01
2

01
1

11

10

AB CD 00
4

00

01
2

11

10

1 1 1 1 1 1 1
3

1
1 5

01 11
3

1 1 1

1 1 1
4

11 10

10

F = A BC + ACD + ABC + AC D
Principles of Computer Architecture by M. Murdocca and V. Heuring

F = BD + A BC + ACD + ABC + AC D
1999 M. Murdocca and V. Heuring

B-12

Appendix B: Reduction of Digital Logic

K-Map Corners are Logically Adjacent

AB CD 00 01 11 10 1 00 1 01 1 1 1 1 1 1 11 10 1

F=BCD + B D + AB
Principles of Computer Architecture by M. Murdocca and V. Heuring
1999 M. Murdocca and V. Heuring

B-13

Appendix B: Reduction of Digital Logic

K-Maps and Dont Cares

There can be more than one minimal grouping, as a result of dont cares.
AB 00 CD 00 01 11 10 d 1 1 1 1 1 01 11 10 d AB 00 CD 00 01 11 10 d 1 1 1 1 1 01 11 10 d

F= BC D + BD
Principles of Computer Architecture by M. Murdocca and V. Heuring

F= A B D + B D
1999 M. Murdocca and V. Heuring

B-14

Appendix B: Reduction of Digital Logic

Five-Variable K-Map
Visualize two 4-variable K-maps stacked one on top of the other; groupings are made in three dimensional cubes.
AB CDE 000 001 011 010 1 AB CDE 100 101 111 110

00 1

01

11

10

00 1

01

11

10

1 1 1

1 1

1 1

1 1

F = A C D E + A B DE + B E
Principles of Computer Architecture by M. Murdocca and V. Heuring
1999 M. Murdocca and V. Heuring

B-15

Appendix B: Reduction of Digital Logic

Six-Variable K-Map
Visualize four 4-variable K-maps stacked one on top of the other; groupings are made in three dimensional cubes.
DEF 000 001 011 010 1 1 1 1 ABC 000 001 011 010 1 DEF 100 101 111 110 ABC 000 001 011 010 1

DEF 000 001 011 010

ABC 100 101 111 110 1

DEF 100 101 111 110

ABC 100 101 111 110 1

G = B C EF + A B DE
Principles of Computer Architecture by M. Murdocca and V. Heuring
1999 M. Murdocca and V. Heuring

B-16

Appendix B: Reduction of Digital Logic

3-Level Majority Circuit

K-Kap Reduction results in a reduced two-level circuit (that is, AND followed by OR. Inverters are not included in the two-level count). Algebraic reduction can result in multi-level circuits with even fewer logic gates and fewer inputs to the logic gates.
A B C

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-17

Appendix B: Reduction of Digital Logic

Map-Entered Variables
An example of a K-map with a map-entered variable D.

AB C 0 1

00 D

01

11

10

F = BC + ABCD

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-18

Appendix B: Reduction of Digital Logic

Two Map-Entered Variables

A K-map with two map-entered variables D and E. F = BC + ACD + BE + ABCE

AB C 0 1

00 D

01 d 1

11 E 1

10 E

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-19

Appendix B: Reduction of Digital Logic

Truth Table with Dont Cares

A truth table representation of a single function with dont cares.
A B C D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F d 1 0 1 0 1 1 1 0 0 1 d 0 1 0 d
1999 M. Murdocca and V. Heuring

Principles of Computer Architecture by M. Murdocca and V. Heuring

B-20

Appendix B: Reduction of Digital Logic

Tabular (Quine-McCluskey) Reduction

Tabular reduction begins by grouping minterms for which F is nonzero according to the number of 1s in each minterm. Dont cares are considered to be nonzero. The next step forms a consensus (the logical form of a cross product) between each pair of adjacent groups for all terms that differ in only one variable.
Initial setup After first reduction A B C D 0 0 0 0 _ 0 _ 0 1 _ 1 1 0 0 _ _ 0 1 1 1 0 1 _ 1 0 _ 0 1 1 _ 0 1 1 1 1 _ (b) _ 1 1 1 1 1 1 _ _ 1 1 1 * * * After second reduction A B C D 0 _ _ 1 * _ _ 1 1 * _ 1 _ 1 * (c) A B C D 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 0 1 (a) 0 1 1 1 0 0 1 1 1 1

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

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Appendix B: Reduction of Digital Logic

Table of Choice
The prime implicants form a set that completely covers the function, although not necessarily minimally. A table of choice is used to obtain a minimal cover set.
Prime Implicants 0 00 _ * 0 11 _ * 1 01 _ 0 __ 1 _ _1 1 * _ 1_ 1
Principles of Computer Architecture by M. Murdocca and V. Heuring

Minterms 0001
1999 M. Murdocca and V. Heuring

0011

0101

0110

0111

1010

1101

B-22

Appendix B: Reduction of Digital Logic

Reduced Table of Choice

In a reduced table of choice, the essential prime implicants and the minterms they cover are removed, producing the eligible set. F = ABC + ABC + BD + AD

Eligible Set X Y Z 0 0 0_ 0 _ _1 _ _ 11

Minterms 0001 0011

Set 1 000_ __11

Set 2 0__1

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-23

Appendix B: Reduction of Digital Logic

Multiple Output Truth Table

The power of tabular reduction comes into play for multiple functions, in which minterms can be shared among the functions.
A B C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 F0 F1 F2 1 0 0 1 0 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1

Minterm m0 m1 m2 m3 m4 m5 m6 m7

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-24

Appendix B: Reduction of Digital Logic

Multiple Output Table of Choice

F0(A,B,C) = ABC + BC F1(A,B,C) = AC + AC + BC F2(A,B,C) = B
Prime Implicants F0 F1 F1 F2 F1,2 Minterms F0(A,B,C) F1(A,B,C) F2(A,B,C) m 2 m3 m6 m7

m0 m3 m 7 m 1 m 3 m4 m 6 m 7

* 0 00 * 0 _1 * 1 _0 * _ 1_ 1 1_

F0,1,2 * _ 1 1

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-25

Appendix B: Reduction of Digital Logic

Speed and Performance

The speed of a digital system is governed by:
the propagation delay through the logic gates and the propagation delay across interconnections.

We will look at characterizing the delay for a logic gate, and a method of reducing circuit depth using function decomposition.

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-26

Appendix B: Reduction of Digital Logic

Propagation Delay for a NOT Gate

(From Hamacher et. al. 1990)
Transition Time

+5V
A NOT gate input changes from 1 to 0

10%

(Fall Time) 50% (2.5V) 90% Propagation Delay (Latency) Transition Time

0V

+5V
The NOT gate output changes from 0 to 1 10%

(Rise Time) 50% (2.5V)

90%

0V Time
Principles of Computer Architecture by M. Murdocca and V. Heuring
1999 M. Murdocca and V. Heuring

B-27

Appendix B: Reduction of Digital Logic

MUX Decomposition
1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

1 0 0 1

00 01 10 11

BC+BC

F 0 1 1 0

B C 0 00 01 10 11

00 01 10 11

B C+ B C

A D

A B C D B C

F( ABCD) = ABC D + ABCD + ABC D + ABCD + ABC D + ABCD = ( BC + BC ) AD + ( BC + BC ) AD + ( BC + BC )

Principles of Computer Architecture by M. Murdocca and V. Heuring
1999 M. Murdocca and V. Heuring

B-28

Appendix B: Reduction of Digital Logic

OR-Gate Decomposition
Fanin affects circuit depth.
A BCD AB CD AB C D

A+B+C+D Initial high fan-in gate

(A + B) + (C + D) Balanced tree

Associative law of Boolean algebra: A + B + C + D = (A + B) + (C + D) (( A + B) + C) + D Degenerate tree

Principles of Computer Architecture by M. Murdocca and V. Heuring
1999 M. Murdocca and V. Heuring

B-29

Appendix B: Reduction of Digital Logic

State Reduction
Description of state machine M0 to be reduced.

Input Present state A B C D E 0 C/0 D/0 C/1 C/1 A/0

X 1 E/1 E/1 B/0 A/0 C/1

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-30

Appendix B: Reduction of Digital Logic

Distinguishing Tree
A next state tree for M0.
(ABCDE) 0 (CDA)(CC) (ABE)(CD) 0 1 Next states Distinguished states 1 (EEC)(BA) (ABE)(CD) 0 1

(CC)(C)(CC) (BA)(E)(BB) (AB)(E)(CD)* (AB)(E)(CD) 0 1

(AA)(C)(DC) (CC)(B)(EE) (AB)(E)(CD) (AB)(E)(CD)* 0 1

(DC)(A)(DD) (EE)(C)(EE) (CC)(C)(CC) (EE)(B)(AB) (AB)(E)(CD) (AB)(E)(CD)* 0 1 (CC)(C)(CC) (AB)(E)(AA) (AB)(E)(CD) 0 1 (CD)(A)(CC) (EE)(C)(EE)
Principles of Computer Architecture by M. Murdocca and V. Heuring
1999 M. Murdocca and V. Heuring

B-31

Appendix B: Reduction of Digital Logic

Reduced State Table

A reduced state table for machine M1.

Input Current state AB: A' CD: B' E: C' 0 B'/0 B'/1 A'/0

X 1 C'/1 A'/0 B'/1

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-32

Appendix B: Reduction of Digital Logic

The State Assignment Problem

Two state assignments for machine M2.

Input P.S. A B C D 0 B/1 C/0 C/0 B/1

X 1 A/1 D/1 D/0 A/0

Input S0S1 A: 00 B: 01 C: 10 D: 11 0 01/1 10/0 10/0 01/1

X 1 00/1 11/1 11/0 00/0

Input S 0S 1 A: 00 B: 01 C: 11 D: 10 0 01/1 11/0 11/0 01/1

X 1 00/1 10/1 10/0 00/0

Machine M2

State assignment SA0

State assignment SA1

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-33

Appendix B: Reduction of Digital Logic

State Assignment SA0

Boolean equations for machine M2 using state assignment SA0.
X S0S1 00 01 11 10 1 1 0 1 X S0S1 00 01 11 10 1 1 0 1 1 1 X S0S1 00 01 11 10 1 0 1 1 1 1

S0 = S0S1 + S0S1

S1 = S0S1X + S0S1X + S0S1X + S0S1X

Z = S0S1 + S0X + S0S1X

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-34

Appendix B: Reduction of Digital Logic

State Assignment SA1

Boolean equations for machine M2 using state assignment SA1.

X S0S1 00 01 11 10
S0 = S 1

X 0 1 S0S1 00 01 11 10 0 1 1 1 1
S1 = X

X 1 S0S1 00 01 11 10 1 0 1 1 1 1

1 1

1 1

Z = S1 X + S0 X

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-35

Appendix B: Reduction of Digital Logic

Sequence Detector State Transition Diagram 0/0

0/0

D
1/0 0/0

B
0/0 1/0

E
1/1 0/0

A
0/0 1/0

F
0/1

1/1

C
Input: 011011100 1/0 Output: 0 0 1 1 1 1 0 1 0 Time: 0 1 2 3 4 5 6 7 8
Principles of Computer Architecture by M. Murdocca and V. Heuring

G
1/0
1999 M. Murdocca and V. Heuring

B-36

Appendix B: Reduction of Digital Logic

Sequence Detector State Table

Input Present state A B C D E F G 0 B/0 D/0 F/0 D/0 F/0 D/0 F/1

X 1 C/0 E/0 G/0 E/0 G/1 E/1 G/0

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-37

Appendix B: Reduction of Digital Logic

Sequence Detector Reduced State Table

Input Present state A: A' BD: B' C: C' E: D' F: E' G: F' 0 B'/0 B'/0 E'/0 E'/0 B'/0 E'/1 X 1 C'/0 D'/0 F'/0 F'/1 D'/1 F'/0

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-38

Appendix B: Reduction of Digital Logic

Sequence Detector State Assignment

Input Present state
S2S1S0

X 0
S2S1S0Z

1
S2S1S0Z

A': B': C': D': E': F':

000 001 010 011 100 101

001/0 001/0 100/0 100/0 001/0 100/1

010/0 011/0 101/0 101/1 011/1 101/0

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-39

Appendix B: Reduction of Digital Logic

Excitation Tables
In addition to the D flip-flop, the S-R, J-K, and T flip-flops are used as delay elements in finite state machines. A Master-Slave J-K flip-flop is shown below.

J CLK K

J Q K Q

Circuit

Symbol

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-40

Appendix B: Reduction of Digital Logic

Sequence Detector K-Maps

S2S1

K-map reduction of next state and output functions for sequence detector.

S0X 00 01 11 10

00 1

01

11 d

10 1 1 1

S2S1 S0X 00 01 11 10

00

01

11 d

10

1 1 1 1

d d d

1 1

d d d

S 0 = S 2 S1 X + S 0 X + S2S0 + S1X

S1 = S2S1X + S2S0X

S2S1 00 S0X 00 01 11 10

01 1 1 1 1

11 d d d d

10

S2S1 00 S0X 00 01

01

11 d d

10

1 1

11 10

d d 1

S2 = S2S0 + S1
Principles of Computer Architecture by M. Murdocca and V. Heuring

Z = S2S0X + S1S0X + S2S0X

1999 M. Murdocca and V. Heuring

B-41

Appendix B: Reduction of Digital Logic

Clocked T Flip-Flop
Logic diagram and symbol for a T flip-flop.

1 T

Q T

K Q Circuit

Q Symbol

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-42
X

Appendix B: Reduction of Digital Logic

Sequence Detector Circuit

CLK

D Q S0 Q

D Q S1 Q

D Q S2 Q

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-43

Appendix B: Reduction of Digital Logic

Excitation Tables
Each table shows the settings that must be applied at the inputs at time t in order to change the outputs at time t+1.
Qt Qt+1 S-R flip-flop 0 0 1 1 0 1 0 1 S 0 1 0 0 R 0 0 1 0 D flip-flop Qt Qt+1 0 0 1 1 0 1 0 1 D 0 1 0 1

Qt Qt+1 J-K flip-flop 0 0 1 1 0 1 0 1

J K 0 1 d d d d 1 0 T flip-flop

Qt Qt+1 0 0 1 1 0 1 0 1

T 0 1 1 0

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-44

Appendix B: Reduction of Digital Logic

Serial Adder
Time (t) 4 3 2 1 0 01100 01110 X Z Serial Y Adder Cout Cin 4 3 2 1 0 Time (t) 11010

No carry state xi yi 01/1 00/0 zi 10/1

XY

Carry state 11/0 01/0

A
00/1

B
11/1

10/0

State transition diagram, state table, and state assignment for a serial adder.

Input Present state A B Next state 00 A/0 A/1 01 A/1 B/0 Output

10 A/1 B/0

11 B/0 B/1

Present state (St) A:0 B:1

Input 00 0/0 0/1 01 0/1 1/0

XY 10 0/1 1/0 11 1/0 1/1

1999 M. Murdocca and V. Heuring

Principles of Computer Architecture by M. Murdocca and V. Heuring

B-45

Appendix B: Reduction of Digital Logic

Serial Adder Next-State Functions

Truth table showing next-state functions for a serial adder for D, S-R, T, and J-K flip-flops. Shaded functions are used in the example.
Present State (Set) (Reset)

X Y St 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

D 0 0 0 1 0 1 1 1

S 0 0 0 0 0 0 1 0

R 0 1 0 0 0 0 0 0

T 0 1 0 0 0 0 1 0

J 0 d 0 d 0 d 1 d

K d 1 d 0 d 0 d 0

Z 0 1 1 0 1 0 0 1

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-46

Appendix B: Reduction of Digital Logic

J-K Flip-Flop Serial Adder Circuit

X Y X Y CLK J Q S K Q

X Y Y Z X

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-47

Appendix B: Reduction of Digital Logic

D Flip-Flop Serial Adder Circuit

X Y X DQ S Q CLK

X Y Y Z X

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-48

Appendix B: Reduction of Digital Logic

Majority Finite State Machine

1/0 0/0 0/0

D
1/0 00_ 01_

B
0/0 Input History ___ 0__ 0/0 0/0 1/0 Input: 0 1 1 1 0 0 1 0 1 Output: 0 0 1 0 0 0 0 0 1 Time: 0 1 2 3 4 5 6 7 8 1__ 1/1 1/1

F
0/0 1/0 10_ 11_

C
0/1 1/1

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-49

Appendix B: Reduction of Digital Logic

Majority FSM State Table

(a) State table for majority FSM; (b) partitioning; (c) reduced state table.
Input P.S. A B C D E F G 0 B/0 D/0 F/0 A/0 A/0 A/0 A/1 (a) Input 1 C/0 E/0 G/0 A/0 A/1 A/1 A/1 P0 = (ABCDEFG) P1 = (ABCD)(EF)(G) P2 = (AD)(B)(C)(EF)(G) P3 = (A)(B)(C)(D)(EF)(G) P4 = (A)(B)(C)(D)(EF)(G) (b) P.S. A: A' B: B' C: C' D: D' EF: E' G: F' (c) 0 B'/0 D'/0 E'/0 A'/0 A'/0 A'/1

X 1 C'/0 E'/0 F'/0 A'/0 A'/1 A'/ 1

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-50

Appendix B: Reduction of Digital Logic

Majority FSM State Assignment

(a) State assignment for reduced majority FSM using D flip-flops; and (b) using T flip-flops.

Input P.S.
S2S1S0

X 0
S2S1S0Z

Input 1 P.S.
S2S1S0

X 0
T2T1T0Z

1
T2T1T0Z

S2S1S0Z

A': B': C': D': E': F':

000 001 010 011 100 101

001/0 011/0 100/0 000/0 000/0 000/1 (a)

010/0 100/0 101/0 000/0 000/1 000/1

A': B': C': D': E': F':

000 001 010 011 100 101

001/0 000/0 110/0 011/0 100/0 101/1 (b)

010/0 010/0 111/0 011/0 100/1 101/1

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

B-51

Appendix B: Reduction of Digital Logic

Majority FSM Circuit

0 0 1 0 0 0 0 0

000 001 010 011 100 101 110 111

x x 1 D Q T 2 Q 1 0 0 0 0

000 001 010 011 100 101 110 111

x x 0 x 1 0 1 0 0

000 001 010 011 100 101 110 111

0 0 0 D Q T 0 Q 0 x 1 0 0

000 001 010 011 100 101 110 111

D Q T 1 Q

CLK

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring