Giao Trinh VI Xu Ly 8051

B
KHOA CNG NGH I NT MN I N T CNG NGHI P
GI O T R N H
BIN SO N: PH M QUANG TR
TP. H
CH MINH 6 - 2006
KHOA CNG NGH I NT B MN I N T CNG NGHI P
GIO TRNH VI X
Chng 1: Gi i thi u chung v b vi x l.
Tr ng H Cng nghi p Tp.HCM.
CHNG 1 GI I THI U CHUNG V B

I. S PHT TRI N C A CC B 1. Th h 1 (1971 - 1973): VI X L:
VI X
c i m chung c a cc vi x l th h ny: Bus d li u: 4 bit. Bus a ch : 12 bit. Cng ngh ch t o: PMOS. T c th c hi n l nh: 10 60 s/l nh v i fCLOCK = 0,1 0,8 MHz.
M t s b vi x l c trng cho th h ny: 4040 (Intel), PPS-4 (Rockwell International), 2. Th h 2 (1974 - 1977): c i m chung c a cc vi x l th h ny: Bus d li u: 8 bit. Bus a ch : 16 bit. Cng ngh ch t o: NMOS ho c CMOS. T c th c hi n l nh: 1 8 s/l nh v i fCLOCK = 1 5 MHz.
M t s b vi x l c trng cho th h ny: 6502 (Mos Technology), 6800/6809 (Motorola), 8080/8085 (Intel), Z80 (Zilog), 3. Th h 3 (1978 - 1982): c i m chung c a cc vi x l th h ny: Bus d li u: 16 bit. Bus a ch : 20 - 24 bit. Cng ngh ch t o: HMOS. T c th c hi n l nh: 0,1 1 s/l nh v i fCLOCK = 5 10 MHz.
M t s b vi x l c trng cho th h ny: 68000 / 68010 (Motorola), 8086 / 80186 / 80286 (Intel), 4. Th h 4 (1983 - nay): c i m chung c a cc vi x l th h ny: Bus d li u: 32 - 64 bit. Bus a ch : 32 bit. Cng ngh ch t o: HCMOS. T c th c hi n l nh: 0,01 0,1 s v i fCLOCK = 20 100 MHz.
M t s b vi x l c trng cho th h ny: 68020 / 68030 / 68040 / 68060 (Motorola), 80386 / 80486 / Pentium (Intel), II. S KH I C A M T H VI X L: nh ngha h vi x l: Kh nng c l p trnh thao tc trn cc d li u m khng c n s can thi p c a con ng i. Giao trnh Vi x ly. 1 Bien soan: Pham Quang Tr
Chng 1: Gi i thi u chung v b vi x l. Kh nng lu tr v ph c h i d li u.
T ng qut, h vi x l g m: Ph n c ng (Hardware): cc thi t b ngo i vi giao ti p v i con ng i. Ph n m m (Software): chng trnh x l d li u.
CPU (Central Processing Unit): n v x l trung tm. RAM (Random Access Memory): b nh truy xu t ng u nhin. ROM (Read Only Memory): b nh ch c. Interface Circuitry: m ch i n giao ti p. Peripheral Devices (Input): cc thi t b ngo i vi (thi t b nh p). Peripheral Devices (Output): cc thi t b ngo i vi (thi t b xu t). Address bus: bus a ch . Data bus: bus d li u. Control bus: bus i u khi n. III. N V X L TRUNG TM: CPU ng vai tr ch o trong h vi x l, n qu n l t t c cc ho t ng c a h v th c hi n t t c cc thao tc trn d li u. CPU l m t vi m ch i n t c tch h p cao. Khi ho t ng, CPU c m l nh c ghi d i d ng cc bit 0 v bit 1 t b nh , sau n s th c hi n gi i m cc l nh ny thnh dy cc xung i u khi n tng ng v i cc thao tc trong l nh i u khi n cc kh i khc th c hi n t ng b c cc thao tc v t t o ra cc xung i u khi n cho ton h .
Giao trnh Vi x ly.
Bien soan: Pham Quang Tr
IR (Instruction Register): thanh ghi l nh. PC (Program Counter / Instruction Pointer): b m chng trnh / con tr l nh. Instruction decode and control unit: n v gi i m l nh v i u khi n. ALU (Arithmetic and Logic Unit): n v s h c v logic. Registers: cc thanh ghi. Tm l i, khi ho t ng CPU s th c hi n lin t c 2 thao tc: tm n p l nh v gi i m th c hi n l nh. Thao tc tm n p l nh: - N i dung c a thanh ghi PC c CPU a ln bus a ch (1). - Tn hi u i u khi n c (Read) chuy n sang tr ng thi tch c c (2). - M l nh (Opcode) t b nh c a ln bus d li u (3). - M l nh c chuy n vo trong thanh ghi IR trong CPU (4). - N i dung c a thanh ghi PC tng ln m t n v chu n b tm n p l nh k ti p t b nh .
Thao tc gi i m th c hi n l nh: - M l nh t thanh ghi IR c a vo n v gi i m l nh v i u khi n. - n v gi i m l nh v i u khi n s th c hi n gi i m opcode v t o ra cc tn hi u i u khi n vi c xu t nh p d li u gi a ALU v cc thanh ghi (Registers). - Cn c trn cc tn hi u i u khi n ny, ALU th c hi n cc thao tc c xc nh. M t chu i cc l nh (Opcode) k t h p l i v i nhau th c hi n m t cng vi c c ngha c g i l chng trnh (Program) hay ph n m m (Software). IV. B NH BN D N: B nh bn d n l m t b ph n khc r t quan tr ng c a h vi x l, cc chng trnh v d li u u c lu gi trong b nh . B nh bn d n trong h vi x l g m: ROM: b nh chng trnh lu gi chng trnh i u khi n ho t ng c a ton h th ng. RAM: b nh d li u lu gi d li u, m t ph n chng trnh i u khi n h th ng, cc ng d ng v k t qu tnh ton. Giao trnh Vi x ly. 3 Bien soan: Pham Quang Tr
S l c v c u trc v phn lo i ROM RAM: ROM (Read Only Memory): b nh ch c, thng tin trong ROM s khng b m t i ngay c khi ngu n i n cung c p cho ROM khng cn. - C u trc ROM:
Phn lo i m t s lo i ROM: o MROM (Mask ROM): ROM m t n . o PROM (Programmable ROM): ROM l p trnh c. o EPROM (Eraseable PROM): ROM l p trnh v xa c. UV-EPROM (Ultra Violet EPROM): ROM xa b ng tia c c tm. EEPROM (Electric EPROM): ROM l p trnh v xa b ng tn hi u i n. Flash ROM: ROM l p trnh v xa b ng tn hi u i n. RAM (Random Access Memory): b nh truy xu t ng u nhin (b nh ghi c), thng tin trong RAM s b m t i khi ngu n i n cung c p cho RAM khng cn.. - C u trc RAM:
Phn lo i m t s lo i RAM: o DRAM (Dynamic RAM): RAM ng o SRAM (Static RAM): RAM tnh
Cch xc nh dung l ng b nh bn d n 8 bit s d ng cho chip vi i u khi n 8051 nh sau: D a vo s l ng chn a ch : Dung l ng = 2N , v i N l s ng a ch c a b nh . V d : B nh bn d n 8 bit c 10 ng a ch . Cho bi t dung l ng c a b nh l bao nhiu? N = 10 Dung l ng = 210 = 1024 = 1 KB
Giao trnh Vi x ly.
Chng 1: Gi i thi u chung v b vi x l. D a vo m s c a b nh : M s : XX YYYY
XX: lo i b nh 27: UV-EPROM 28: EEPROM 61,62: SRAM 40,41: DRAM YYYY: dung l ng b nh Dung l ng = YYYY (Kbit) ho c Dung l ng = YYYY / 8 (KB)
V d : B nh c m s 27256, dung l ng c a b nh l bao nhiu ? 27 B nh UV-EPROM 256 Dung l ng = 256 (Kbit) = 32 (KB) V. CC THI T B NGO I VI (CC THI T B XU T NH P): M ch i n giao ti p (Interface Circuitry) v cc thi t b xu t nh p hay thi t b ngo i vi (Peripheral Devices) t o ra kh nng giao ti p gi a h vi x l v i th gi i bn ngoi. B ph n giao ti p gi a bus h th ng c a h vi x l v i cc th gi i bn ngoi th ng c g i l c ng (Port). Nh v y ty theo t ng lo i thi t b giao ti p m ta c cc c ng nh p (Input) l y thng tin t ngoi vo h v cc c ng xu t (Output) a thng tin t trong h ra ngoi. T ng qut, ta c 3 lo i thi t b xu t nh p sau: Thi t b lu tr l n: bng t , a t , a quang, Thi t b giao ti p v i con ng i: mn hnh, bn phm, my in, Thi t b i u khi n / ki m tra: cc b kch thch, cc b c m bi n,
VI. H TH NG BUS: Bus l t p h p cc ng dy mang thng tin c cng ch c nng. Vi c truy xu t thng tin t i m t m ch i n xung quanh CPU th n s d ng 3 lo i bus: bus a ch , bus d li u v bus i u khi n. CPU s d ng h th ng bus ny th c hi n cc thao tc c (READ) v ghi (WRITE) thng tin gi a CPU v i b nh ho c cc thi t b ngo i vi. Bus a ch (Address bus): - chuy n t i thng tin c a cc bit a ch . - L lo i bus 1 chi u (CPU MEM hay I/O). - xc nh b nh ho c thi t b ngo i vi m CPU c n trao i thng tin. - xc nh dung l ng b nh ho c ngo i vi m CPU c kh nng truy xu t. Bus d li u (Data bus): - chuy n t i thng tin c a cc bit d li u. - L lo i bus 2 chi u (CPU MEM hay I/O). - xc nh s bit d li u m CPU c kh nng x l cng m t lc. Bus i u khi n (Control bus): - chuy n t i thng tin c a cc bit i u khi n (m i ng dy l m t tn hi u i u khi n khc nhau). - L lo i bus 1 chi u (CPU MEM-I/O ho c MEM-I/O CPU). - i u khi n cc kh i khc trong h v nh n tn hi u i u khi n t cc kh i ph i h p ho t ng.
Giao trnh Vi x ly.
Chng 1: Gi i thi u chung v b vi x l. VII. VI X L VI I U KHI N:
phn bi t b vi x l v b vi i u khi n ta c th d a trn cc y u t nh sau: Y u t phn lo i CPU ROM RAM M ch giao ti p n i ti p M ch giao ti p song song M ch i u khi n ng t Cc m ch i u khi n khc ng d ng l n, tnh ton ph c t p ng d ng nh , tnh ton n gi n Cc ki u nh a ch di t d li u x l Vi x l (Microprocessor) X Vi i u khi n (Microcontroller) X X X X X X X X X Nhi u Byte, Word, Double word, t Bit, Byte
C u trc ph n c ng (Hardware architecture)
Cc ngd ng (Applications) Cc c trng c a t p l nh (Instruction set feature)
VIII. MINH H A KI N TRC C A M T H VI I U KHI N:
WDT (Watch-Dog Timer): B nh th i Watch-Dog. OSC., OSC/N (Oscillator): B dao ng (N: h s chia t n). Timer: B nh th i. A/D (Analog/Digital): B bi n i tn hi u tng t /s . SFR Registers (Special Function Register): Cc thanh ghi ch c nng c bi t. RAM Memory: B nh d li u. Giao trnh Vi x ly. 6 Bien soan: Pham Quang Tr
Chng 1: Gi i thi u chung v b vi x l. Program Memory: B nh chng trnh. EEPROM: B nh EEPROM. I/O Ports: Cc port xu t/nh p. Instruction Decoder: B gi i m l nh. ALU: n v logic v s h c. Accumulator: Thanh ghi tch ly. Control Logic: i u khi n logic. Program Counter: B m chng trnh. Instructions/Addresses: Cc l nh / a ch . IX. L A CH N B VI I U KHI N KHI THI T K :
C b n h vi i u khi n thng d ng trn th tr ng hi n nay l: 68xxx c a Motorola, 80xxx c a Intel, Z8xx c a Zilog v PIC16xxx c a Microchip Technology. M i lo i vi i u khi n trn u c m t t p l nh v thanh ghi ring nn chng khng tng thch l n nhau. V y khi ta ti n hnh thi t k m t h th ng s d ng vi i u khi n th ta c n d a trn nh ng tiu chu n no? C ba tiu ch n chnh: Tiu chu n th nh t l: p ng yu c u tnh ton m t cch hi u qu v kinh t . Do v y, tr c tin ta c n ph i xem xt b vi i u khi n 8 bit, 16 bit hay 32 bit l thch h p nh t. M t s tham s k thu t c n c cn nh c khi ch n l a l: o T c : t c l n nh t m vi i u khi n h tr l bao nhiu. o Ki u IC: l ki u 40 chn DIP, QFP hay l ki u ng v khc (DIP: v d ng hai hng chn, QFP: v vung d t). Ki u ng v r t quan tr ng khi c yu c u v khng gian, ki u l p rp v t o m u th cho s n ph m cu i cng. o Cng su t tiu th : l m t tiu chu n c n c bi t lu n u s n ph m dng pin ho c i n p l i. o Dung l ng b nh ROM v RAM tch h p s n trn chip. o S chn vo/ra v b nh th i trn chip. o Kh nng d dng nng cao hi u su t ho c gim cng su t tiu th . o Gi thnh trn m t n v khi mua s l ng l n. V y l v n c nh h ng n gi thnh cu i cng c a s n ph m. Tiu chu n th hai l: C s n cc cng c pht tri n ph n m m, ch ng h n nh cc chng trnh m ph ng, trnh bin d ch, trnh h p d ch v g r i. Tiu chu n th ba l: Kh nng p ng v s l ng hi n t i cng nh tng lai. i v i m t s nh thi t k th tiu chu n ny th m ch cn quan tr ng hn c hai tiu chu n trn.
Giao trnh Vi x ly.
GIO TRNH VI X
Chng 2: Ph n c ng chip vi i u khi n 8051.
CHNG 2 PH N C NG CHIP VI I U KHI N 8051

I. T NG QUT: 1. Gi i thi u chung: MCS-51 l h vi i u khi n c a hng Intel. Vi m ch t ng qut c a h MCS-51 l chip 8051. Chip 8051 c m t s c trng c b n sau: - B nh chng trnh bn trong: 4 KB (ROM). - B nh d li u bn trong: 128 byte (RAM). - B nh chng trnh bn ngoi: 64 KB (ROM). - B nh d li u bn ngoi: 64 KB (RAM). - 4 port xu t nh p (I/O port) 8 bit. - 2 b nh th i 16 bit. - M ch giao ti p n i ti p. - B x l bit (thao tc trn cc bit ring l ). - 210 v tr nh c nh a ch , m i v tr 1 bit. - Nhn / Chia trong 4 s. Ngoi ra, trong h MCS-51 cn c m t s chip vi i u khi n khc c c u trc tng ng nh: Chip 8031 8032 8051 8052 8751 8752 8951 8952 2.1 ROM trong 0 KB 0 KB 4 KB PROM 8 KB PROM 4 KB UV-EPROM 8 KB UV-EPROM 4 KB FLASH ROM 8 KB FLASH ROM RAM trong 128 byte 256 byte 128 byte 256 byte 128 byte 256 byte 128 byte 256 byte B nh th i 2 3 2 3 2 3 2 3
2. Cc phin b n c a chip vi i u khi n 8051: B vi i u khi n 8031: 8031 l m t phin b n khc c a h 8051. Chip ny th ng c coi l 8051 khng c ROM trn chip. c th dng c chip ny c n ph i b sung thm ROM ngoi ch a chng trnh c n thi t cho 8031. 8051 c chng trnh c ch a ROM trn chip b gi i h n n 4KB, cn ROM ngoi c a 8031 th c th ln n 64KB. Tuy nhin, c th truy c p h t b nh ROM ngoi th c n dng thm hai c ng (Port 0 v Port 2) , do v y ch cn l i c hai c ng (Port 1 v Port 3) s d ng. Nh m kh c ph c v n ny, chng ta c th b sung thm c ng vo/ra cho 8031. 2.2 B vi i u khi n 8052: 8052 l m t phin b n c a h 8051. 8052 c t t c cc thng s k thu t c a 8051, ngoi ra cn c thm 128 byte RAM, 4KB ROM v m t b nh th i n a. Nh v y, 8052 c t ng c ng 256 byte RAM, 8KB ROM v ba b nh th i.
Gio trnh Vi x l.
Bin so n: Ph m Quang Tr
Chng 2: Ph n c ng chip vi i u khi n 8051. c tnh k thu t ROM trn chip (KB) RAM trn chip (byte) B nh th i Chn vo/ra C ng n i ti p Ngu n ng t 8031 0 128 2 32 1 5
Tr ng H Cng nghi p Tp.HCM. 8051 4 128 2 32 1 5 8052 8 256 3 32 1 6
Nh b ng thng s trn ta th y 8051 l m t tr ng h p ring c a 8052. M i chng trnh vi t cho 8051 u c th ch y c trn 8052 nhng i u ng c l i c th l khng ng. 2.3 B vi i u khi n 8751: Chip 8751 ch c 4KB b nh UV-EPROM trn chip. s d ng chip ny c n ph i c thi t b l p trnh PROM v thi t b xo UV-EPROM. Do ROM trn chip c a 8751 l UV-EPROM, nn c n ph i m t kho ng 20 pht xo 8751 tr c khi c l p trnh. V y l qu trnh m t nhi u th i gian nn nhi u nh s n xu t cho ra phin b n Flash ROM v UV-RAM. 2.4 B vi i u khi n AT8951 c a Atmel Corporation: AT8951 l phin b n 8051 c ROM trn chip l b nh Flash. Phin b n ny r t thch h p cho cc ng d ng nhanh v b nh Flash c th c xa trong vi giy. D nhin l dng AT8951 c n ph i c thi t b l p trnh PROM h tr b nh Flash nhng khng c n n thi t b xa ROM v b nh Flash c xa b ng thi t b l p trnh PROM. ti n s d ng, hi n nay hng Atmel ang nghin c u m t phin b n c a AT8951 c th c l p trnh qua c ng COM c a my tnh PC v nh v y s khng c n n thi t b l p trnh PROM. K hi u AT89C51 AT89LV51 AT89C1051 AT89C2051 AT89C52 AT89LV52 2.5 ROM 4KB 4KB 1KB 2KB 8KB 8KB RAM 128 128 64 128 256 256 I/O 32 32 15 15 32 32 Timer 2 2 1 2 3 3 Ng t 5 5 3 5 6 6 Vcc 5V 3V 3V 3V 5V 3V S chn IC 40 40 20 20 40 40
B vi i u khi n DS5000 c a Dallas Semiconductor:
M t phin b n ph bi n khc n a c a 8051 l DS5000 c a hng Dallas Semiconductor. B nh ROM trn chip c a DS5000 l NV-RAM. DS5000 c kh nng n p chng trnh vo ROM trn chip trong khi n v n trong h th ng m khng c n ph i l y ra. Cch th c hi n l dng qua c ng COM Gio trnh Vi x l. 9 Bin so n: Ph m Quang Tr
c a my tnh PC. y l m t i m m nh r t c a chu ng. Ngoi ra, NV-RAM cn c u vi t l cho php thay i n i dung RAM theo t ng byte m khng c n ph i xa h t tr c khi l p trnh nh b nh EPROM. K hi u DS5000-8 DS5000-32 DS5000T-8 DS5000T-32 ROM 8KB 32KB 8KB 32KB RAM 128 128 128 128 I/O 32 32 32 32 Timer 2 2 2 2 Ng t 6 6 6 6 Vcc 5V 5V 5V 5V S chn IC 40 40 40 40
i m c bi t l cc chip c ch T theo sau k hi u 5000 c ngha l chip c thi t k thm m t ng h th i gian th c (RTC: Real Time Clock) bn trong. Lu ng h th i gian th c RTC hon ton khc v i b nh th i Timer. RTC t o v lu gi th i gian c a ngy (gi /pht/giy) v ngy thng (ngy/thng/nm) trn th c t ngay c khi khng c ngu n cung c p. 2.6 B vi i u khi n P89V51xx c a Philips Corporation: y l m t phin b n c i ti n s d ng CPU l b vi i u khi n 80C51 v i nhi u tnh nng v t tr i: dung l ng ROM/RAM trn chip r t l n, 3 Timer 16 bit + 1 Watch-dog Timer, 2 thanh ghi DPTR, 8 ngu n ng t, PWM (Pulse Width Modulator), SPI (Serial Peripheral Interface) v c bi t l b nh chng trnh trn chip c tnh nng ISP (In-System Programming) v IAP (In-Application Programming), II. CC CHN C A CHIP 8051: 1. S kh i v ch c nng cc kh i c a chip 8051:
Gio trnh Vi x l.
10
- CPU (Central Processing Unit): n v x l trung tm tnh ton v i u khi n qu trnh ho t ng c a h th ng. - OSC (Oscillator): M ch dao ng t o tn hi u xung clock cung c p cho cc kh i trong chip ho t ng. - Interrupt control: i u khi n ng t nh n tn hi u ng t t bn ngoi (INT0\, INT1\), t b nh th i (Timer 0, Timer 1) v t c ng n i ti p (Serial port), l n l t a cc tn hi u ng t ny n CPU x l. - Other registers: Cc thanh ghi khc lu tr d li u c a cc port xu t/nh p, tr ng thi lm vi c c a cc kh i trong chip trong su t qu trnh ho t ng c a h th ng. - RAM (Random Access Memory): B nh d li u trong chip lu tr cc d li u. - ROM (Read Only Memory): B nh chng trnh trong chip lu tr chng trnh ho t ng c a chip. - I/O ports (In/Out ports): Cc port xu t/nh p i u khi n vi c xu t nh p d li u d i d ng song song gi a trong v ngoi chip thng qua cc port P0, P1, P2, P3. - Serial port: Port n i ti p i u khi n vi c xu t nh p d li u d i d ng n i ti p gi a trong v ngoi chip thng qua cc chn TxD, RxD. - Timer 0, Timer 1: B nh th i 0, 1 dng nh th i gian ho c m s ki n ( m xung) thng qua cc chn T0, T1. - Bus control: i u khi n bus i u khi n ho t ng c a h th ng bus v vi c di chuy n thng tin trn h th ng bus. - Bus system: H th ng bus lin k t cc kh i trong chip l i v i nhau. 2. S chn v ch c nng cc chn c a chip 8051:
Gio trnh Vi x l.
11
Chng 2: Ph n c ng chip vi i u khi n 8051. 2.1. -
Port 0: Port 0 (P0.0 P0.7) c s chn t 32 39. Port 0 c hai ch c nng: Port xu t nh p d li u (P0.0 - P0.7) khng s d ng b nh ngoi. Bus a ch byte th p v bus d li u a h p (AD0 AD7) c s d ng b nh ngoi. Lu : Khi Port 0 ng vai tr l port xu t nh p d li u th ph i s d ng cc i n tr ko ln bn ngoi. ch m c nh (khi reset) th cc chn Port 0 (P0.0 - P0.7) c c u hnh l port xu t d li u. Mu n cc chn Port 0 lm port nh p d li u th c n ph i l p trnh l i, b ng cch ghi m c logic cao (m c 1) n t t c cc bit c a port tr c khi b t u nh p d li u t port (v n ny c trnh by ph n k ti p). - Khi l p trnh cho ROM trong chip th Port 0 ng vai tr l ng vo c a d li u (D0 D7) (xem sch H vi i u khi n 8051 trang 333-352). Port 1: Port 1 (P1.0 P1.7) c s chn t 1 8. Port 1 c m t ch c nng: Port xu t nh p d li u (P1.0 P1.7) s d ng ho c khng s d ng b nh ngoi. ch m c nh (khi reset) th cc chn Port 1 (P1.0 P1.7) c c u hnh l port xu t d li u. Mu n cc chn Port 1 lm port nh p d li u th c n ph i l p trnh l i, b ng cch ghi m c logic cao (m c 1) n t t c cc bit c a port tr c khi b t u nh p d li u t port (v n ny c trnh by ph n k ti p). - Khi l p trnh cho ROM trong chip th Port 1 ng vai tr l ng vo c a a ch byte th p (A0 A7) (xem sch H vi i u khi n 8051 trang 333-352). Port 2: - Port 2 (P2.0 P2.7) c s chn t 21 28. - Port 2 c hai ch c nng: Port xu t nh p d li u (P2.0 P2.7) khng s d ng b nh ngoi. Bus a ch byte cao (A8 A15) c s d ng b nh ngoi. ch m c nh (khi reset) th cc chn Port 2 (P2.0 P2.7) c c u hnh l port xu t d li u. Mu n cc chn Port 2 lm port nh p d li u th c n ph i l p trnh l i, b ng cch ghi m c logic cao (m c 1) n t t c cc bit c a port tr c khi b t u nh p d li u t port (v n ny c trnh by ph n k ti p). - Khi l p trnh cho ROM trong chip th Port 2 ng vai tr l ng vo c a a ch byte cao (A8 A11) v cc tn hi u i u khi n (xem sch H vi i u khi n 8051 trang 333-352). Port 3: Port 3 (P3.0 P3.7) c s chn t 10 17. Port 3 c hai ch c nng: Port xu t nh p d li u (P3.0 P3.7) khng s d ng b nh ngoi ho c cc ch c nng c bi t. Cc tn hi u i u khi n c s d ng b nh ngoi ho c cc ch c nng c bi t. ch m c nh (khi reset) th cc chn Port 3 (P3.0 P3.7) c c u hnh l port xu t d li u. Mu n cc chn Port 3 lm port nh p d li u th c n ph i l p trnh l i, b ng cch ghi m c logic cao (m c 1) n t t c cc bit c a port tr c khi b t u nh p d li u t port (v n ny c trnh by ph n k ti p). Gio trnh Vi x l. 12 Bin so n: Ph m Quang Tr 2.4. 2.3. 2.2.
- Khi l p trnh cho ROM trong chip th Port 3 ng vai tr l ng vo c a cc tn hi u i u khi n (xem sch H vi i u khi n 8051 trang 333-352). - Ch c nng c a cc chn Port 3: Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 2.5. Tn RxD TxD INT0\ INT1\ T0 T1 WR\ RD\ a ch bit B0H B1H B2H B3H B4H B5H B6H B7H Ch c nng Chn nh n d li u c a port n i ti p. Chn pht d li u c a port n i ti p. Ng vo ng t ngoi 0. Ng vo ng t ngoi 1. Ng vo c a b nh th i/ m 0. Ng vo c a b nh th i/ m 1. i u khi n ghi vo RAM ngoi. i u khi n c t RAM ngoi.
Chn PSEN\: - PSEN (Program Store Enable): cho php b nh chng trnh, chn s 29. - Ch c nng: L tn hi u cho php truy xu t ( c) b nh chng trnh (ROM) ngoi. L tn hi u xu t, tch c c m c th p. PSEN\ = 0 trong th i gian CPU tm - n p l nh t ROM ngoi. PSEN\ = 1 CPU s d ng ROM trong (khng s d ng ROM ngoi). - Khi s d ng b nh chng trnh bn ngoi, chn PSEN\ th ng c n i v i chn OE\ c a ROM ngoi cho php CPU c m l nh t ROM ngoi. Chn ALE: - ALE (Address Latch Enable): cho php ch t a ch , chn s 30. - Ch c nng: L tn hi u cho php ch t a ch th c hi n vi c gi i a h p cho bus a ch byte th p v bus d li u a h p (AD0 AD7). L tn hi u xu t, tch c c m c cao. ALE = 0 trong th i gian bus AD0 - AD7 ng vai tr l bus D0 - D7. ALE = 1 trong th i gian bus AD0 - AD7 ng vai tr l bus A0 - A7. - Khi l p trnh cho ROM trong chip th chn ALE ng vai tr l ng vo c a xung l p trnh (PGM\) (xem sch H vi i u khi n 8051 trang 333-352). Lu : f = f OSC c th dng lm xung clock cho cc m ch khc. ALE 6 fALE (MHz): t n s xung t i chn ALE. fOSC (MHz): t n s dao ng trn chip (t n s th ch anh). - Khi l nh l y d li u t RAM ngoi (MOVX) c th c hi n th m t xung ALE b b qua (xem gi n trang 38-39 sch H vi i u khi n 8051). 2.7. Chn EA\: EA (External Access): truy xu t ngoi, chn s 31. Ch c nng: L tn hi u cho php truy xu t (s d ng) b nh chng trnh (ROM) ngoi. 13 Bin so n: Ph m Quang Tr 2.6.
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L tn hi u nh p, tch c c m c th p. EA\ = 0 Chip 8051 s d ng chng trnh c a ROM ngoi. EA\ = 1 Chip 8051 s d ng chng trnh c a ROM trong. - Khi l p trnh cho ROM trong chip th chn EA ng vai tr l ng vo c a i n p l p trnh (Vpp = 12V 12,5V cho h 89xx; 21V cho h 80xx, 87xx) (xem sch H vi i u khi n 8051 trang 333-352). Lu : Chn EA\ ph i c n i ln Vcc (n u s d ng chng trnh c a ROM trong) ho c n i xu ng GND (n u s d ng chng trnh c a ROM ngoi), khng bao gi c php b tr ng chn ny. 2.8. Chn XTAL1, XTAL2: - XTAL (Crystal): tinh th th ch anh, chn s 18-19. - Ch c nng: Dng n i v i th ch anh ho c m ch dao ng t o xung clock bn ngoi, cung c p tn hi u xung clock cho chip ho t ng. XTAL1 ng vo m ch t o xung clock trong chip. XTAL2 ng ra m ch t o xung clock trong chip. Lu : fTYP (MHz): t n s danh nh. fTYP = 12MHz
2.9.
Chn RST: RST (Reset): thi t l p l i, chn s 9. Ch c nng: L tn hi u cho php thi t l p ( t) l i tr ng thi ban u cho h th ng. L tn hi u nh p, tch c c m c cao. RST = 0 Chip 8051 ho t ng bnh th ng. RST = 1 Chip 8051 c thi t l p l i tr ng thi ban u. 12 Lu : tRe set 2 TMachine TMachine = f OSC fOSC (MHz): t n s th ch anh. tRESET ( s): th i gian reset. TMACHINE ( s): chu k my. -
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V d : Xc nh chu k my v th i gian reset tng ng cho t ng tr ng h p fOSC = 11,0592MHz, fOSC = 12MHz v fOSC = 16MHz. Gi i fOSC = 11,0592MHz TMACHINE = 1,085 s v tRESET 2,17 s. fOSC = 12MHz TMACHINE = 1 s v tRESET 2 s. fOSC = 16MHz TMACHINE = 0,75 s v tRESET 1,5 s 2.10. Chn Vcc, GND: - Vcc, GND: ngu n c p i n, chn s 40 v 20. - Ch c nng: Cung c p ngu n i n cho chip 8051 ho t ng. Vcc = +5V 10% v GND = 0V. III. C U TRC CC PORT XU T NH P CHIP 8051: Kh nng fanout (s l ng t i u ra) c a cc t ng chn port chip 8051 l: Port 0: 8 t i TTL. Port 1: 4 t i TTL. Port 2: 4 t i TTL. Port 3: 4 t i TTL. Lu : Khi Port 0 ng vai tr l port xu t nh p th s khng c i n tr ko ln bn trong do ng i s d ng c n thm vo i n tr ko ln bn ngoi (xem Hnh III.1).
ch m c nh (khi reset) th t t c cc chn c a cc port (P0 P3) c c u hnh l port xu t d li u. Mu n cc chn port c a chip 8015 lm port nh p d li u th ta c n ph i c l p trnh l i, b ng cch ghi m c logic cao (m c 1) n t t c cc bit (cc chn) c a port tr c khi b t u nh p d li u t port (v n ny c trnh by ph n k ti p).
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Cc chn trong cng m t port khng nh t thi t ph i c cng ki u c u hnh (port xu t ho c port nh p). Ngha l trong cng m t port c th c chn dng nh p d li u, c th c chn dng xu t d li u. i u ny l ty thu c vo nhu c u v m c ch c a ng i l p trnh. Qu trnh ghi chn port (xu t d li u ra chn port).
Qu trnh c chn port (nh p d li u t chn port).
Qu trnh c b ch t (ki m tra d li u t i chn port).
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Lu : Vi c c d li u c a b t k m t port no c th cho ta hai gi tr khc nhau ty thu c vo l nh m ta s d ng c d li u t port (xem thm trong ph n t p l nh). X y ra hi n t ng khng mong mu n ny l do qu trnh c d li u c a chip 8051 g m hai qu trnh khc nhau: qu trnh c chn port v qu trnh c b ch t. o Qu trnh c chn port: Khi ta s d ng cc l nh MOV, ADD, D li u nh n c sau khi th c hi n qu trnh c l d li u hi n t i cc chn port. o Qu trnh c b ch t: Khi ta s d ng cc l nh ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR bit, SETB bit, MOV bit. D li u nh n c sau khi th c hi n qu trnh c l d li u hi n t i cc b ch t (l cc d li u c ghi ra port t i th i i m tr c b i qu trnh ghi chn port), ch khng ph i l d li u hi n t i cc chn port. Cho nn, n u t i th i i m th c hi n qu trnh c m d li u t i cc chn port c b thay i i chng n a th d li u c v cng khng c c p nh t. IV. T CH C B NH C A CHIP 8051: B vi x l c khng gian b nh chung cho d li u v chng trnh.
chng trnh v d li u n m chung trn RAM tr c khi a vo CPU th c thi. B vi i u khi n c khng gian b nh ring cho d li u v chng trnh.
chng trnh v d li u n m ring trn ROM v RAM tr c khi a vo CPU th c thi. T ch c b nh c a chip 8051:
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1. B nh trong:
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1.1. B nh chng trnh (ROM): - Dng lu tr chng trnh i u khi n cho chip 8051 ho t ng. - Chip 8051 c 4 KB ROM trong, a ch truy xu t: 000H FFFH. 1.2. B nh d li u (RAM): - Dng lu tr cc d li u v tham s . - Chip 8051 c 128 byte RAM trong, a ch truy xu t: 00H 7FH. - RAM trong c a chip 8051 c chia ra: RAM a ch c nng:
RAM nh a ch bit: cho php x l t ng bit d li u ring l m khng nh h ng n cc bit khc trong c byte.
Lu : N u trong chng trnh khng s d ng cc bit trong vng RAM nh a ch bit ny, ta c th s d ng vng nh 20H 2FH cho cc m c ch khc c a ta. Ng c l i, ta ph i vi t chng trnh c n th n khi s d ng vng nh 20H 2FH v n u s su t ta c th ghi d li u ln cc bit c s d ng. V d : Vi t l nh lm cho 8 bit trong nh c a ch 20H thu c RAM n i c gi tr l 1 (xt tr ng h p a ch byte v a ch bit).
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Cc dy thanh ghi: cho php truy xu t d li u nhanh, l nh truy xu t n gi n v ng n g n.
B ng s li u d i y minh h a a ch c a cc nh trong m t dy v cc k hi u thanh ghi R0 R7 c gn cho t ng nh trong dy tch c c.
Lu : o ch m c nh th dy thanh ghi tch c c (ang c s d ng) l dy 0 v cc thanh ghi trong dy l n l t c tn l R0 - R7. C th thay i dy tch c c b ng cch thay i cc bit ch n dy thanh ghi RS1 v RS0 trong thanh ghi PSW (xem ph n thanh ghi PSW). o N u chng trnh c a ta ch s d ng dy thanh ghi u tin (dy 0) th ta c th s d ng vng nh 08H 1FH cho cc m c ch khc c a ta. Nhng n u trong chng trnh c s d ng cc dy thanh ghi (dy 1, 2 ho c 3) th ph i r t c n th n khi s d ng vng nh t 1FH tr xu ng v n u s su t ta c th ghi d li u ln cc thanh ghi R0 R7 c a ta. V d 1: Quan h gi a k hi u thanh ghi R4 v i cc nh c a ch tng ng trong dy thanh ghi tch c c? o N u dy 0 tch c c: Thanh ghi R4 nh 04H RAM n i. o N u dy 1 tch c c: Thanh ghi R4 nh 0CH RAM n i. o N u dy 2 tch c c: Thanh ghi R4 nh 14H RAM n i. o N u dy 3 tch c c: Thanh ghi R4 nh 1CH RAM n i. V d 2: Khi chip 8051 th c hi n l nh MOV R4, #1AH th gi tr 1AH s c n p vo trong nh c a ch l bao nhiu thu c RAM n i. Xt tng ng cho t ng tr ng h p dy thanh ghi tch c c l Dy 0 v Dy 3?
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Chng 2: Ph n c ng chip vi i u khi n 8051. 1.3. Thanh ghi ch c nng c bi t (SFR):
Lu : o Khng c php c hay ghi d li u vo cc a ch SFR m n cha c ng k (ngha l cc a ch SFR cha c t tn). V vi c c hay ghi d li u vo cc ni ny c th lm pht sinh nh ng ho t ng khng mong mu n v c th l nguyn nhn lm cho chng trnh c a ta khng tng thch v i cc phin b n sau c a chip MCS-51 (c th cc phin b n cc a ch SFR ny c s d ng cho m t vi m c ch khc). o Ch c truy xu t cc SFR b ng ki u nh a ch tr c ti p (tuy t i khng s d ng ki u nh a ch gin ti p trong tr ng h p ny). V d : Cho bi t tr c (R0)=90H. Vi t l nh dng xu t (ghi) gi tr 5AH ra Port1 nh sau (xem gi i thch l nh trong Chng 3: T p l nh c a 8051.): S d ng ki u nh a ch tr c ti p: MOV P1, #5AH ho c MOV 90H, #5AH S d ng ki u nh a ch gin ti p: MOV @R0, #5AH SAI i u ny khng h p l i v i chip 8051 v phng php nh a ch gin ti p nh trn ch s d ng cho vng nh RAM n i. Trong khi RAM n i c a chip 8051 ch c 128 byte (00H 7FH), cho nn khi th c hi n l nh ny n s tr v k t qu khng xc nh. (Lu : n u ta dng phin b n chip 8052 th s trnh c i u ny). 1.3.1. Thanh ghi A:
Accumulator: thanh ghi tch luy Thanh ghi A E0H E7 E6 E5 E4 E3 E2 E1 E0 a ch byte: E0H a ch bit: E0H - E7H Cong dung: cha d lieu cua cac phep toan ma vi ieu khien x ly A
1.3.2. Thanh ghi B:
Php nhn 2 s 8 bit khng d u k t qu l s 16 bit. Byte cao ch a vo thanh ghi B. Byte th p ch a vo thanh ghi A. Php chia 2 s 8 bit thng s v s d l s 8 bit. 21 Bin so n: Ph m Quang Tr
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Chng 2: Ph n c ng chip vi i u khi n 8051. Thng s ch a vo thanh ghi A. S d ch a vo thanh ghi B. V d : Th c hi n php tnh 12H x 2AH. H i (A)=?, (B)=?
x1 2 B 2 4 0 2 F 2 H A H 4 4 H (A)
(A) = F4H (B) = 02H
(B)
V d : Th c hi n php tnh A6H : 21H. H i (A)=?, (B)=?
V d : Th c hi n php tnh FDH : 0CH. H i (A)=?, (B)=?
1.3.3. Thanh ghi t PSW:
C CY (Carry Flag): c nh bo c nh /m n t i bit 7. CY = 0: n u khng c nh t bit 7 ho c khng c m n cho bit 7. CY = 1: n u c nh t bit 7 ho c c m n cho bit 7. C AC (Auxiliary Carry): c nh ph bo c nh /m n t i bit 3. AC = 0: n u khng c nh t bit 3 ho c khng c m n cho bit 3. AC = 1: n u c nh t bit 3 ho c c m n cho bit 3.
- C F0 (Flag 0): c zero c nhi u m c ch dnh cho cc ng d ng khc nhau c a ng i l p trnh (d tr cho cc phin b n chip trong tng lai).
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- Bit RS0, RS1 (Register Select): bit ch n dy thanh ghi cho php xc nh dy thanh ghi tch c c (hay dy thanh ghi m cc thanh ghi c tn l R0-R7). RS1 0 0 1 1 RS0 0 1 0 1 Dy thanh ghi Dy 0 Dy 1 Dy 2 Dy 3 R0 R7 00H 07H 08H 0FH 10H 17H 18H 1FH
- C OV (Overflow): c trn bo k t qu tnh ton c a php ton s h c (php ton c d u) c n m trong kho ng t -128 n +127 hay khng. OV = 0: n u -128 k t qu +127. OV = 1: n u k t qu < -128 ho c k t qu > +127. Ni cch khc l: i v i php c ng th OV=1 n u c nh t bit 7 nhng khng c nh t bit 6 ho c n u c nh t bit 6 nhng khng c nh t bit 7. i v i php tr th OV=1 n u c m n cho bit 7 nhng khng c m n cho bit 6 ho c n u c m n bit 6 nhng khng c m n bit 7.
- C P (Parity): c ch n l bo s ch s 1 trong thanh ghi A l s ch n hay s l (trong chip 8051 s d ng ch parity ch n). P = 0: n u s ch s 1 trong thanh ghi A l s ch n (parity ch n). P = 1: n u s ch s 1 trong thanh ghi A l s l (parity ch n). V d : Minh h a cch 8051 bi u di n s -5. Gi i Cc b c th c hi n: 0000 0101 Bi u di n s 5 d ng nh phn 8 bit. B1: B2: 1111 1010 L y b 1. 1111 1011 L y b 2. B3: V y s FBH l bi u di n s c d u d ng b 2 c a s -5. V d : Minh h a cch 8051 bi u di n s -34H. Cc b c th c hi n: 0011 0100 Bi u di n s 34H d ng nh phn 8 bit. B1: B2: 1100 1011 L y b 1. 1100 1100 L y b 2. B3: V y s CCH l bi u di n s c d u d ng b 2 c a s -34H.
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V d : Minh h a cch 8051 bi u di n s -128. Cc b c th c hi n: B1: 1000 0000 Bi u di n s -128 d ng nh phn 8 bit. B2: 0111 1111 L y b 1. 1000 0000 L y b 2. B3: V y s 80H l bi u di n s c d u d ng b 2 c a s -128. V d : Minh h a tr ng thi ho t ng c a cc c CY, AC, OV v P khi th c hi n php c ng/tr s h c hai gi tr v i nhau.
C nh (CY): Minh h a ho t ng c a c CY trong tr ng h p CY = 1:
Xt c CY trong hai tr ng h p 7AH+28H v 9AH-5DH:
Xt c CY trong hai tr ng h p 95H+86H v 00H-A6H:
C nh ph (AC): Minh h a ho t ng c a c AC trong tr ng h p AC = 1

?
AC=1 + AC=1
H L H L
AC=1
B + 7 6 5 4 3 2 1 0 B
7 6 5 4 3 2 1 0 Kieu BIN
H H
B 7 6 5 4 3 2 1 0 B
7 6 5 4 3 2 1 0
?
AC=1 H L H L
H H
Kieu HEX
Kieu HEX
Kieu BIN
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Chng 2: Ph n c ng chip vi i u khi n 8051. Xt c AC trong hai tr ng h p 92H+28H v 4AH-E3H:
Xt c AC trong hai tr ng h p 7AH+59H v 97H-5DH:
C trn (OV): Minh h a ho t ng c a c OV trong tr ng h p OV = 1
Xt c OV trong cc tr ng h p B3H+25H, BBH+C9H, BBH-96H v 4BH-F3H:
Xt c OV trong cc tr ng h p 53H+45H, 82H+BAH, 9AH-3EH v 66H-DAH:
C Parity (P): Xt c P trong cc tr ng h p (A)=45H, (A)=E7H, (A)=00H:
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V d : Xc nh n i dung cc nh thu c RAM n i c a o n chng trnh sau:
V d : Xc nh n i dung cc nh thu c RAM n i c a o n chng trnh sau:
1.3.4. Thanh ghi SP:
- Ngn x p l vng nh dng lu tr t m th i cc d li u. - i v i chip 8051 th vng nh c dng lm ngn x p c gi trong RAM n i. - s d ng ngn x p th ta ph i kh i ng thanh ghi SP (ngha l n p gi tr cho thanh ghi SP) vng nh c a ngn x p c a ch b t u: (SP)+1 v a ch k t thc: 7FH. - N u khng kh i ng SP vng nh c a ngn x p c a ch b t u: 08H v a ch k t thc: 7FH (ch m c nh). Lu : Trong tr ng h p khng kh i ng SP (ch m c nh) th dy thanh ghi 1 (v c th l dy 2 v dy 3) s khng cn h p l v khi vng nh ny c s d ng lm ngn x p. i u ny c ngha l n u ta s d ng cc dy thanh ghi ny v lu tr d li u vo th c kh nng s b m t do tc ng c t d li u vo ngn x p c a cc l nh (PUSH, ACALL, LCALL, ).
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V d : Hy cho bi t t m a ch c a vng nh ngn x p trong hai tr ng h p sau: (SP)=5FH v (SP)=49H. Theo qui nh th vng nh c a ngn x p c a ch b t u: (SP)+1 v a ch k t thc: 7FH. Tr ng h p (SP)=5FH: t m a ch c a vng nh ngn x p l 60H - 7FH. Tr ng h p (SP)=49H: t m a ch c a vng nh ngn x p l 4AH - 7FH. V d : Hy cho bi t gi tr c n ph i n p cho thanh ghi SP vng nh ngn x p c t m a ch trong hai tr ng h p sau: 62H 7FH v 50H 7FH. Theo qui nh th vng nh c a ngn x p c a ch b t u: (SP)+1 v a ch k t thc: 7FH. Tr ng h p 62H 7FH: gi tr c n n p cho thanh ghi SP l 61H. Tr ng h p 50H 7FH: gi tr c n n p cho thanh ghi SP l 4FH. V d : Minh h a vng nh ngn x p trong tr ng h p khng kh i ng SP (ch m c nh) v c kh i ng SP (v i (SP) = 3FH). N u ng i s d ng khng kh i ng thanh ghi SP (ch m c nh) th: (xem hnh bn d i, pha tri)
N u ng i s d ng mu n vng nh ngn x p (ch ty nh) c t m a ch l 40H7FH th: (xem hnh bn trn, pha ph i) 1.3.5. Thanh ghi DPTR:
Data Pointer Register: thanh ghi con tro d lieu Thanh ghi DPTR 83H 82H a ch byte: 83H va 82H DPH DPL
a ch bit: khong nh a ch bit Cong dung: la thanh ghi 16 bit (DPH+DPL), cha a ch cua o nh can truy xuat thuoc ROM (trong/ngoai) va RAM ngoai.
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Stack memory
Stack memory
V d : Khi ta mu n truy xu t (ghi/ c) d li u t m t nh thu c RAM ngoi c a ch l 0123H th ta ph i lm sao n p c gi tr 0123H vo thanh ghi DPTR v sau th c hi n l nh truy xu t MOVX (xem gi i thch l nh trong Chng 3: T p l nh c a 8051.). (DPTR) = 0123H (DPH) = 01H v (DPL) = 23H V d : Khi ta mu n truy xu t ( c) byte m t m t nh thu c ROM trong c a ch l 0ABCH th ta ph i lm sao n p c gi tr 0ABCH vo thanh ghi DPTR v sau th c hi n l nh truy xu t MOVC (xem gi i thch l nh trong Chng 3: T p l nh c a 8051.). (DPTR) = 0ABCH (DPH) = 0AH v (DPL) = BCH 1.3.6. Thanh ghi port xu t nh p:
Lu : Trong tr ng h p ph n c ng c s d ng ROM ho c RAM bn ngoi th ta khng th s d ng Port 0 v Port 2 xu t nh p d li u. V khi chip 8051 s s d ng hai port ny xc nh a ch v d li u cho b nh ngoi. Khi , ta ch c th s d ng Port 1 v Port 3 xu t nh p d li u. ch m c nh (khi reset) th t t c cc chn c a cc port (P0 P3) c c u hnh l port xu t d li u. Mu n cc chn port c a chip 8015 lm port nh p d li u th ta c n ph i c l p trnh l i, b ng cch ghi m c logic cao (m c 1) n t t c cc bit (cc chn) c a port tr c khi b t u nh p d li u t port. V d 1: Ho t ng xu t (ghi) v nh p ( c) d li u t i cc chn port (Port 0) c a chip 8051 (xem hnh minh h a bn d i). Hnh pha tri: Minh h a tr ng thi ho t ng c a port khi th c hi n l nh xu t (ghi) d li u ra Port 0 c a chip 8051. Hnh pha ph i: Minh h a tr ng thi ho t ng c a port khi th c hi n l nh nh p ( c) d li u t Port 0 c a chip 8051.
LED sang LED tat
PORT 0
+VCC +VCC
10K 39 38 37 36 35 34 33 32 330
Nhan SW
Nha SW
PORT 0
+VCC
10K 39 38 37 36 35 34 33 32
CPU - 8051 CAH

WRITE
Xuat gia tr CAH (11001010B) t chip 8051 ra Port 0. (P0)=CAH
0 1 0 1 0 0 1 1
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
CPU - 8051 92H

READ
Nhap gia tr t Port 0 vao chip 8051
0 1 0 0 1 0 0 1
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
(P0)=92H
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V d 2: o n chng trnh d i y s c u hnh cho Port 0 lm port nh p ( c) d li u. Sau lin t c c d li u t port ny v g i d li u n Port 1 (xem gi i thch l nh trong Chng 3: T p l nh c a 8051.): MOV P0, #0FFH ;C u hnh P0 lm port nh p b ng ;cch ghi 1 vo t t c cc bit. BACK: MOV A, P0 ; c d li u t P0. MOV P1, A ;G i d li u ra P1. SJMP BACK ;L p l i. V d 3: o n chng trnh d i y s th c hi n cc thao tc sau (xem gi i thch l nh trong Chng 3: T p l nh c a 8051.): Lin t c ki m tra bit P1.2 cho n khi bit ny b ng 1. Khi P1.2 =1, hy xu t (ghi) gi tr 45H ra P0. G i m t xung m c cao t i P1.3. SETB P1.2 ;C u hnh P1.2 lm ng vo. JNB P1.2, $ ;Ki m tra lin t c n u P1.2 = 0. MOV P0, #45H ; Xu t gi tr 45H ra P0. SETB P1.3 ;a P1.3 ln cao r i a P1.3 CLR P1.3 ;xu ng th p t o xung. 1.3.7. Thanh ghi port n i ti p:
(xem thm trong Chng 5: Ho t ng c a port n i ti p.)
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Chng 2: Ph n c ng chip vi i u khi n 8051. 1.3.8. Thanh ghi nh th i:
(xem thm trong Chng 4: Ho t ng c a b nh th i.)
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Chng 2: Ph n c ng chip vi i u khi n 8051. 1.3.9. Thanh ghi ng t:
(xem thm trong Chng 6: Ho t ng ng t.) 1.3.10. Thanh ghi i u khi n ngu n:
(xem thm trong Chng 5: Ho t ng c a port n i ti p.) Bit SMOD (Serial Mode) cho php tng g p i t c truy n d li u n i ti p (t c baud) khi SMOD = 1. Bit GF1, GF0 (General Function) cho php ng i l p trnh dng v i m c ch ring (d tr cho cc phin b n chip trong tng lai). Bit PD (Power Down) dng qui nh ch ngu n gim. Bit IDL (Idle) dng qui nh ch ngh.
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Lu : H th ng ph i ph c h i Vcc = 5V tr c khi thot kh i ch ngu n gim.
2. B nh ngoi: Chip 8051 cho ta kh nng m r ng: Khng gian b nh chng trnh ln n 64 KB. Khng gian b nh d li u ln n 64 KB. Khi s d ng b nh ngoi: Port 0 bus a ch byte th p v bus d li u a h p (AD0-AD7). Port 2 bus a ch byte cao (A8-A15). Port 3 cc tn hi u i u khi n (WR\, RD\). S khc nhau gi a a h p v khng a h p bus a ch v bus d li u:
nh m lm gim s l ng chn a ra ngoi chip gim kch th c c a chip.
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Chng 2: Ph n c ng chip vi i u khi n 8051. 2.1. K t n i v truy xu t b nh chng trnh ngoi:
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Chng 2: Ph n c ng chip vi i u khi n 8051. 2.2. K t n i v truy xu t b nh d li u ngoi:
Mot chu ky may ALE PSEN\ RD\ PORT 2 PORT 0 PCL PCH Lenh DPL
Mot chu ky may
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
DPH Data
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Chng 2: Ph n c ng chip vi i u khi n 8051. 2.3. Gi i m a ch :
N u ta tr ng h p ROM v RAM c k t h p t nhi u b nh c dung l ng nh ho c c hai giao ti p v i chip 8051 th ta c n ph i gi i m a ch . Vi c gi i m a ch ny cng c n cho h u h t cc b vi x l (xem thm trong Chng ph l c 1: Gi i m a ch .). V d n u cc ROM v RAM c dung l ng 8KB c s d ng th t m a ch m chip 8051 qu n l (0000H FFFFH) c n ph i c gi i m thnh t ng o n 8 KB chip c th ch n t ng IC nh trn cc gi i h n 8KB tng ng: IC1: 0000H 1FFFH, IC2: 2000H 3FFFH, IC chuyn dng cho vi c t o tn hi u gi i m l 74HC138, cc ng ra c a IC ny l n l t c n i v i cc ng vo ch n chip CS\ tng ng c a cc IC nh cho php cc IC nh ho t ng (t i m t th i i m ch c m t IC nh c php ho t ng). C n lu l do cc ng cho php IC nh ho t ng ring l cho t ng lo i (PSEN\ cho b nh chng trnh, RD\ v WR\ cho b nh d li u) nn 8051 c th qu n l khng gian nh ln n 64KB cho ROM v 64KB cho RAM.
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Chng 2: Ph n c ng chip vi i u khi n 8051. 2.4. Cc khng gian nh chng trnh v d li u g i nhau:
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Chng 2: Ph n c ng chip vi i u khi n 8051. V. HO T NG RESET:
Chn RST = 0 Chip 8051 ho t ng bnh th ng. Chn RST = 1 Chip 8051 c reset. Lu : o hon t t qu trnh reset th chn RST ph i m c cao t i thi u l 2 chu k my v sau chuy n xu ng m c th p. o N i dung c a RAM trong chip khng b nh h ng b i ho t ng reset. o Sau khi reset, vi c th c thi chng trnh lun lun b t u vi tr u tin trong b nh chng trnh: a ch 0000H. o Tr ng thi c a cc thanh ghi sau khi reset h th ng: B m chng trnh (PC) 0000H Thanh ghi A 00H Thanh ghi B 00H Thanh ghi PSW 00H Thanh ghi SP 07H Thanh ghi DPTR 0000H Port 0 Port 3 FFH Thanh ghi IP xxx00000B Thanh ghi IE 0xx00000B Cc thanh ghi nh th i 00H Thanh ghi SCON 00H Thanh ghi SBUF 00H Thanh ghi PCON (HMOS) 0xxxxxxxB Thanh ghi PCON (CMOS) 0xxx0000B VI. PH N BI T P: Bi 1: S d ng m t vi m ch 74138 v cc c ng c n thi t thi t k m ch gi i m a ch t o ra cc tn hi u ch n chip tng ng cc vng a ch sau: Tn hi u ch n chip
CS0
CS1
Vng a ch 0000H - 3FFFH 4000H - 7FFFH 6000H - 7FFFH 8000H - 87FFH 8800H - 8FFFH
c tnh truy xu t
PSEN
PSEN
CS2
CS3
RD, WR
RD
CS4
WR
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Bi 2: S d ng m t vi m ch 74138 v cc c ng c n thi t thi t k m ch gi i m a ch t o ra cc tn hi u ch n chip tng ng cc vng a ch sau: Tn hi u ch n chip

CS0
CS1
Vng a ch 9800H - 9BFFH 9800H - 9BFFH 9C00H - 9DFFH 9E00H - 9EFFH
c tnh truy xu t
PSEN
RD, WR RD, WR
RD, WR
CS2
CS3
Bi 3: Ch dng m t vi m ch 74138 (khng dng thm c ng), thi t k m ch gi i m a ch t o ra m t tn hi u ch n chip /CS tng ng t m a ch F000H-F3FFH.
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GIO TRNH VI X
Chng 3: T p l nh c a 8051.
CHNG 3 T P L NH C A 8051
I. M U:
Khung d ng t ng qut c a m t dng l nh: [LABEL:] MNEMONIC [OPERAND][,OPERAND] [;COMMENT] o Nhn (Label): bi u th a ch c a dng l nh (ho c d li u) theo sau, c dng trong tr ng ton h ng c a l nh nh y, l nh r nhnh (SJMP AAA; ACALL BBB; CJNE A, #35H, LOOP; JNB P3.1, TEST_1). Lu v nhn: Do ng i l p trnh t t (khng c trng v i t kho, m g i nh , ch d n, ton t ho c k hi u ti n nh ngha). B t u b ng k t ch , d u ch m h i (?), d u g ch d i (_). Di t i a 31 k t . K t thc b ng d u hai ch m (:). o M g i nh (Mnemonic): bi u di n cc m c a l nh ho c cc ch d n c a chng trnh d ch h p ng (M g i nh : ADD, SUBB, INC, ; Ch d n: ORG, EQU, DB, ). o Ton h ng (Operand): ch a a ch ho c d li u m l nh s s d ng. S l ng ton h ng trong m t dng l nh ph thu c vo t ng dng l nh (RET khng ton h ng, INC A m t ton h ng, ADD A, R0 hai ton h ng, CJNE A, #12H, ABC ba ton h ng). Lu v ton h ng: trong cc l nh c 2 ton h ng th ton h ng u tin cn c g i l ton h ng ch (Destination), ton h ng th hai cn c g i l ton h ng ngu n (Source). o Ch thch (Comment): lm cho r ngha cho chng trnh. Cc ch thch ph i n m trn cng m t dng v b t u b ng d u ch m ph y (;). Cc ch thch n u n m trn nhi u dng th m i dng cng ph i b t u b ng d u ch m ph y (;). Lu : Chi ti t v ph n ny xem thm t i Chng 7: L p trnh h p ng trong sch H vi i u khi n T ng Vn On.
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Chng 3: T p l nh c a 8051. II. CC KI U NH A CH (ADDRESSING MODE):
1. nh a ch thanh ghi (Register Addressing): c dng truy xu t d li u trong cc thanh ghi t R0 n R7. S byte c a l nh: 1 byte. C u trc l nh: V d : ADD A, R5 L nh c ng n i dung thanh ghi A v i n i dung thanh ghi R5. (Gi s : (A)=05H, (R5)=9AH). M l nh:
M t l nh: Ngoi ra, m t s tr ng h p c bi t ki u nh a ch ny cng dng truy xu t d li u trong cc thanh ghi nh: thanh ghi ch a A, thanh ghi con tr d li u DPTR, thanh ghi b m chng trnh PC, c nh C v c p thanh ghi AB. V d : INC A INC DPTR L nh tng n i dung thanh ghi A. L nh tng n i dung thanh ghi DPTR.
2. nh a ch tr c ti p (Direct Addressing): c dng truy xu t d li u trong cc nh (00H - FFH) hay trong cc thanh ghi (A, B, P0P3, DPH, DPL,) c a b nh bn trong chip. S byte c a l nh: 2 byte. C u trc l nh:
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V d : ADD A, P1 ADD A, 90H L nh c ng n i dung thanh ghi A v i n i dung thanh ghi port 1 hay nh 90H. (Gi s : (A) = 05H, (P1) = (90H) = 9AH).
M l nh:
M t l nh: 3. nh a ch gin ti p (Indirect Addressing): c dng truy xu t d li u trong cc nh gin ti p c a b nh bn trong chip. Cc thanh ghi R0 v R1 c dng ch a a ch c a cc nh gin ti p (00H - FFH) trong chip. Lu r ng, tr c cc thanh ghi R0, R1 c n ph i c d u @. S byte c a l nh: 1 byte. C u trc l nh: V d : ADD A, @R0 L nh c ng n i dung thanh ghi A v i n i dung nh c a ch ch a trong thanh ghi R0. (Gi s : (A) = 05H, (R0) = 3BH, (3BH) = 9AH).
M l nh:
M t l nh: 4. nh a ch t c th i (Immediate Addressing): c dng truy xu t m t h ng s (gi tr bi t tr c) thay v l m t bi n (gi tr khng bi t tr c) nh cc ki u nh a ch trn. Lu r ng, tr c d li u t c th i c n ph i c d u #. Ch nh a ch t c th i c th dng n p d li u vo m i nh v thanh ghi b t k ( i v i thanh ghi 8 bit: #00H - #0FFH, i v i thanh ghi 16 bit: #0000H - #0FFFFH). S byte c a l nh: 2 byte. C u trc l nh: V d : ADD A, #9AH L nh c ng n i dung thanh ghi A v i gi tr 9AH. (Gi s : (A) = 05H). M l nh:
M t l nh:
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Chng 3: T p l nh c a 8051. 5. nh a ch tng i (Relative Addressing): c s d ng cho cc l nh nh y. a ch tng i (hay offset) l m t gi tr 8 bit c d u.
T m nh y gi i h n l: -128 byte 127 byte t v tr c a l nh ti p theo sau l nh nh y. S byte c a l nh: 2 byte. C u trc l nh: V d 1: SJMP AAA L nh nh y n nhn AAA (Gi s : nhn AAA t tr c l nh 0107H, l nh SJMP n m trong b nh t i a ch 0100H v 0101H). a ch
M l nh: M t l nh: xem hnh 3.5.2.1. V d 2: SJMP AAA L nh nh y n nhn AAA (Gi s : nhn AAA t tr c l nh 203BH, l nh SJMP n m trong b nh t i a ch 2040H v 2041H). a ch
M l nh: M t l nh: xem hnh 3.2.5.2.
6. nh a ch tuy t i (Absolute Addressing): c s d ng cho cc l nh ACALL v AJMP. a ch tuy t i l m t gi tr 11 bit. T m nh y gi i h n l: trong cng trang 2K hi n hnh (trang 2K ch a l nh nh y). S byte c a l nh: 2 byte. C u trc l nh:
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Tr ng H Cng nghi p Tp.HCM. a ch
V d : AJMP AAA L nh nh y n nhn AAA (Gi s : nhn AAA t tr c l nh 0F46H, l nh AJMP n m trong b nh t i a ch 0900H v 0901H).
M l nh: M t l nh:
FFFFH F800H F800H 1800H 17FFH 1000H 0FFFH 0800H 07FFH 0000H 2K trang 31 0FFFH
2K trang 2 2K trang 1 2K trang 0
32 x 2K (64K)
AAA 2K trang 1
0F46H
0901H 0900H
46H E1H
AJMP AAA
Ban o nh 64K c chia thanh 32 trang 2K

A15 A11A10
0800H
A0
Cach thanh lap a ch cua nhan se nhay ti
5 bit xac nh trang 2K T 5 bit (A15...A11) trong thanh ghi PC
11 bit xac nh a ch trong 1 trang 2K T 11 bit (A10...A0) trong lenh nhay
7. nh a ch di (Long Addressing): c s d ng cho cc l nh LCALL v LJMP. a ch di l m t gi tr 16 bit. T m nh y gi i h n l: ton b khng gian nh 64K. S byte c a l nh: 3 byte. C u trc l nh:
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Tr ng H Cng nghi p Tp.HCM. a ch
V d : LJMP AAA L nh nh y n nhn AAA (Gi s : nhn AAA t tr c l nh A209H, l nh LJMP n m trong b nh t i a ch 0100H, 0101H v 0102H). M l nh:
FFFFH
AAA 64K
A209H
0102H 0101H 0100H
09H A2H 12H
LJMP AAA
0000H
M t l nh: 8. nh a ch ch s (Indexed Addressing): c dng trong cc ng d ng c n t o cc b ng nh y hay cc b ng tm ki m. Ki u nh a ch ny dng m t thanh ghi n n (PC hay DPTR) k t h p v i m t offset (A) t o thnh d ng a ch hi u d ng cho l nh. S byte c a l nh: 1 byte. C u trc l nh:
V d : JMP @A+DPTR L nh nh y gin ti p.
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Chng 3: T p l nh c a 8051. III. T P L NH C A 8051 (8051 INSTRUCTION SET):
M t s k hi u dng trong l nh: Rn a ch thanh ghi s d ng (R0 R7). direct a ch tr c ti p c a m t byte trong RAM n i (00H-FFH) @Ri a ch gin ti p s d ng (R0 ho c R1). source Ton h ng ngu n (Rn, direct ho c @Ri). dest Ton h ng ch (Rn, direct ho c @Ri). #data H ng s 8 bit (#00H - #0FFH). #data16 H ng s 16 bit (#0000H - #0FFFFH). bit a ch tr c ti p c a m t bit ( a ch bit). rel Offset 8 bit c d u. addr11 a ch 11 bit. addr16 a ch 16 bit. c thay th b i () N i dung c a (( )) N i dung c ch a b i rrr Thanh ghi c a dy thanh ghi (000 = R0, 001 = R1, , 111 = R7). i a ch gin ti p s d ng R0 (i = 0) ho c R1 (i = 1). dddddddd Cc bit d li u. aaaaaaaa Cc bit a ch . eeeeeeee a ch tng i. M t s lu khi l p trnh b vi i u khi n 8051: thng bo l m t gi tr t c th i th c n ph i t thm k hi u # vo tr c gi tr . N u khng c k hi u # th gi tr c hi u l a ch c a nh . MOV A, #12H ;N p gi tr 12H vo thanh ghi A. MOV A, 12H ;Sao chp n i dung c a nh c a ;ch 12H vo thanh ghi A. y ta cng nn lu r ng n u thi u k hi u # th l nh trn cng khng gy ra l i trong qu trnh bin d ch. V trnh d ch h p ng cho l m t l nh h p l . Tuy nhin, k t qu l p trnh s khng ng nh mu n c a ng i l p trnh. Cc gi tr t c th i n u c thnh ph n ch (A, B, C, , F) ng u th c n ph i thm s 0 vo tr c thnh ph n ch v sau k hi u #. Vi c ny bo r ng thnh ph n ch l m t s HEX ch khng ph i l m t k t . MOV A, #BH ;Thi u s 0 gy l i khi bin d ch. MOV A, #0BH ;Thm s 0 ng. MOV A, #F9H ;Thi u s 0 gy l i khi bin d ch. MOV A, #0F9H ;Thm s 0 ng.
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y ta cng nn lu r ng vi c thi u s 0 thm vo ny s gy l i trong qu trnh bin d ch i v i cc chng trnh bin d ch c. Ngy nay, m t s ph n m m bin d ch h tr vi c ny. i u ny c ngha l ta c th thm hay khng thm s 0 vo th u khng nh h ng g n qu trnh bin d ch (khng gy ra l i khi bin d ch). Trong l nh, cc gi tr t c th i hay a ch c a nh c th c bi u di n d i b t k d ng no BIN (nh phn), DEC (th p phn) hay HEX (th p l c phn). o a ch nh : cc cu l nh sau y l tng ng nhau: MOV A, 64H ;Sao chp n i dung c a nh c a ;ch 64H vo thanh ghi A. MOV A, 100 ;Sao chp n i dung c a nh c a ;ch 64H vo thanh ghi A. MOV A, 01100100B ;Sao chp n i dung c a nh c a ;ch 64H vo thanh ghi A. o Gi tr t c th i: cc cu l nh sau y l tng ng nhau: MOV A, #0C9H ;N p gi tr C9H vo thanh ghi A. MOV A, #201 ;N p gi tr C9H vo thanh ghi A. MOV A, #11001001B ;N p gi tr C9H vo thanh ghi A. Lu cc h u t i km tng ng cho t ng d ng: B d ng BIN (nh phn), H d ng HEX (th p l c phn), D ho c khng c h u t d ng DEC (th p phn). Chuy n m t gi tr t c th i hay a ch c a nh l n hn kh nng ch a c a m t thanh ghi th s gy ra l i (00H-FFH: cho thanh ghi ho c nh 8 bit; 0000H-FFFFH: cho thanh ghi 16 bit DPTR). MOV A, #123H ;Khng h p l v 123H > FFH. MOV A, #214 ;H p l v 214 (D6H) < FFH (255). MOV A, #0F2H ;H p l v F2H < FFH. MOV A, 123H ;Khng h p l v 123H > FFH. MOV A, 200 ;H p l v 200 (C8H) < FFH (255). MOV DPTR, #123H ;H p l v 123H < FFFFH (16 bit). 1. Nhm l nh s h c: 1.1. L nh ADD A, <src-byte>: Ch c nng: C ng (Add). M t : ADD c ng n i dung c a thanh ghi A (A) v i n i dung c a m t byte c a ch c ch ra trong l nh (src- byte) v t k t qu vo thanh ghi A. Cc c b nh h ng. o C CY = 1 n u c s nh t bit 7. Ng c l i CY = 0. o C AC = 1 n u c s nh t bit 3. Ng c l i AC = 0. o C OV = 1 n u c s nh t bit 6 nhng khng c s nh t bit 7 ho c n u c s nh t bit 7 nhng khng c s nh t bit 6. Ng c l i OV = 0. o Khi c ng hai s nguyn khng d u v c d u: S khng d u: CY = 1 Php ton c nh . S c d u: CY = 1 S dng = S m + S m. S m = S dng + S dng.
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Chng 3: T p l nh c a 8051. Cc d ng l nh: ADD A, Rn S byte S chu k M i t ng Ho t ng ADD A, direct S byte S chu k M i t ng Ho t ng ADD A, @Ri S byte S chu k M i t ng Ho t ng ADD A, #data S byte S chu k M i t ng Ho t ng
1 1 00101rrr (A) (A) + (Rn) 2 1 00100101 aaaaaaaa (A) (A) + (direct) 1 1 0010011i (A) (A) + ((Ri)) 2 1 00100100 dddddddd (A) (A) + #data
V d : Cho bi t tr c (A)=C3H, (R0)=47H, (P1)=(90H)=AAH, (47H)=D2H. Sau khi th c thi l nh ADD A, R0 th: (A)=0AH, CY=1, AC=0, OV=0
Sau khi th c thi l nh ADD A, 90H hay ADD A, P1 th: (A)=6DH, CY=1, AC=0, OV=1
Sau khi th c thi l nh ADD A, @R0 th: (A)=95H, CY=1, AC=0, OV=0
A C3H R0 47H 47H D2H
ADD A, @R0
C3H + D2H = 95H
A 95H
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Sau khi th c thi l nh ADD A, #4EH th: (A)=11H, CY=1, AC=1, OV=0
1.2. ADDC A, <src-byte> Ch c nng: C ng c c nh (Add with Carry). M t : ADDC c ng ng th i n i dung c a thanh ghi A (A) v i n i dung c a byte c a ch c ch ra trong l nh (src-byte) v c nh (CY), t k t qu vo thanh ghi A. Cc c b nh h ng. o C CY = 1 n u c s nh t bit 7. Ng c l i CY = 0. o C AC = 1 n u c s nh t bit 3. Ng c l i AC = 0. o C OV = 1 n u c s nh t bit 6 nhng khng c s nh t bit 7 ho c n u c s nh t bit 7 nhng khng c s nh t bit 6. Ng c l i OV = 0. o Khi c ng hai s nguyn khng d u v c d u: S khng d u: CY = 1 Php ton c nh . S c d u: CY = 1 S dng = S m + S m. S m = S dng + S dng. Cc d ng l nh: ADDC A, Rn S byte S chu k M i t ng Ho t ng ADDC A, direct S byte S chu k M i t ng Ho t ng ADDC A,@Ri S byte S chu k M i t ng Ho t ng ADDC A, #data S byte S chu k M i t ng Ho t ng 1 1 00110rrr (A) (A) + (C) + (Rn) 2 1 00110101 aaaaaaaa (A) (A) + (C) + (direct) 1 1 0011011i (A) (A) + (C) + ((Ri)) 2 1 00110100 dddddddd (A) (A) + (C) + # data
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V d : Cho bi t tr c (A)=C3H, (R0)=47H, (P1)=(90H)=AAH, (47H)=D2H v c CY=1. Sau khi th c thi l nh ADDC A, R0 th: (A)=0BH, CY=1, AC=0, OV=0
A C3H R0 47H
CY C3H + 47H + 1H = 0BH
ADDC A, R0
A 0BH
Sau khi th c thi l nh ADDC A, 90H hay ADDC A, P1 th: (A)=6DH, CY=1, AC=0, OV=1
Sau khi th c thi l nh ADDC A, @R0 th: (A)=96H, CY=1, AC=0, OV=0
Sau khi th c thi l nh ADDC A, #4EH th: (A)=11H, CY=1, AC=1, OV=0
A C3H 4EH
1.3. SUBB A, <src-byte>
ADDC A, #4EH
C3H + 4EH + 1H = 12H
12H
Ch c nng: Tr c s m n (Subtract with Borrow). M t : SUBB tr n i dung c a thanh ghi A (A) v i n i dung c a byte c a ch c ch ra trong l nh (src-byte) cng v i c nh v c t k t qu vo thanh ghi A. Cc c b nh h ng. o C CY = 1 n u c s m n cho bit 7. Ng c l i CY = 0. o C AC = 1 n u c s m n cho bit 3. Ng c l i AC = 0. o C OV = 1 n u c s m n cho bit 6 nhng khng c s m n cho bit 7 ho c n u c s m n cho bit 7 nhng khng c s m n cho bit 6. Ng c l i OV = 0. o Khi c ng hai s nguyn khng d u v c d u: S khng d u: CY = 1 Php ton c m n. S c d u: CY = 1 S dng = S m - S dng. S m = S dng - S m.
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Chng 3: T p l nh c a 8051. Cc d ng l nh: SUBB A, Rn S byte S chu k M i t ng Ho t ng SUBB A, direct S byte S chu k M i t ng Ho t ng SUBB A, @Ri S byte S chu k M i t ng Ho t ng SUBB A, #data S byte S chu k M i t ng Ho t ng
1 1 10011rrr (A) (A) (C) (Rn) 2 1 10010101 aaaaaaaa (A) (A) (C) (direct) 1 1 1001011i (A) (A) (C) ((Ri)) 1 1 100110100 dddddddd (A) (A) (C) #data
V d : Cho bi t tr c (A)=83H, (R0)=78H, (P1)=(90H)=AAH, (78H)=C5H v c CY=1. Sau khi th c thi l nh SUBB A, R0 th: (A)=0AH, CY=0, AC=1, OV=1
Sau khi th c thi l nh SUBB A, 90H hay SUBB A, P1 th: (A)=D8H, CY=1, AC=1, OV=0
Sau khi th c thi l nh SUBB A, @R0 th: (A)=BDH, CY=1, AC=1, OV=0
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Sau khi th c thi l nh SUBB A, #D6H th: (A)=ACH, CY=1, AC=1, OV=0
1.4. INC byte Ch c nng: Tng thm 1 (Increment). M t : Lu : Tng n i dung c a byte c a ch c ch ra trong l nh (byte) thm 1. Cc c khng b nh h ng. Khi l nh ny c dng thay i gi tr c a m t port xu t th gi tr c dng lm d li u ban u c a port c l y t b ch t d li u xu t, khng ph i c l y t cc chn nh p. INC A S byte S chu k M i t ng Ho t ng INC Rn S byte S chu k M i t ng Ho t ng INC direct S byte S chu k M i t ng Ho t ng INC @Ri S byte S chu k M i t ng Ho t ng Sau khi th c thi l nh INC A th: (A)=C4H
Cc d ng l nh: 1 1 00000100 (A) (A) + 1 1 1 00001rrr (Rn) (Rn) + 1 2 1 00000101 aaaaaaaa (direct) (direct) + 1 1 1 0000011i ((Ri)) ((Ri)) + 1
V d : Cho bi t tr c (A)=C3H, (R0)=69H, (P1)=(90H)=AAH, (69H)=7FH.
Sau khi th c thi l nh INC 90H hay INC P1 th: (P1)=(90H)=ABH
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Chng 3: T p l nh c a 8051. Sau khi th c thi l nh INC @R0 th: (@R0)=(69H)=80H
Sau khi th c thi l nh INC R0 th: R0=6AH
1.5. INC DPTR Ch c nng: Tng con tr d li u (Increment Data Pointer). M t : Tng n i dung c a thanh ghi con tr d li u 16-bit thm 1. Cc c khng b h ng. S byte S chu k M i t ng Ho t ng V d 1: Cho bi t tr c (DPTR)=1234H. Sau khi th c thi l nh INC DPTR th: (DPTR)=1235H v i (DPH)=12H v (DPL)=35H 1 2 10100011 (DPTR) (DPTR) + 1 nh
V d 2: Cho bi t tr c (DPH)=12H v (DPL)=FFH. Sau khi th c thi l nh INC DPTR th: (DPTR)=1300H v i (DPH)=13H v (DPL)=00H
Lu :
Khng c l nh gim n i dung c a DPTR (DEC DPTR). N u mu n gim n i dung c a DPTR ta ph i vi t m t o n chng trnh con th c hi n i u ny. Chng trnh con c minh h a nh sau: DEC_DPTR: ;Chng trnh con gim DPTR. PUSH ACC ;C t t m gi tr ACC. DEC DPL ;Gim byte th p c a DPTR. MOV A, DPL ;So snh byte th p c a DPTR CJNE A,#0FFH, SKIP ;v i FFH. DEC DPH ;Gim byte cao c a DPTR. SKIP: POP ACC ;Ph c h i gi tr ACC. RET
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Chng 3: T p l nh c a 8051. 1.6. DEC byte Ch c nng: Gim b t 1 (Decrement). M t : Lu :
Gim n i dung c a byte c a ch c ch ra trong l nh (byte) b t 1. Cc c khng b nh h ng. Khi l nh ny c dng thay i gi tr c a m t port xu t th gi tr c dng lm d li u ban u c a port c l y t b ch t d li u xu t, khng ph i c l y t cc chn nh p. DEC A S byte S chu k M i t ng Ho t ng DEC Rn S byte S chu k M i t ng Ho t ng DEC direct S byte S chu k M i t ng Ho t ng DEC @Ri S byte S chu k M i t ng Ho t ng 1 1 00011rrr (Rn) (Rn) 1 2 1 00010101 aaaaaaaa (direct) (direct) 1 1 1 0001011i ((Ri)) ((Ri)) 1 1 1 00010100 (A) (A) 1
Cc d ng l nh:
V d : Cho bi t tr c (A)=C3H, (R0)=60H, (P1)=(90H)=AAH, (60H)=7AH. Sau khi th c thi l nh DEC A th: (A)=C2H
Sau khi th c thi l nh DEC 90H hay DEC P1 th: (P1)=(90H)=A9H
Sau khi th c thi l nh DEC @R0 th: (@R0)=(60H)=79H
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Chng 3: T p l nh c a 8051. Sau khi th c thi l nh DEC R0 th: R0=5FH
1.7. MUL AB Ch c nng: Nhn (Multiply). M t : MUL AB nhn cc s nguyn khng d u 8-bit ch a trong thanh ghi A v thanh ghi B. Tch s l m t gi tr 16 bit, byte th p (8 bit th p) c c t trong thanh ghi A cn byte cao (8 bit cao) c c t trong thanh ghi B. N u tch s l n hn 255 (0FFH) th c trn OV=1. C nh CY lun lun b xa. S byte S chu k M i t ng Ho t ng 1 4 10100100 (B) HIGH BYTE OF (A) (B) (A) LOW BYTE OF (A) (B)
V d 1: Cho bi t tr c (A)=02H, (B)=7CH. Sau khi th c thi l nh MUL AB th: (B)= 00H, (A)= F8H, CY=0, OV=0.
V d 2: Cho bi t tr c (A)=C3H, (B)=AAH. Sau khi th c thi l nh MUL AB th: (B)= 81H, (A)= 7EH, CY=0, OV=1.
1.8. DIV AB Ch c nng: Chia (Divide). M t : DIV AB chia s nguyn khng d u 8-bit ch a trong thanh ghi A cho s nguyn khng d u 8-bit ch a trong thanh ghi B. Thng s c c t trong thanh ghi A cn s d c c t trong thanh ghi B. C CY v c OV b xo. N u ban u B ch a 00H, gi tr tr v trong thanh ghi A v thanh ghi B khng c xc nh v c OV=1. C CY c xa trong m i tr ng h p. S byte S chu k M i t ng Ho t ng 1 4 10000100 (A) QUOTIENT OF (A) / (B) (B) REMAINDER OF (A) / (B)
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Chng 3: T p l nh c a 8051. V d 1: Cho bi t tr c (A)=C3H, (B)=0AH.
Sau khi th c thi l nh DIV AB th: (B)= 05H, (A)= 13H, CY=0, OV=0.
V d 2: Cho bi t tr c (A)=00H, (B)=0AH. Sau khi th c thi l nh DIV AB th: (B)= 00H, (A)= 00H, CY=0, OV=0.
V d 3: Cho bi t tr c (A)=C3H, (B)=00H. Sau khi th c thi l nh DIV AB th: (B)= yyH, (A)= xxH, CY=0, OV=1.
DIV AB
A C3H B
1.9. DA A
00H
C3H / 00H = xxH d yyH
yyH
A xxH
Ch c nng: Hi u ch nh th p phn n i dung c a thanh ghi A i v i php c ng (Decimal-adjust Accumulator for Addition) M t : DA A hi u ch nh gi tr 8-bit trong thanh ghi A (gi tr ny l k t qu php c ng hai ton h ng c d ng BCD - gi tr c ) t o ra hai digit 4 bit. Php c ng c th c hi n b i l nh ADD ho c ADDC, l nh DA A khng p d ng cho php tr SUBB). N u c AC = 1 ho c n u 4 bit th p c a thanh ghi A c gi tr > 9 (xxxx1010 xxxx1111), th 6 c c ng v i n i dung c a thanh ghi A t o ra s BCD 4 bit th p. Sau khi c ng, c CY = 1 n u c s nh t 4 bit th p chuy n n t t c 4 bit cao. N u c CY = 1 ho c n u 4 bit cao c a thanh ghi A c gi tr > 9 (1010xxxx 1111xxxx), th 6 c c ng v i 4 bit cao t o ra s BCD 4 bit cao. Sau khi c ng c CY = 1 n u c s nh t 4 bit cao nhng c CY khng b xa. V y th c CY ch ra r ng t ng c a 2 ton h ng BCD ban u l n hn 99. C OV khng b nh h ng. T t c s ki n trn ch x y ra trong m t chu k my. L nh ny th c hi n php bi n i th p phn b ng cch c ng 00H, 06H, 60H hay 66H v i n i dung c a thanh ghi A ty thu c vo n i dung ban u c a thanh ghi A v cc i u ki n c a t tr ng thi chng trnh PSW. DA A khng th n gi n bi n i s hex trong thanh ghi A thnh s d ng BCD, DA A cng khng p d ng cho php tr th p phn. S byte S chu k M i t ng Gio trnh Vi x l. 1 1 11010100 55 Bin so n: Ph m Quang Tr
Lu :
Chng 3: T p l nh c a 8051. Ho t ng
Tr ng H Cng nghi p Tp.HCM. Gi s n i dung c a thanh ghi A l BCD IF [[(A3 A0) > 9] OR [(AC) = 1]] THEN (A3 A0) (A3 A0) + 6 AND IF [[(A7 A4) > 9] OR [(C) = 1]] THEN (A7 A4) (A7 A4) + 6
V d 1: Cho bi t tr c (A)=56H bi u di n BCD c a s 56 (R3)=67H bi u di n BCD c a s 67 ADD A, R3 DA A th: c CY=1 v (A)=23 bi u di n BCD c a s 123 (56+67) Sau khi th c thi chu i l nh:
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V d 4: Cho bi t tr c (A)=56H bi u di n BCD c a s 56 (R3)=67H bi u di n BCD c a s 67 c CY=1 ADDC A, R3 DA A th: c CY=1 v (A)=24 bi u di n BCD c a s 124 (56+67+1) Sau khi th c thi chu i l nh:
Lu :
Cc gi tr BCD c th c tng thm 1 n v ho c gim i 1 n v b ng cch c ng v i 01H (khi tng) ho c c ng v i 99H (khi gim).
o V d 1: Gi s cho (A)=39H bi u di n BCD c a s 39. ADD A, #01H DA A th: c CY=0 v (A)=40H bi u di n BCD c a s 40. Sau khi th c thi chu i l nh: o V d 2: Gi s cho (A)=30H bi u di n BCD c a s 30. ADD A, #99H DA A th: c CY=1 v (A)=29H bi u di n BCD c a s 29. Sau khi th c thi chu i l nh: 2. Nhm l nh logic: B ng tr ng thi c a cc php ton logic AND OR XOR CPL A 0 0 1 1 B 0 1 0 1 A AND B 0 0 0 1 A OR B 0 1 1 1 A XOR B 0 1 1 0 CPL A 1 1 0 0
2.1. ANL <dest-byte>, <src-byte> Ch c nng: AND hai ton h ng (Logical-AND). M t : Lu : ANL th c hi n php ton AND t ng bit gi a hai ton h ng c ch ra trong l nh v lu k t qu vo ton h ng ch (dest-byte). Cc c khng b nh h ng. Khi l nh ny c dng s a i m t port xu t, gi tr c dng lm d li u ban u c a port c c t b ch t d li u xu t, khng ph i t cc chn port.
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Chng 3: T p l nh c a 8051. Cc d ng l nh: ANL A, Rn S byte S chu k M i t ng Ho t ng ANL A, direct S byte S chu k M i t ng Ho t ng ANL A, @Ri S byte S chu k M i t ng Ho t ng ANL A, #data S byte S chu k M i t ng Ho t ng ANL direct, A S byte S chu k M i t ng Ho t ng ANL direct, #data S byte S chu k M i t ng Ho t ng Sau khi th c thi l nh ANL A, R0 th: (A)=02H
A C3H R0 2AH
ANL A, R0
1 1 01011rrr (A) (A) AND (Rn) 2 1 01010101 aaaaaaaa (A) (A) AND (direct) 1 1 0101011i (A) (A) AND ((Ri)) 2 1 01010100 dddddddd (A) (A) AND #data 2 1 01010010 aaaaaaaa (direct) (direct) AND (A) 3 2 01010011 aaaaaaaa dddddddd (direct) (direct) AND #data
V d : Cho bi t tr c (A)=C3H, (R0)=2AH, (P3)=(B0H)=75H, (2AH)=55H.
C3H AND 2AH = 02H

AND
A 02H
11000011B 00101010B 00000010B
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Chng 3: T p l nh c a 8051. Sau khi th c thi l nh ANL A, B0H hay ANL A, P3 th: (A)=41H
Sau khi th c thi l nh ANL A, @R0 th: (A)=41H
Sau khi th c thi l nh ANL A, #2AH th: (A)=02H
Sau khi th c thi l nh ANL B0H, A hay ANL P3, A th: (P3)=41H
Sau khi th c thi l nh ANL 2AH, #B0H th: (2AH)=10H
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Chng 3: T p l nh c a 8051. 2.2. ORL <dest-byte>, <src-byte> Ch c nng: OR logic hai ton h ng (Logical-OR). M t : Lu :
ORL th c hi n php ton OR t ng bit gi a hai ton h ng c ch ra trong l nh v lu k t qu vo ton h ng ch (dest-byte). Cc c khng b nh h ng. Khi l nh ny c dng s a i m t port xu t, gi tr c dng lm d li u ban u c a port c c t b ch t d li u xu t, khng ph i t cc chn port. ORL A, Rn S byte S chu k M i t ng Ho t ng ORL A, direct S byte S chu k M i t ng Ho t ng ORL A, @Ri S byte S chu k M i t ng Ho t ng ORL A, #data S byte S chu k M i t ng Ho t ng ORL direct, A S byte S chu k M i t ng Ho t ng ORL direct, #data S byte S chu k M i t ng Ho t ng
Cc d ng l nh: 1 1 01001rrr (A) (A) OR (Rn) 2 1 01000101 aaaaaaaa (A) (A) OR (direct) 1 1 0100011i (A) (A) OR ((Ri)) 2 1 01000100 dddddddd (A) (A) OR #data 2 1 01000010 aaaaaaaa (direct) (direct) OR (A) 3 2 01000011 aaaaaaaa dddddddd (direct) (direct) OR #data
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V d : Cho bi t tr c (A)=C3H, (R0)=2AH, (P3)=(B0)=75H, (2AH)=55H. Sau khi th c thi l nh ORL A, R0 th: (A)=EBH
Sau khi th c thi l nh ORL A, B0H hay ORL A, P3 th: (A)=F7H
Sau khi th c thi l nh ORL A, @R0 th: (A)=D7H
Sau khi th c thi l nh ORL A, #2AH th: (A)=EBH
A C3H 2AH
ORL A, #2AH
C3H OR 2AH = EBH

OR
A EBH
11000011B 00101010B 11101011B
Sau khi th c thi l nh ORL B0H, A hay ORL P3, A th: (P3)=F7H
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Chng 3: T p l nh c a 8051. Sau khi th c thi l nh ORL 2AH, #B0H th: (2AH)=F5H
2AH 55H B0H
ORL 2AH, #B0H
55H OR B0H = F5H

OR
2AH F5H
01010101B 10110000B 11110101B
2.3. XRL <dest-byte>, <src-byte> Ch c nng: XOR logic hai ton h ng (Logical Exclusive-OR). M t : Lu : XRL th c hi n php ton XOR t ng bit gi a hai ton h ng c ch ra trong l nh v lu k t qu vo ton h ng ch (dest-byte). Cc c khng b nh h ng. Khi l nh ny c dng s a i m t port xu t, gi tr c dng lm d li u ban u c a port c c t b ch t d li u xu t, khng ph i t cc chn port. XRL A, Rn S byte S chu k M i t ng Ho t ng XRL A, direct S byte S chu k M i t ng Ho t ng XRL A, @Ri S byte S chu k M i t ng Ho t ng XRL A, #data S byte S chu k M i t ng Ho t ng XRL direct, A S byte S chu k M i t ng Ho t ng
Cc d ng l nh: 1 1 01101rrr (A) (A) (Rn) 2 1 01100101 aaaaaaaa (A) (A) (direct) 1 1 0110011i (A) (A) ((Ri)) 2 1 01100100 dddddddd (A) (A) #data 2 1 01100010 aaaaaaaa (direct) (direct) (A)
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Chng 3: T p l nh c a 8051. XRL direct, #data S byte S chu k M i t ng Ho t ng Sau khi th c thi l nh XRL A, R0 th: (A)=E9H
Tr ng H Cng nghi p Tp.HCM. 3 2 01100011 aaaaaaaa dddddddd (direct) (direct) #data
V d : Cho bi t tr c (A)=C3H, (R0)=2AH, (P3)=(B0)=75H, (2AH)=55H.
Sau khi th c thi l nh XRL A, B0H hay XRL A, P3 th: (A)=B6H
Sau khi th c thi l nh XRL A, @R0 th: (A)=96H
Sau khi th c thi l nh XRL A, #2AH th: (A)=E9H
Sau khi th c thi l nh XRL B0H, A hay XRL P3, A th: (P3)=B6H
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Chng 3: T p l nh c a 8051. Sau khi th c thi l nh XRL 2AH, #B0H th: (2AH)=E5H
2AH 55H B0H
XRL 2AH, #B0H
55H XOR B0H = E5H

XOR
2AH E5H
01010101B 10110000B 11100101B
2.4. CLR A Ch c nng: Xa thanh ghi A (Clear Acc). M t : Thanh ghi A b xa (t t c cc bit u b ng 0). Cc c khng b S byte S chu k M i t ng Ho t ng V d : Cho bi t tr c (A)=5CH. Sau khi th c thi l nh CLR A th: (A)=00H 1 1 11100100 (A) 0 nh h ng. Cc d ng l nh:
2.5. CPL A Ch c nng: L y b n i dung thanh ghi A (Complement Acc). M t : M i m t bit c a thanh ghi A c l y b logic (b 1: cc bit 1 c th i thnh bit 0 v cc bit 0 c th i thnh bit 1). Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng V d : Cho bi t tr c (A)=5CH. Sau khi th c thi l nh CPL A th: (A)=A3H
CPL A
1 1 11110100 (A) NOT(A)
A 5CH
A A3H
01011100B 10100011B
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Chng 3: T p l nh c a 8051. 2.6. RL A Ch c nng: Quay tri thanh ghi A (Rotate Acc Left). M t :
8 bit trong thanh ghi A c quay tri 1 bit. Bit 7 c quay n v tr c a bit 0. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 1 1 00100011 (An+1) (An), n = 0 6 (A0) A7
V d : Cho bi t tr c (A)=C5H. Sau khi th c thi l nh RL A th: (A)=8BH
2.7. RLC A Ch c nng: Quay tri thanh ghi A cng v i c nh . M t : 8 bit trong thanh ghi A v c nh cng c quay tri 1 bit. Bit 7 c di chuy n n c CY v tr ng thi ban u c a c CY c a n v tr c a bit 0. Cc c khc khng b nh h ng. S byte S chu k M i t ng Ho t ng 1 1 00110011 (An+1) (An), n = 0 6 (A0) (C), (C) A7
V d : Cho bi t tr c (A)=C5H v c CY=0. Sau khi th c thi l nh RLC A th: (A)=8AH v c CY=1
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Chng 3: T p l nh c a 8051. 2.8. RR A Ch c nng: Quay ph i thanh ghi A (Rotate Acc Right). M t :
8 bit trong thanh ghi A c quay ph i 1 bit. Bit 0 c quay n v tr c a bit 7. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 1 1 00000011 (An) (An+1), n = 0 6 (A7) A0
V d : Cho bi t tr c (A)=C5H. Sau khi th c thi l nh RR A th: (A)=E2H
2.9. RRC A Ch c nng: Quay ph i thanh ghi A cng v i c nh . M t : 8 bit trong thanh ghi A v c nh cng c quay ph i 1 bit. Bit 0 c di chuy n n c nh v tr ng thi ban u c a c nh c a n v tr c a bit 7. Cc c khc khng b nh h ng. S byte S chu k M i t ng Ho t ng 1 1 00010011 (An) (An+1), n = 0 6 (A7) (C) (B) A0
V d : Cho bi t tr c (A)=C5H v c CY=0. Sau khi th c thi l nh RRC A th: (A)=62H v c CY=1
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Chng 3: T p l nh c a 8051. 2.10. SWAP A
Ch c nng: Tro i n i dung hai n a th p v cao c a thanh ghi A (Swap nibble). M t : SWAP A tro i n i dung hai n a th p v cao c a thanh ghi A (cc bit t 3 n 0 cc bit t 7 n 4). Thao tc ny cn c th c hi u nh l quay thanh ghi A i 4 bit. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng V d : Cho bi t tr c (A)=C5H. Sau khi th c thi l nh SWAP A th: (A)=5CH 1 1 11000100 (A3 A0) (A7 A4)
Lu :
L nh ny c th c dng chuy n i gi tr nh phn trong thanh ghi A (gi tr ny nh hn 100) thnh s BCD nh sau: MOV DIV SWAP ADD B, #10 AB A A, B ;Chia gi tr cho 10 tch ra ;(A)=digit ch c (B)=digit n v . ;a digit ch c ln n a cao c a ACC. ;Thm digit n v vo n a th p.
3. Nhm l nh di chuy n d li u: 3.1. MOV <dest-byte>, <src-byte> Ch c nng: Di chuy n n i dung c a ton h ng ngu n (src-byte) n ton h ng ch (destbyte). M t : N i dung c a byte c ch ra b i ton h ng th hai c sao chp vo v tr c xc nh b i ton h ng th nh t. Byte ngu n khng b nh h ng. Cc thanh ghi khc v cc c khng b nh h ng. MOV A, Rn S byte S chu k M i t ng Ho t ng MOV A, direct S byte S chu k M i t ng Ho t ng Lu : Gio trnh Vi x l.
Cc d ng l nh: 1 1 11101rrr (A) (Rn) 2 1 11100101 aaaaaaaa (A) (direct) MOV A, ACC l l nh khng h p l . 67 Bin so n: Ph m Quang Tr
Chng 3: T p l nh c a 8051. MOV A, @Ri S byte S chu k M i t ng Ho t ng MOV A, #data S byte S chu k M i t ng Ho t ng MOV Rn, A S byte S chu k M i t ng Ho t ng MOV Rn, direct S byte S chu k M i t ng Ho t ng MOV Rn, #data S byte S chu k M i t ng Ho t ng MOV direct, A S byte S chu k M i t ng Ho t ng MOV direct, Rn S byte S chu k M i t ng Ho t ng MOV direct, direct S byte S chu k M i t ng Ho t ng 1 1 1110011i (A) ((Ri))
2 1 01110100 dddddddd (A) #data 1 1 11111rrr (Rn) (A) 2 2 10101rrr (Rn) (direct) 2 1 01111rrr (Rn) #data
aaaaaaaa
dddddddd
2 1 11110101 aaaaaaaa (direct) (A) 2 2 10001rrr (direct) (Rn)
aaaaaaaa
3 2 10000101 aaaaaaaa aaaaaaaa (direct) (direct)
Lu : byte 2 ch a a ch ngu n, byte 3 ch a a ch ch.
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Chng 3: T p l nh c a 8051. MOV direct, @Ri S byte S chu k M i t ng Ho t ng MOV direct, #data S byte S chu k M i t ng Ho t ng MOV @Ri, A S byte S chu k M i t ng Ho t ng MOV @Ri, direct S byte S chu k M i t ng Ho t ng MOV @Ri, #data S byte S chu k M i t ng Ho t ng
Tr ng H Cng nghi p Tp.HCM. 2 2 1000011i (direct) ((Ri))
aaaaaaaa
3 2 01110101 aaaaaaaa dddddddd (direct) #data 1 1 1111011i ((Ri)) (A) 2 2 1010011i aaaaaaaa ((Ri)) (direct) 2 1 0111011i dddddddd ((Ri)) #data
V d : Cho bi t tr c (A)=5FH, (R0)=30H, (30H)=40H, (P1)=CAH. Sau khi th c thi l nh MOV A, R0 th: (A)=30H, (R0)=30H
Sau khi th c thi l nh MOV A, 30H th: (A)=40H, (30H)=40H
Sau khi th c thi l nh MOV A, @R0 th: (A)=40H, (R0)=30H, (30H)=40H
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Chng 3: T p l nh c a 8051. Sau khi th c thi l nh MOV A, #30H th: (A)=30H
Sau khi th c thi l nh MOV R0, A th: (A)=5FH, (R0)=5FH
Sau khi th c thi l nh MOV R0, P1 th: (R0)=CAH, (P1)=CAH
Sau khi th c thi l nh MOV R0, #90H th: (R0)=90H
Sau khi th c thi l nh MOV P1, A th: (A)=5FH, (P1)=5FH
Sau khi th c thi l nh MOV P1, R0 th: (R0)=30H, (P1)=30H
Sau khi th c thi l nh MOV P1, 30H th: (30H)=40H, (P1)=40H
Sau khi th c thi l nh MOV P1, @R0 th: (R0)=30H, (30H)=40H, (P1)=40H
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Chng 3: T p l nh c a 8051. Sau khi th c thi l nh MOV 30H, #30H th: (30H)=30H
Sau khi th c thi l nh MOV @R0, A th: (A)=5FH, (30H)=5FH, (R0)=30H
Sau khi th c thi l nh MOV @R0, P1: (30H)=CAH, (P1)=CAH, (R0)=30H
Sau khi th c thi l nh MOV @R0, #90H th: (30H)=90H, (R0)=30H
3.2. MOVC A, @A+ <base-reg> Ch c nng: Di chuy n byte m ho c byte h ng s . M t : MOVC n p cho thanh ghi A byte m ho c byte h ng s t b nh chng trnh. a ch c a byte c tm n p l t ng c a gi tr 8 bit khng d u ban u ch a trong thanh ghi A v i n i dung c a thanh ghi n n 16 bit (thanh ghi n n c th l con tr d li u ho c PC). Trong tr ng h p sau, thanh ghi PC c tng ch n a ch c a l nh ti p theo tr c khi c c ng v i n i dung c a thanh ghi A, cc thanh ghi n n khng b thay i. Php c ng bit th 16 do s nh t 8 bit th p c th truy n qua cc bit cao. Cc c khng b nh h ng. MOVC A, @A+DPTR S byte S chu k M i t ng Ho t ng MOVC A, @A+PC S byte S chu k M i t ng Ho t ng
Cc d ng l nh: 1 2 10010011 (A) ((A)+(DPTR)) 1 2 10000011 (A) ((A)+(PC))
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Tr ng H Cng nghi p Tp.HCM. ROM n i
V d 1: Cho bi t tr c (A)=7BH, (PC)=345H, (DPTR)=1234H. nh (3C0H)=AAH. nh ROM ngoi (12AFH)=BBH. Sau khi th c thi l nh MOVC A, @A+PC th: (A)=AAH
Sau khi th c thi l nh MOVC A, @A+DPTR th: (A)=BBH
V d 2: Cho chu i l nh sau: MOVC A, @A+PC ;(@A+PC)=([A]+[PC]) SJMP $ ; di l nh l 2 byte. DULIEU: DB 66H,77H,88H DB 99H,0AAH DB 0BBH Sau khi th c thi chu i l nh th: (A) = 66H n u tr c khi th c thi l nh ta c (A) = 02H. (A) = 77H n u tr c khi th c thi l nh ta c (A) = 03H. (A) = 88H n u tr c khi th c thi l nh ta c (A) = 04H. (A) = 99H n u tr c khi th c thi l nh ta c (A) = 05H. (A) = AAH n u tr c khi th c thi l nh ta c (A) = 06H. (A) = BBH n u tr c khi th c thi l nh ta c (A) = 07H. V d 3: Cho chu i l nh sau: MOV DPTR, #CODEDISP MOVC A, @A+DPTR ;(@A+DPTR)=([A]+[DPTR]) SJMP $ ; di l nh l 2 byte. CODEDISP: DB 48H,5AH,6BH,0A9H,0F5H,90H Sau khi th c thi chu i l nh th: (A) = 48H n u tr c khi th c thi l nh ta c (A) = 00H. (A) = 5AH n u tr c khi th c thi l nh ta c (A) = 01H. (A) = 6BH n u tr c khi th c thi l nh ta c (A) = 02H. (A) = A9H n u tr c khi th c thi l nh ta c (A) = 03H. (A) = F5H n u tr c khi th c thi l nh ta c (A) = 04H. (A) = 90H n u tr c khi th c thi l nh ta c (A) = 05H.
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Chng 3: T p l nh c a 8051. 3.3. MOVX <dest-byte>, <src-byte> Ch c nng: Di chuy n M t : b nh ngoi (Move External).
MOVX chuy n d li u gi a thanh ghi A v i n i dung c a m t byte trong b nh d li u ngoi (ta dng k hi u X n i ti p v i MOV). Cc l nh ny c chia lm 2 lo i, hai lo i ny khc nhau ch chng cung c p a ch gin ti p 8 bit hay 16 bit cho b nh d li u ngoi c dung l ng 256 byte hay 64 KB. V i lo i th nh t, s d ng thanh ghi R0 ho c R1 lu gi a ch c a d li u c n truy xu t thu c RAM ngoi. Lo i ny dng trong tr ng h p b nh RAM c dung l ng nh (t i a l 256 byte). Port 1 & Port 2 l port xu t/nh p d li u. V i lo i th hai, s d ng thanh ghi DPTR lu gi a ch c a d li u c n truy xu t thu c RAM ngoi. Lo i ny dng trong tr ng h p b nh RAM c dung l ng l n (t i a l 64 KB). Port 1 l port xu t/nh p d li u. Trong nhi u tnh hu ng ta c th tr n hai lo i trn c a l nh MOVX. M t dy RAM l n v i cc ng a ch cao c i u khi n b i P2 c th c nh a ch thng qua con tr d li u ho c v i m xu t ra cc bit a ch cao n P2 c ti p theo b i m t l nh MOVX s d ng R0 ho c R1. MOVX A, @Ri S byte S chu k M i t ng Ho t ng MOVX A, @DPTR S byte S chu k M i t ng Ho t ng MOVX @Ri, A S byte S chu k M i t ng Ho t ng MOVX @DPTR, A S byte S chu k M i t ng Ho t ng
Cc d ng l nh: 1 2 11100011i (A) ((Ri)) 1 2 11100000 (A) ((DPTR)) 1 2 11110011 ((Ri)) (A) 1 2 11110000 ((DPTR)) (A)
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V d : Cho bi t tr c (A)=AAH, (DPTR)=1234H, (R0)=34H. nh RAM ngoi 256 byte: (34H)=12H & 64 KB: (1234H)=7FH Sau khi th c thi l nh MOVX A, @R0 th: (A)=12H
Sau khi th c thi l nh MOVX @R0, A th: nh RAM ngoi (34H)=AAH
Sau khi th c thi l nh MOVX A, @DPTR th: (A)=7FH
Sau khi th c thi l nh MOVX @DPTR, A th: (1234H)=AAH
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Chng 3: T p l nh c a 8051. 3.4 MOV DPTR, #data16
Ch c nng: N p h ng s 16-bit cho con tr d li u DPTR. M t : Con tr d li u c n p b i h ng s 16-bit ch ra trong l nh. H ng s 16-bit c t byte 2 v byte 3 c a l nh. Byte 2 l byte cao c n p cho DPH cn byte 3 l byte th p c n p cho DPL. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng V d : Sau khi th c thi l nh MOV DPTR, #1234H th: 3 2 10010000 dddddddd dddddddd (DPTR) #data16
3.5. PUSH direct Ch c nng: C t vo ngn x p (stack). M t : Con tr stack c tng b i 1. N i dung c a ton h ng c ch ra trong l nh sau c sao chp vo RAM n i t i a ch c tr n b i con tr stack. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 2 2 11000000 aaaaaaaa (SP) (SP) + 1 ((SP)) (direct)
V d : C t t m th i n i dung c a thanh ghi A, B v R0 vo ngn x p. Cho bi t tr c (A)=AAH, (B)=BBH, (R0)=CCH, (SP)=5FH. PUSH A PUSH B PUSH 00H Th: (SP)=62H, (60H)=AAH, (61H)=BBH, (62H)=CCH Sau khi th c thi chu i l nh:
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3.6. POP direct Ch c nng: L y ra t ngn x p (stack). M t : N i dung c a vng RAM n i c nh a ch b i con tr stack SP c c v n i dung con tr stack c gi m b i 1. Gi tr c c sau c chuy n n byte c nh a ch tr c ti p ch ra trong l nh. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 2 2 11010000 aaaaaaaa (direct) ((SP)) (SP) (SP) 1
V d : L y l i n i dung c a thanh ghi A, B v R0 c t vo ngn x p lc u (v d trn). POP 00H POP B POP A Th: (SP)=5FH, (R0)=CCH, (B)=BBH, (A)=AAH Sau khi th c thi chu i l nh:
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Chng 3: T p l nh c a 8051. 3.7. XCH A, <byte>
Ch c nng: Tro i n i dung c a thanh ghi A v i n i dung c a m t byte M t : XCH n p cho thanh ghi A n i dung c a byte ch ra trong l nh, ng th i ghi n i dung ban u c a thanh ghi A cho byte v a nu trn. Ton h ng ngu n ng th i l ton h ng ch v ng c l i. XCH A, Rn S byte S chu k M i t ng Ho t ng XCH A, direct S byte S chu k M i t ng Ho t ng XCH A, @Ri S byte S chu k M i t ng Ho t ng
Cc d ng l nh: 1 1 11001rrr (A) (Rn) 2 1 11000101 aaaaaaaa (A) (direct) 1 1 1100011i (A) ((Ri))
V d : Cho bi t tr c (A)=3FH, (R0)=20H, (20H)=75H. Sau khi th c thi l nh XCH A, R0 th: (A)=20H, (R0)=3FH
Sau khi th c thi l nh XCH A, 20H th: (A)=75H, (20H)=3FH
Sau khi th c thi l nh XCH A, @R0 th: (A)=75H, (20H)=3FH, (R0)=20H
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Chng 3: T p l nh c a 8051. 3.8. XCHD A, @Ri Ch c nng: Tro i digit (Exchange Digit). M t :
XCHD tro i n i dung n a th p c a thanh ghi A (bi u di n m t digit s hex ho c BCD) v i n i dung n a th p c a m t byte trong RAM n i, byte ny c nh a ch gin ti p b i thanh ghi ch ra trong l nh. N a cao c a cc thanh ghi v a nu trn khng b nh h ng v cc c cng khng b nh h ng. S byte S chu k M i t ng Ho t ng 1 1 110101i (A3 A0) (Ri3 Ri0)
V d : Cho bi t tr c (A)=36H, (R0)=20H, (20H)=75H. Sau khi th c thi l nh XCHD A, @R0 th: (A)=35H, (20H)=76H
4. Nhm l nh x l bit: 4.1. CLR bit Ch c nng: Xa bit. M t : Bit c ch ra trong l nh c xa. Cc c khng b nh h ng. CLR c th thao tc trn c nh v trn m t bit b t k c nh a ch bit. CLR C S byte S chu k M i t ng Ho t ng CLR bit S byte S chu k M i t ng Ho t ng Sau khi th c thi l nh CLR C th: c CY=0
Cc d ng l nh: 1 1 11000011 (C) 0 2 1 11000010 (bit) 0
bbbbbbbb
V d : Cho bi t tr c c CY=1, (P1)=FFH.
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Chng 3: T p l nh c a 8051. Sau khi th c thi l nh CLR P1.3 th: P1.3=0 t c lm (P1)=F7H
4.2. CPL bit Ch c nng: L y b bit (Complex). M t : Bit c ch ra trong l nh c l y b. M t bit c gi tr 1 c i thnh 0 v ng c l i. Cc c khng b nh h ng. CPL c th thao tc trn c nh v trn m t bit b t k c nh a ch bit. Khi l nh ny c dng lm thay i gi tr c a m t chn xu t (b t k chn no c a m t port) th gi tr c dng lm d li u ban u c a chn c l y t b ch t d li u xu t, khng ph i c l y t chn nh p. CPL C S byte S chu k M i t ng Ho t ng CPL bit S byte S chu k M i t ng Ho t ng Sau khi th c thi l nh CPL C th: c CY=0
Lu :
Cc d ng l nh: 1 1 10110011 (C) NOT(C) 2 1 10110010 bbbbbbbb (bit) NOT(bit)
V d : Cho bi t tr c c CY=1, (P1)=FFH.
Sau khi th c thi l nh CPL P1.3 th: P1.3=0 t c lm (P1)=F7H
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Chng 3: T p l nh c a 8051. 4.3. SETB <bit> Ch c nng: Set bit b ng 1 (Set Bit). M t :
SETB set bit c ch ra trong l nh b ng 1. SETB c th thao tc trn c nh ho c cc bit b t k c nh a ch bit. Cc c khng b nh h ng. SETB C S byte S chu k M i t ng Ho t ng SETB bit S byte S chu k M i t ng Ho t ng
Cc d ng l nh: 1 1 11010011 (C) 1 2 1 11010010 (bit) 1
bbbbbbbb
V d : Cho bi t tr c c CY=0, (P1)=00H. Sau khi th c thi l nh SETB C th: c CY=1
Sau khi th c thi l nh SETB P1.3 th: P1.3=1 t c lm (P1)=08H
4.4. ANL C, <src-bit> Ch c nng: AND logic hai bit. M t : N u gi tr c a bit ngu n l 0 th l nh ny s xa CY v ng c l i n u gi tr c a bit ngu n l 1 th l nh ny gi nguyn gi tr hi n hnh c a c CY. D u g ch cho (/) t tr c ton h ng trong chng trnh h p ng ch ra r ng bit ngu n c l y b tr c khi AND v i CY nhng gi tr c a bit ngu n khng b thay i b i thao tc l y b ny. Cc c khng b nh h ng. ANL C, bit S byte S chu k M i t ng Ho t ng ANL C, /bit S byte S chu k M i t ng Gio trnh Vi x l.
Cc d ng l nh: 2 2 10000010 bbbbbbbb (C) (C) AND (bit) 2 2 10110000 80
bbbbbbbb Bin so n: Ph m Quang Tr
Chng 3: T p l nh c a 8051. Ho t ng V d : Cho bi t tr c (A)=72H, c CY=1. Sau khi th c thi l nh ANL C, ACC.7 th: c CY=0, (A)=72H
Tr ng H Cng nghi p Tp.HCM. (C) (C) AND NOT(bit)
Sau khi th c thi l nh ANL C, /ACC.7 th: c CY=1, (A)=72H
4.5. ORL C, <src-bit> Ch c nng: OR logic hai bit. M t : N u gi tr c a bit ngu n l 1 th php ton s set c CY=1 v ng c l i n u gi tr c a bit ngu n l 0 th php ton gi nguyn gi tr hi n hnh c a c CY. D u g ch cho / t tr c ton h ng trong chng trnh h p ng ch ra r ng bit ngu n c l y b tr c khi OR logic v i c nh nhng gi tr c a bit ngu n khng b thay i b i thao tc l y b. Cc c khng b nh h ng. ORL C, bit S byte S chu k M i t ng Ho t ng ORL C, /bit S byte S chu k M i t ng Ho t ng
Cc d ng l nh: 2 2 01110010 bbbbbbbb (C) (C) OR (bit) 2 2 10100000 bbbbbbbb (C) (C) OR NOT(bit)
V d : Cho bi t tr c(A)=72H, c CY=0. Sau khi th c thi l nh ORL C, ACC.7 th: c CY=0, (A)=72H
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Chng 3: T p l nh c a 8051. Sau khi th c thi l nh ORL C, /ACC.7 th: c CY=1, (A)=72H
Lu :
Cc l nh trn bao g m l nh ANL v ORL nhng khng t n t i l nh XRL. Cho nn n u ta c n XOR hai bit , BIT1 v BIT2, v k t qu c c t vo trong c nh (CY) th ta s d ng o n l nh sau y: MOV C, BIT1 ;N p BIT1 vo c nh . JNB BIT2, SKIP ;BIT2=0 th C = BIT1. CPL C ;BIT2=1 th C\ = BIT1\. SKIP: ;BIT1 XOR BIT2
4.6. MOV <dest-bit>, <src-bit> Ch c nng: Di chuy n bit ngu n (src-bit) n bit ch (dest-bit). M t : N i dung c a bit c ch ra b i ton h ng th hai c sao chp vo v tr c xc nh b i ton h ng th nh t. M t trong hai ton h ng ph i l c nh v ton h ng cn l i c th l bit b t k c nh a ch bit. Bit ngu n khng b nh h ng. Cc thanh ghi khc v cc c khng b nh h ng. MOV C, bit S byte S chu k M i t ng Ho t ng MOV bit, C S byte S chu k M i t ng Ho t ng
Cc d ng l nh: 2 1 10100010 bbbbbbbb (C) (bit) 2 2 10010010 bbbbbbbb (bit) (C)
V d : Cho bi t tr c c CY=1, (P1)=C5H. Sau khi th c thi l nh MOV C, P1.3 th: c CY=0, (P1)=C5H
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Chng 3: T p l nh c a 8051. Sau khi th c thi l nh MOV P1.3, C th: c CY=1, (P1)=CDH
4.7. JB bit, rel Ch c nng: Nh y n u bit b ng 1. M t : N u bit ch ra trong l nh b ng 1 th nh y n a ch c ch ra trong l nh cn ng c l i th ti p t c v i l nh ti p theo. Cc c khng b nh h ng, bit c ki m tra s khng b thay i. S byte S chu k M i t ng Ho t ng 3 2 00100000 bbbbbbbb eeeeeeee (PC) (PC) + 3 IF (bit) = 1 THEN (PC) (PC) + byte_2
Lu :
Lu :
T m nh y c a l nh JB bit, rel b gi i h n kho ng cch nh y t -128 byte (nh y lui) n +127 byte (nh y t i) k t l nh k ti p theo sau l nh nh y c i u ki n ny.
V d 1: Cho bi t tr c (A)=56H, (P1)=CAH. Sau khi th c thi chu i l nh: JB P1.2, AAA JB ACC.2, BBB th chng trnh c ti p t c v i l nh t i nhn BBB, (P1)=CAH v (A)=56H. V d 2: Cho chu i l nh: MOV A, #0FFH MOV P0, #9CH ; 9CH = 10011100B JB P0.7, AAA MOV A, #00H AAA: Sau khi th c thi chu i l nh th (A)=FFH, (P0)=9CH (chng trnh th c hi n l nh nh y JB P0.7, AAA). Gio trnh Vi x l. 83 Bin so n: Ph m Quang Tr
V d 3: Cho chu i l nh: MOV A, #0FFH MOV P0, #9CH ; 9CH = 10011100B JB P0.5, AAA MOV A, #00H AAA: Sau khi th c thi chu i l nh th (A)=00H, (P0)=9CH (chng trnh khng th c hi n l nh nh y JB P0.5, AAA). 4.8. JNB bit, rel Ch c nng: Nh y n u bit b ng 0. M t : N u bit ch ra trong l nh b ng 0 th nh y n a ch c ch ra trong l nh cn ng c l i th ti p t c v i l nh ti p theo. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 3 2 00110000 bbbbbbbb eeeeeeee (PC) (PC) + 3 IF (bit) = 0 THEN (PC) (PC) + byte_2
Lu :
Lu :
T m nh y c a l nh JNB bit, rel b gi i h n kho ng cch nh y t -128 byte (nh y lui) n +127 byte (nh y t i) k t l nh k ti p theo sau l nh nh y c i u ki n ny.
V d 1: Cho bi t tr c (A)=56H, (P1)=CAH. Sau khi th c thi chu i l nh: JNB P1.3, AAA JNB ACC.3, BBB th chng trnh c ti p t c v i l nh t i nhn BBB, (A)=56H v (P1)=CAH.
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V d 2: Cho chu i l nh: MOV P1, #10H MOV A, #6BH ; 6BH = 01101011B JNB ACC.5, AAA MOV P1, #01H AAA: Sau khi th c thi chu i l nh th (A)=6BH, (P1)=01H (chng trnh khng th c hi n l nh nh y JNB ACC.5, AAA). V d 3: Cho chu i l nh: MOV P1, #10H MOV E0H, #6BH ; 6BH = 01101011B JNB E2H, AAA MOV P1, #01H AAA: Sau khi th c thi chu i l nh th (A)=(E0H)=6BH, (P1)=10H (chng trnh th c hi n l nh nh y JNB E2H, AAA). 4.9. JBC bit, rel Ch c nng: Nh y n u bit b ng 1 v xa bit (lm cho bit = 0). M t : N u bit c ch ra trong l nh b ng 1 th xa bit ny v r nhnh n a ch cho trong l nh cn ng c l i th ti p t c v i l nh ti p theo. Bit s khng c xa n u bit ny l 0. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 3 2 00010000 bbbbbbbb eeeeeeee (PC) (PC) + 3 IF (bit) = 1 THEN (bit) 0 (PC) (PC) + byte_2
Lu :
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Chng 3: T p l nh c a 8051. Lu :
T m nh y c a l nh JBC bit, rel b gi i h n kho ng cch nh y t -128 byte (nh y lui) n +127 byte (nh y t i) k t l nh k ti p theo sau l nh nh y c i u ki n ny. Khi l nh ny c dng lm thay i gi tr c a m t port xu t th gi tr c dng lm d li u ban u c a port c l y t b ch t d li u xu t, khng ph i c l y t cc chn nh p.
V d 1: Cho bi t tr c (A)=56H. Sau khi th c thi chu i l nh: JBC ACC.3, AAA JBC ACC.2, BBB th chng trnh c ti p t c v i l nh t i nhn BBB v (A)=52H. V d 2: Cho chu i l nh: MOV A, #76H MOV P3, #9CH ; 9CH = 10011100B JBC P3.2, AAA MOV A, #67H AAA: Sau khi th c thi chu i l nh th (A)=76H, (P3)=98H (chng trnh th c hi n l nh nh y JBC P3.2, AAA). V d 3: Cho chu i l nh: MOV A, #76H MOV B0H, #9CH ; 9CH = 10011100B JBC B1H, AAA MOV A, #67H AAA: Sau khi th c thi chu i l nh th (A)=67H, (P3)=(B0H)=9CH (chng trnh khng th c hi n l nh nh y JBC B1H, AAA). 4.10. JC rel Ch c nng: Nh y n u c CY = 1. M t : N u c CY = 1 th nh y n a ch cho trong l nh cn ng c l i th ti p t c v i l nh ti p theo. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 2 2 01000000 eeeeeeee (PC) (PC) + 2 IF (C) = 1 THEN (PC) (PC) + byte_2
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Lu :
T m nh y c a l nh JC rel b gi i h n kho ng cch nh y t -128 byte (nh y lui) n +127 byte (nh y t i) k t l nh k ti p theo sau l nh nh y c i u ki n ny.
V d 1: Cho bi t tr c (A)=7FH, c CY=0. Sau khi th c thi chu i l nh: JC AAA ADD A,#0F7H JC BBB th chng trnh c ti p t c v i l nh t i nhn BBB, (A)=76H, c CY=1. V d 2: Cho chu i l nh: MOV A, #9AH MOV R0, #76H ADD A, R0 JC AAA MOV R0, #67H AAA: Sau khi th c thi chu i l nh th (A)=10H, (R0)=76H v c CY=1 (chng trnh th c hi n l nh nh y JC AAA). 4.11. JNC rel Ch c nng: Nh y n u c CY = 0. M t : N u c CY = 0 th nh y n a ch cho trong l nh cn ng c l i th ti p t c v i l nh ti p theo. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 2 2 01010000 eeeeeeee (PC) (PC) + 2 IF (C) = 0 THEN (PC) (PC) + byte_2
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Lu :
T m nh y c a l nh JNC rel b gi i h n kho ng cch nh y t -128 byte (nh y lui) n +127 byte (nh y t i) k t l nh k ti p theo sau l nh nh y c i u ki n ny.
V d 1: Cho bi t tr c (A)=7FH, c CY=1. Sau khi th c thi chu i l nh: JNC AAA ADD A,#26H JNC BBB th chng trnh c ti p t c v i l nh t i nhn BBB, (A)=A5H, c CY=0. V d 2: Cho chu i l nh: MOV A, #0B9H MOV R1, #52H ADD A, R1 JNC AAA MOV R1, #25H AAA: Sau khi th c thi chu i l nh th (A)=0BH, (R1)=25H v c CY=1 (chng trnh khng th c hi n l nh nh y JNC AAA).
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Chng 3: T p l nh c a 8051. 5. Nhm l nh r nhnh: 5.1. ACALL addr11 Ch c nng: G i n a ch tuy t i (Absolute Call) M t :
ACALL g i khng i u ki n m t chng trnh con t t i a ch c ch ra trong l nh (xem thm gi i thch v chng trnh con ph n 5.3). Ch r ng, chng trnh con c g i ph i c b t u trong cng kh i 2K c a b nh chng trnh v i byte u tin c a l nh theo sau l nh ACALL. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 2 2 aaa1001
aaaaaaaa
Lu : aaa = A10A8 v aaaaaaaa = A7A0 (PC) (PC) + 2 (SP) (SP) + 1 ((SP)) (PC7PC0) (SP) (SP) + 1 ((SP)) (PC15PC8) (PC10PC0) a ch trang
M t :
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Lu : Do khng gian b nh chng trnh t i a l 64KB cho nn ta c 32 trang (kh i) v m i trang b t u a ch l bin c a 2KB (nh l: 0000H, 0800H, 1000H, 1800H, , F800H).
FFFFH F800H F800H 1800H 17FFH 1000H 0FFFH 0800H 07FFH 0000H 2K trang 31 1000H 0FFFH Trang 2
A
2K trang 2 2K trang 1 2K trang 0
32 x 2K (64K)
2K trang 1
Ban o nh 64K c chia thanh 32 trang 2K
0800H 07FFH
Trang 0
V d 1: Cho bi t tr c (SP)=07H, l nh ACALL v tr 0123H v nhn AAA b nh chng trnh. L nh k ti p l nh ACALL v tr 0125H. Sau khi th c thi l nh ACALL AAA th: (SP)=09H, (PC)=0345H v 2 nh (08H)=23H, (09H)=01H. V d 2: Cho bi t tr c (SP)=07H, l nh ACALL b nh chng trnh. v tr 0800H v nhn AAA
v tr 0345H c a c a RAM n i v tr 0700H c a
Khng th th c thi l nh ACALL AAA (l i l p trnh) v l nh ACALL v nhn AAA khng n m trong cng m t trang (l nh ACALL thu c trang 1, nhn AAA thu c trang 0).
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Chng 3: T p l nh c a 8051. 5.2. LCALL addr16 Ch c nng: G i m t chng trnh con (Long Call). M t :
LCALL g i m t chng trnh con v i a ch b t u chng trnh con c ch ra trong l nh (xem thm gi i thch v chng trnh con ph n 5.3). Ch r ng, chng trnh con c th b t u b t c ni no trong khng gian b nh chng trnh 64KB. Cc c khng b nh h ng. S byte S chu k M i t ng Lu : 3 2 00010010 aaaaaaaa aaaaaaaa
byte 2 ch a cc bit a ch t A15 A8 byte 3 ch a cc bit a ch t A7 A0. Ho t ng (PC) (PC) + 3 (SP) (SP) + 1 (SP) (PC7 PC0) (SP) (SP) + 1 (SP) (PC15 PC8) (PC) addr15 addr0
M t :
LCALL AAA
64 KB AAA:
2 3
RET
V d : Cho bi t tr c (SP)=07H, l nh LCALL v tr 0123H v nhn AAA b nh chng trnh. L nh k ti p l nh ACALL v tr 0126H. Sau khi th c thi l nh LCALL AAA th: (SP)=09H, (PC)=1234H v 2 nh (08H)=26H, (09H)=01H.
v tr 1234H c a c a RAM n i
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Chng 3: T p l nh c a 8051. 5.3. RET Ch c nng: Tr v t chng trnh con (Return). M t :
RET l y l i cc byte cao v byte th p c a PC t stack, gi m con tr stack b i 2. Vi c th c thi chng trnh ti p t c v i l nh a ch ch a trong PC, trong tr ng h p t ng qut l l nh ngay sau l nh ACALL ho c LCALL. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 1 2 00100010 (PC15 PC8) ((SP)) (SP) (SP) 1 (PC7 PC0) ((SP)) (SP) (SP) 1
Lu : Chng trnh con c m t s qui nh sau: o L m t chu i g m nhi u l nh c k t h p l i v i nhau th c hi n m t cng vi c no . o B t u b ng m t NHN, do ng i l p trnh t t ra (nhn ny chnh l tn c a chng trnh con). o K t thc b ng l nh RET. o c t cu i chng trnh, pha trn ch d n k t thc chng trnh END. o Gi a chng trnh con v chng trnh chnh ph i c cch ly b ng l nh: SJMP $. SJMP MAIN (MAIN: l nhn b t k thu c chng trnh chnh). o Chng trnh con c th c g i ra nhi u l n t i b t k th i i m no, ty thu c vo ng i l p trnh yu c u (thng qua cc l nh g i ACALL, LCALL v cc tn hi u ng t). o Trong m t chng trnh c th c m t ho c nhi u chng trnh con.
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V d 1: D a vo V d 1 c a ph n 5.1. Cho bi t tr c (SP)=09H; nh RAM n i (08H)=25H v (09H)=01H . Sau khi th c thi l nh RET th: (SP)=07H v chng trnh c ti p t c v i l nh t i a ch 0125H (v tr c a l nh k ti p l nh ACALL). V d 2: D a vo V d c a ph n 5.2. Cho bi t tr c (SP)=09H; nh RAM n i (08H)=26H v (09H)=01H . Sau khi th c thi l nh RET th: (SP)=07H v chng trnh c ti p t c v i l nh t i a ch 0126H (v tr c a l nh k ti p l nh LCALL). 5.4. RETI Ch c nng: Tr v t chng trnh con ph c v ng t. M t : RETI l y l i cc byte cao v byte th p c a PC t stack, ph c h i logic ng t c th nh n cc ng t khc c cng u tin ng t v i ng t v a x l. Con tr stack c gi m b i 2. Khng c thanh ghi no khc b nh h ng; PSW khng c t ng ph c h i tr l i tr ng thi tr c khi x l ng t. Vi c th c thi chng trnh ti p t c v i l nh a ch ch a trong PC, trong tr ng h p t ng qut l l nh ngay sau i m m yu c u ng t c pht hi n. N u c m t ng t c u tin ng t th p hn ho c cng u tin ng t c treo khi l nh RETI c th c thi, m t l nh c th c thi tr c khi ng t ang treo c x l. S byte S chu k M i t ng Ho t ng 1 2 00110010 (PC15 PC8) ((SP)) (SP) (SP) 1 (PC7 PC0) ((SP)) (SP) (SP) 1
Lu :
L nh RETI tr i u khi n v chng trnh g i t m t ISR (ISR: Interrupt Service Routine: chng trnh con ph c v ng t). i m khc nhau gi a RETI v RET l RETI c bo hi u cho h th ng i u khi n ng t r ng qu trnh x l ng t xong. N u tr ng h p khng c m t ng t no c duy tr trong th i gian RETI th c thi th l nh RETI s ho t ng nh l nh RET.
V d : Cho bi t tr c (SP)=0BH; nh RAM n i (0AH)=23H v (0BH)=01H. m t tn hi u ng t c pht hi n trong l nh a ch 0123H ang th c thi. Sau khi th c thi l nh RETI th: (SP)=09H v chng trnh c ti p t c v i l nh t i a ch 0123H.
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Chng 3: T p l nh c a 8051. 5.5. AJMP addr11 Ch c nng: Nh y n a ch tuy t i (Absolute Jump). M t :
AJMP chuy n vi c th c thi chng trnh n a ch c ch ra trong l nh. Ch r ng, ch nh y n ph i trong cng kh i 2K c a b nh chng trnh v i byte u tin c a l nh theo sau l nh AJMP. S byte S chu k M i t ng 2 2 aaa00001
aaaaaaaa
Ghi ch: aaa = A10 A8 v aaaaaaaa = A7 A0 Ho t ng (PC) (PC) + 2 (PC10 PC0) a ch trang M t :
V d : Cho bi t tr c l nh AJMP v tr 0345H v nhn AAA v tr 0123H c a b nh chng trnh. Sau khi th c thi l nh AJMP AAA th: (PC)=0123H.
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Chng 3: T p l nh c a 8051. 5.6. LJMP addr16 Ch c nng: Nh y di (Long Jump). M t :
LJMP t o ra m t r nhnh khng i u ki n n a ch c ch ra trong l nh. Ch r ng, a ch ch c th b t c ni no trong khng gian a ch c a b nh chng trnh 64KB. Cc c khng b nh h ng. S byte S chu k M i t ng Lu : Ho t ng 3 2 00010010 aaaaaaaa aaaaaaaa byte 2 ch a cc bit a ch t A15A8 byte 3 ch a cc bit a ch t A7A0 (PC) addr15 addr0
M t :
V d : Cho bi t tr c l nh LJMP trnh.
v tr 0123H v nhn AAA v tr 1234H c a b nh chng
Sau khi th c thi l nh LJMP AAA th: (PC)=1234H.
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Chng 3: T p l nh c a 8051. 5.7. SJMP rel Ch c nng: Nh y ng n (Short Jump). M t :
i u khi n chng trnh r nhnh khng i u ki n n a ch c ch ra trong l nh. Ch r ng, t m nh y cho php l 128 byte tr c l nh v 127 byte sau l nh. S byte S chu k M i t ng Ho t ng 2 2 10000000 eeeeeeee (PC) (PC) + 2 (PC) (PC) + byte_2
M t :
Lu :
L nh SJMP $ l m t l nh vng l p v t n (l nh nh y t i ch ), th ng c s d ng khi c n k t thc m t chng trnh i u khi n c a chip 8051 (lu r ng cc tn hi u ng t v n ho t ng bnh th ng, v th y chnh l phng php duy nh t thot kh i vng l p v t n ny).
V d : Cho bi t tr c l nh SJMP n m t i a ch 0100H v nhn AAA n m t i a ch 0123H trong b nh chng trnh. Sau khi th c thi l nh SJMP AAA th: (PC)=0123H.
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Chng 3: T p l nh c a 8051. 5.8. JMP @A+DPTR Ch c nng: Nh y gin ti p. M t :
C ng gi tr 8-bit khng d u ch a trong thanh ghi A v i con tr 16-bit v n p k t qu t ng cho b m chng trnh PC. y chnh l a ch c a l nh k ti p c tm n p. C hai, thanh ghi A v con tr d li u u khng b thay i. Cc c khng b nh h ng. S byte S chu k M i t ng Ho t ng 1 2 01110011 (PC) (PC) + (A) + (DPTR)
V d : Cho bi t tr c (A)=00H, 02H, 04H, 06H. Sau khi th c thi chu i l nh: MOV DPTR, #JMP_TBL JMP @A+DPTR JMP_TBL: AJMP AAA AJMP BBB AJMP CCC AJMP DDD u (A)=00H, chng trnh c ti p t c v u (A)=02H, chng trnh c ti p t c v u (A)=04H, chng trnh c ti p t c v u (A)=06H, chng trnh c ti p t c v 5.9. JZ rel Ch c nng: Nh y n u n i dung thanh ghi A b ng 0. M t : N u t t c cc bit c a thanh ghi A u b ng 0 th nh y n a ch cho trong l nh cn ng c l i ti p t c v i l nh ti p theo. Cc c khng b nh h ng. N i dung thanh ghi A khng b thay i. S byte S chu k M i t ng Ho t ng 2 2 01100000 eeeeeeee (PC) (PC) + 2 IF (A) = 0 THEN (PC) (PC) + byte_2 ; di l nh l 2 byte. ; di l nh l 2 byte. ; di l nh l 2 byte. ; di l nh l 2 byte. i l nh t i nhn AAA. i l nh t i nhn BBB. i l nh t i nhn CCC. i l nh t i nhn DDD.
th:
n n n n
Lu :
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T m nh y c a l nh JZ rel b gi i h n kho ng cch nh y t -128 byte (nh y lui) n +127 byte (nh y t i) k t l nh k ti p theo sau l nh nh y c i u ki n ny.
V d : Cho bi t tr c (A)=01H. Sau khi th c thi chu i l nh: JZ AAA DEC A JZ BBB th chng trnh c ti p t c v i l nh t i nhn BBB. 5.10. JNZ rel Ch c nng: Nh y n u n i dung thanh ghi A khc 0. M t : N u thanh ghi A c m t bit b t k b ng 1 th nh y n a ch cho trong l nh cn ng c l i ti p t c v i l nh ti p theo. Cc c khng b nh h ng. N i dung thanh ghi A khng b thay i. S byte S chu k M i t ng Ho t ng 2 2 01110000 eeeeeeee (PC) (PC) + 2 IF (A) < > 0 THEN (PC) (PC) + byte_2
Lu :
Lu :
T m nh y c a l nh JNZ rel b gi i h n kho ng cch nh y t -128 byte (nh y lui) n +127 byte (nh y t i) k t l nh k ti p theo sau l nh nh y c i u ki n ny.
V d : Cho bi t tr c (A)=00H. Sau khi th c thi chu i l nh: JNZ AAA INC A JNZ BBB th chng trnh c ti p t c v i l nh t i nhn BBB.
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Chng 3: T p l nh c a 8051. 5.11. CJNE <dest-byte>, <src-byte>, rel Ch c nng: So snh v nh y n u khng b ng. M t :
CJNE so snh gi tr c a 2 ton h ng (src-byte) v (dest-byte) r i r nhnh n a ch c ch ra trong l nh n u cc gi tr c a 2 ton h ng ny khng b ng nhau. C CY = 1 n u gi tr nguyn khng d u c a (dest- byte) nh hn gi tr nguyn khng d u c a (src-byte) v ng c l i CY = 0. Khng c ton h ng no trong 2 ton h ng b nh h ng. CJNE A, direct, rel S byte S chu k M i t ng Ho t ng
Cc d ng l nh: 3 2 10110101 aaaaaaaa eeeeeeee (PC) (PC) + 3 IF (A) < > (direct) THEN (PC) (PC) + a ch tng i IF (A) < (direct) THEN (C) 1 ELSE (C) 0 3 2 10110100 dddddddd eeeeeeee (PC) (PC) + 3 IF (A) < > #data THEN (PC) (PC) + a ch tng i IF (A) < #data THEN (C) 1 ELSE (C) 0 3 2 10111rrr dddddddd eeeeeeee (PC) (PC) + 3 IF (Rn) < > #data THEN (PC) (PC) + a ch tng i IF (Rn) < #data THEN (C) 1 ELSE (C) 0
CJNE A, #data, rel S byte S chu k M i t ng Ho t ng
CJNE Rn, #data, rel S byte S chu k M i t ng Ho t ng
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Chng 3: T p l nh c a 8051. CJNE @Ri, #data, rel S byte S chu k M i t ng Ho t ng
Tr ng H Cng nghi p Tp.HCM. 3 2 1011011i dddddddd eeeeeeee (PC) (PC) + 3 IF ((Ri)) < > #data THEN (PC) (PC) + a ch tng i IF ((Ri)) < #data THEN (C) 1 ELSE (C) 0
Lu :
V d 1: Cho bi t tr Sau khi th c thi chu i l nh: CJNE CJNE th chng trnh c ti p t
c (A)=34H, (01H)=(R1)=34H, (34H)=B9H. A, 01H, AAA @R1, #9BH, BBB c v i l nh t i nhn BBB v c C=0.
V d 2: Cho chu i l nh: CLR C MOV A, #40H MOV 40H, #0B1H CJNE A, 40H, AAA MOV 40H, #1BH AAA: ADDC A, 40H Sau khi th c thi chu i l nh th (A)=F2H, (40H)=B1H, CY=0.
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V d 3: ng d ng cho php so snh l n hn hay nh hn. Gi s : o Khi ta mu n nh y n nhn BIG n u (A) #20H, th cc l nh sau c s d ng: CJNE A, #20H, $+3 ;So snh (A) v i con s 20H. JNC BIG ;Nh y n BIG n u (A) #20H. o Khi ta mu n nh y n nhn SMALL n u (A) < #20H, th cc l nh sau c s d ng: CJNE A, #20H, $+3 ;So snh (A) v i con s 20H. JC SMALL ;Nh y n SMALL n u (A) < #20H. Lu : K hi u $ l m t k hi u c a trnh d ch h p ng , bi u th a ch c a l nh hi n hnh (v CJNE c di l nh l 3 byte nn $+3 s l a ch c a l nh ti p theo CJNE, t c l l nh JC/JNC). 5.12. DJNZ <byte>, <rel-addr> Ch c nng: Gi m v nh y n u byte khc 0. M t : DJNZ gi m byte ch ra b i ton h ng u trong l nh v r nhnh n a ch c ch ra b i ton h ng th hai trong l nh n u k t qu sau khi gi m khc 0. N u gi tr ban u c a byte l 00H ta s c trn sang 0FFH. Cc c khng b nh h ng. DJNZ Rn, rel S byte S chu k M i t ng Ho t ng
Cc d ng l nh: 2 2 11011rrr eeeeeeee (PC) (PC) + 2 (Rn) (Rn) 1 IF (Rn) < > 0 THEN (PC) (PC) + byte_2 3 2 11010101 aaaaaaaa eeeeeeee (PC) (PC) + 2 (direct) (direct) 1 IF (direct) < > 0 THEN (PC) (PC) + byte_2
DJNZ direct, rel S byte S chu k M i t ng Ho t ng
Lu :
Khi l nh ny c dng lm thay i gi tr c a m t port xu t th gi tr c dng lm d li u ban u c a port c l y t b ch t d li u xu t, khng ph i c l y t cc chn nh p.
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Lu :
Khi l nh DJNZ c th c hi n th gi tr trong thanh ghi Rn c gim (-1) tr c khi em ra so snh v i gi tr 0.
V d 1: Cho chu i l nh sau: MOV A, #50 MOV R2, #8 AAA: ADD A, #1 DJNZ R2, AAA Sau khi th c thi chu i l nh th (A)=58, (R2)=0. V d 2: Cho chu i l nh sau: MOV A, #50 MOV R3, #56 AAA: ADD A, #1 DJNZ R3, AAA Sau khi th c thi chu i l nh th (A)=106, (R1)=0. V d 3: Cho chu i l nh sau: MOV A, #50 MOV R1, #0 AAA: ADD A, #1 DJNZ R1, AAA Sau khi th c thi chu i l nh th (A)=50, (R1)=0. Lu r ng: Qua ba v d v l nh DJNZ trn cho ta m t nh n xt nh sau: o N u (Rn)=8 L nh ADD c th c hi n 8 l n. o N u (Rn)=56 L nh ADD c th c hi n 56 l n. o N u (Rn)=0 L nh ADD c th c hi n 256 l n. 5.13. NOP Ch c nng: Khng lm g (No Operation). M t : Vi c th c thi chng trnh ti p t c v i l nh ti p theo. Khng c thanh ghi hay c no b nh h ng. S byte S chu k M i t ng Ho t ng Gio trnh Vi x l. 1 1 00000000 (PC) (PC) + 1 102 Bin so n: Ph m Quang Tr
Danh sch cc l nh lm nh h ng t i cc c CY, AC v OV
Ghi ch:
X l c tng ng b nh h ng. 0 l c tng ng b ng 0. 1 l c tng ng b ng 1. NG D NG V T P L NH:
IV. CC V D
V d 1: Vi t o n l nh xa thanh ghi A v sau c ng 9 vo thanh ghi A 10 l n. Sau khi hon t t th c t gi tr trong thanh ghi A vo thanh ghi R7. Gi i MOV A, #0 ;Xo ACC, A = 0. MOV R0, #10 ;N p s l n l p, R0 = 10. BACK: ADD A, #9 ;C ng thm 9 vo ACC. DJNZ R0, BACK ;Ki m tra s l n l p l i, 10 l n. MOV R7, A ;C t ACC vo thanh ghi R7. V d 2: Vi t o n l nh n p vo thanh ghi A v i gi tr FFH v sau l y b thanh ghi A 500 l n. Gi i MOV A, #0FFH ;N p A = FFH. MOV R0, #10 ;N p s l n l p 1, R0 = 10. LOOP: MOV R1, #50 ;N p s l n l p 2, R1 = 50. BACK: CPL A ;L y b ACC. DJNZ R1, BACK ;Ki m tra s l n l p 2 (vng trong), 50 l n. DJNZ R0, LOOP ;Ki m tra s l n l p 1(vng ngoi), 10 l n.
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V d 3: Vi t o n l nh xc nh xem R0 c ch a gi tr 0 hay khng? N u khng th n p vo R0 gi tr FFH. Gi i MOV A, R0 ;Chuy n n i dung R5 vo A. JNZ NEXT ;Nh y n NEXT n u A ? 0 (thot ra). MOV R0, #0FFH ;N p R0 = FFH n u A = 0. NEXT: V d 4: Vi t o n l nh tm t ng c a 79H, F5H v E2H. Ghi byte th p c a t ng vo R0 v byte cao c a t ng vo R1. Gi i MOV A, #0 ;Xo ACC, A = 0. MOV R1, #0 ;Xo R1, R1 = 0. ADD A, #79H ;C ng thm 79H (A = 79H, CY = 0). JNC NO_CY1 ;Nh y n u CY = 0. INC R1 ;N u CY = 1 th tng R1. NO_CY1: ADD A, #0F5H ;C ng thm F5H (A = 6EH, CY =1). JNC NO_CY2 ;Nh y n u CY = 0. INC R1 ;N u CY = 1 th tng R1. NO_CY2: ADD A, #0E2H ;C ng thm E2H (A = 50H, CY = 1). JNC NO_CY3 ;Nh y n u CY = 0. INC R1 ;N u CY = 1 th tng R1. NO_CY3: MOV R0, A ;R0 = 50H (byte th p), R1 = 02H (byte cao). V d 5: H th ng s d ng 8051 c t n s dao ng c a th ch anh l 11,0592MHz. Hy xc nh th i gian c n thi t th c hi n cc l nh sau: MOV R3, #55H DEC R3 DJNZ R2, AAA LJMP AAA SJMP AAA NOP MUL AB Gi i Chu k my: 12 12 TMachine = = = 1,085(s ) f OSC 11,0592MHz L nh: MOV R3, #55H DEC R3 DJNZ R2, AAA LJMP AAA SJMP AAA NOP MUL AB S chu k my: 1 1 2 2 2 1 4 Th i gian th c hi n: t = 1 x 1,085 ( s) = 1,085 ( t = 1 x 1,085 ( s) = 1,085 ( t = 2 x 1,085 ( s) = 2,17 ( t = 2 x 1,085 ( s) = 2,17 ( t = 2 x 1,085 ( s) = 2,17 ( t = 1 x 1,085 ( s) = 1,085 ( t = 4 x 1,085 ( s) = 4,34 (
s) s) s) s) s) s) s)
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V d 6: H th ng s d ng 8051 c t n s dao ng c a th ch anh l 11,0592MHz. Hy xc nh th i gian c n thi t th c hi n hon t t o n l nh sau: MOV A, #55H MOV P1, A CPL A END Gi i Chu k my: 12 12 TMachine = = = 1,085(s ) f OSC 11,0592MHz S chu k my: o n l nh: MOV A, #55H 1 MOV P1, A 1 CPL A 1 END T ng th i gian th c hi n o n l nh trn l: t = (1 + 1 + 1) x 1,085 ( s) = 3,255 ( s) V d 7: H th ng s d ng 8051 c t n s dao ng c a th ch anh l 11,0592MHz. Hy xc nh th i gian c n thi t th c hi n hon t t o n l nh sau: DELAY: MOV R3, #200 DJNZ R3, $ RET Gi i Chu k my: 12 12 TMachine = = = 1,085(s ) f OSC 11,0592MHz o n l nh: S chu k my: DELAY: MOV R3, #200 1 DJNZ R3, $ 2 RET 1 T ng th i gian th c hi n o n l nh trn l: t = [1 + (2 x 200) + 1] x 1,085 ( s) = 436,17 ( s)
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V d 8: H th ng s d ng 8051 c t n s dao ng c a th ch anh l 11,0592 MHz. Hy xc nh th i gian c n thi t th c hi n hon t t o n l nh sau: Gi i Chu k my:
TMachine =
o n l nh:
12 12 = = 1,085(s ) f OSC 11,0592MHz

S chu k my:
DELAY: MOV R3, #250 1 HERE: NOP 1 NOP 1 NOP 1 NOP 1 DJNZ R3, HERE 2 RET 1 T ng th i gian th c hi n o n l nh trn l: t = [1 + ((1 + 1 + 1 + 1 + 2) x 250) + 1] x 1,085 ( s) = 1629,67 ( s) V d 9: Vi t o n l nh c?t gi tr c a thanh ghi R5, R6 v A vo ngn x p. Sau l y ra v cho l n l t vo cc thanh ghi R2, R3 v B tng ng. Gi i PUSH 05H ;C t R5 vo ngn x p. PUSH 06H ;C t R6 vo ngn x p. PUSH 0E0H ;C t ACC vo ngn x p. POP 0F0H ;L y t ngn x p cho vo B, (B) = (A). POP 03H ;L y t ngn x p cho vo R3, (R3) = (R6). POP 02H ;L y t ngn x p cho vo R2, (R2) = (R5). V d 10: Vi t o n l nh chuy n gi tr trong nh c a ch 55H vo cc nh RAM t i a ch t 40H 44H, s d ng: o Ch nh a ch tr c ti p. o Ch nh a ch gin ti p (khng dng vng l p). o Ch nh a ch gin ti p (dng vng l p). Gi i Ch nh a ch tr c ti p: MOV A, #55H ;N p gi tr 55H vo thanh ghi A. MOV 40H, A ;Sao n i dung c a A vo nh 40H. MOV 41H, A ;Sao n i dung c a A vo nh 41H. MOV 42H, A ;Sao n i dung c a A vo nh 42H. MOV 43H, A ;Sao n i dung c a A vo nh 43H. MOV 44H, A ;Sao n i dung c a A vo nh 44H.
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Ch nh a ch gin ti p (khng dng vng l p): MOV A, #55H ;N p gi tr 55H vo thanh ghi A. MOV R0, #40H ;N p a ch b t u, R0 = 40H. MOV @R0, A ;Sao n i dung A vo nh do R0 tr INC R0 ;Tng con tr , R0 = 41H. MOV @R0, A ;Sao n i dung A vo nh do R0 tr INC R0 ;Tng con tr , R0 = 42H. MOV @R0, A ;Sao n i dung A vo nh do R0 tr INC R0 ;Tng con tr , R0 = 43H. MOV @R0, A ;Sao n i dung A vo nh do R0 tr INC R0 ;Tng con tr , R0 = 44H. MOV @R0, A ;Sao n i dung A vo nh do R0 tr
n. n. n. n. n.
Ch nh a ch gin ti p (dng vng l p): MOV A, #55H ;N p gi tr 55H vo thanh ghi A. MOV R0, #40H ;N p a ch b t u, R0 = 40H. MOV R1, #5 ;N p s l n l p l i, R1 = 5. LOOP: MOV @R0, A ;Sao n i dung A vo nh do R0 tr n. INC R0 ;Tng con tr . DJNZ R1, LOOP ;Ki m tra s l n l p cho n khi s l n = 0. V d 11: Vi t o n l nh xa 16 nh RAM n i c a ch b t u t 60H. Gi i CLR A ;Xo ACC, A = 0. MOV R0, #60H ;N p a ch b t u, R0 = 60H. MOV R1, #16 ;N p s l n l p l i, R1 = 16. LOOP: MOV @R0, A ;Sao n i dung A vo nh do R0 tr n. INC R0 ;Tng con tr . DJNZ R1, LOOP ;Ki m tra s l n l p cho n khi s l n = 0. V d 12: Vi t o n l nh chuy n m t kh i d li u g m 10 byte t v tr nh RAM n i b t u t i a ch 35H n cc v tr nh RAM n i b t u t i a ch 60H. Gi i MOV R0, #35H ;N p a ch b t u (ngu n), R0 = 35H. MOV R1, #60H ;N p a ch b t u (ch), R1 = 60H. MOV R2, #10 ;N p s l n l p l i, R2 = 5. LOOP: MOV A, @R0 ;Sao n i dung nh do R0 tr n vo A. MOV @R1, A ;Sao n i dung A vo nh do R1 tr n. INC R0 ;Tng con tr (ngu n). INC R1 ;Tng con tr (ch). DJNZ R2, LOOP ;Ki m tra s l n l p cho n khi s l n = 0.
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V d 13: Gi s ch DHCN c lu trong ROM n i t i vng nh c a ch b t u l 200H. Hy phn tch cch chng trnh sau y ho t ng v xc nh xem ch DHCN s c lu vo u sau khi chng trnh hon t t? ORG 0000H ; a ch lu chng trnh trong ROM. MOV DPTR, #200H ;N p con tr vng d li u, DPTR=200H. CLR A ;Xo ACC, A = 0. MOVC A, @A+DPTR ;L y d li u t i nh ROM do ;(A+DPTR) = 200H tr n a vo A. MOV R0, A ;C t d li u vo R0. INC DPTR ;Tng con tr , DPTR=201H. CLR A ;Xo ACC, A = 0. MOVC A, @A+DPTR ;L y d li u t i nh ROM do ;(A+DPTR) = 201H tr n a vo A. MOV R1, A ;C t d li u vo R1. INC DPTR ;Tng con tr , DPTR=202H. CLR A ;Xo ACC, A = 0. MOVC A, @A+DPTR ;L y d li u t i nh ROM do ;(A+DPTR) = 202H tr n a vo A. MOV R2, A ;C t d li u vo R2. INC DPTR ;Tng con tr , DPTR=203H. CLR A ;Xo ACC, A = 0. MOVC A, @A+DPTR ;L y d li u t i nh ROM do ;(A+DPTR) = 203H tr n a vo A. MOV R3, A ;C t d li u vo R3. SJMP $ ;D ng chng trnh. ORG 200H ; a ch lu chng trnh trong ROM. MYDATA: DB DHCN ;Khai bo d li u. END ;K t thc chng trnh. Gi i Theo chng trnh trn, cc nh c a b nh chng trnh (ROM) c a ch 200H - 203H ch a cc n i dung sau: (200H) = 44H = D, (201H) = 48H = H, (202H) = 43H = C, (203H) = 4EH = N. u tin v i (DPTR) = 200H v (A) = 0. L nh MOVC A, @A+DPTR chuy n n i dung c a nh c a ch 200H (A + DPTR = 0 + 200H) trong ROM vo A. Thanh ghi A lc ny s ch a gi tr 44H l m ASCII c a k t D. K t ny c c t vo thanh ghi R0. Ti p theo, DPTR c tng ln (DPTR = 201H) v A c xo (A = 0) l y n i dung c a v tr nh k ti p trong ROM c a ch l 201H (A + DPTR = 0 + 200H) vo A. Thanh ghi A lc ny s ch a gi tr 48H l m ASCII c a k t H. K t ny c c t vo thanh ghi R1. Qu trnh di n ra tng t nh v y, sau khi hon t t chng trnh ta c (R0) = 44H, (R1) = 48H, (R2) = 43H, (R3) = 4EH l m ASCII c a cc k t D, H, C v N.
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V d 14: Gi s ch TP.HCM c lu trong ROM n i t i vng nh c a ch b t u l 200H. Hy vi t chng trnh chuy n cc byte d li u ny vo cc nh RAM n i b t u t a ch 40H. Gi i Phng php s d ng b m d li ORG 0000H MOV DPTR, #MYDATA MOV R0, #40H MOV R1, #6 LOOP: CLR A MOVC A, @A+DPTR MOV INC INC DJNZ SJMP ORG MYDATA: DB END @R0, A DPTR R0 R1, LOOP $ 200H TP.HCM u: ; a ch lu chng trnh trong ROM. ;N p con tr vng d li u. ;N p a ch b t u ch a trong RAM. ;N p gi tr b m (s l ng k t ). ;Xo ACC, A = 0 ;L y d li u t i nh ROM do ;(A+DPTR) tr n a vo A. ;C t vo nh RAM do R0 tr n. ;Tng con tr d li u. ;Tng a ch vng RAM. ;L p l i cho n khi b m = 0. ;D ng chng trnh. ; a ch lu chng trnh trong ROM. ;Khai bo d li u. ;K t thc chng trnh.
Phng php s d ng k t NULL k t thc chu i: ORG 0000H ; a ch lu chng trnh trong ROM. MOV DPTR, #MYDATA ;N p con tr vng d li u. MOV R0, #40H ;N p a ch b t u ch a trong RAM. LOOP: CLR A ;Xo ACC, A = 0 MOVC A, @A+DPTR ;L y d li u t i nh ROM do ;(A+DPTR) tr n a vo A. JZ EXIT ;Thot ra n u c k t NULL. MOV @R0, A ;C t vo nh RAM do R0 tr n. INC DPTR ;Tng con tr d li u. INC R0 ;Tng a ch vng RAM. SJMP LOOP ;L p l i. EXIT: SJMP $ ;D ng chng trnh. ORG 200H ; a ch lu chng trnh trong ROM. MYDATA: DB TP.HCM, 0 ;Khai bo d li u, c k t NULL. END ;K t thc chng trnh.
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V d 15: Vi t chng trnh l y gi tr x t P1 v lin t c g i gi tr x2 n P2. Gi i ORG 0000H ; a ch lu chng trnh trong ROM. MOV DPTR, #MYDATA ;N p con tr vng d li u. MOV P1, #0FFH ;C u hnh P1 l port nh p. LOOP: MOV A, P1 ;L y s li u x t P1. MOVC A, @A+DPTR ;L y gi tr x2 t vng d li u. MOV P2, A ;Xu t gi tr x2 ra P2. SJMP LOOP ;L p l i. ORG 200H ; a ch lu chng trnh trong ROM. MYDATA: ;Vng d li u tng ng t 02 - 92. DB 0,1,4,9,16,25,36,49,64,81 END V d 16: Vi t o n l nh tnh t ng cc gi tr c a cc nh RAM n i c a ch 40H 44H. K t qu byte th p c t vo thanh ghi A v byte cao c t vo thanh ghi B. Gi i MOV R0, #40H ;N p a ch b t u ch a trong RAM. MOV R1, #5 ;N p gi tr b m (s l ng nh ). CLR A ;Xo ACC, A = 0. MOV B, A ;Xo thanh ghi B, B = 0 LOOP: ADD A, @R0 ;C ng n i dung nh do R0 tr n vo A. JNC NO_CY ;Nh y n u khng c nh , CY = 0. INC B ;Tng thanh ghi B n u c nh , CY = 1. NO_CY: INC R0 ;Tng con tr n nh k ti p. DJNZ R1, LOOP ;L p l i cho n khi b m = 0. V d 17: Vi t o n l nh tnh t ng hai s 16 bit l 3CE7H v 3B8DH. C t k t qu vo R7 (byte cao) v R6 (byte th p). Gi i CLR C ;Xo c nh , CY = 0. MOV A, #0E7H ;N p byte th p 1 vo A, A = E7H. ADD A, #8DH ;C ng byte th p 2 vo A, A = 74H, CY = 1. MOV R6, A ;Lu byte th p c a t ng vo R6. MOV A, #3CH ;N p byte cao 1 vo A, A = 3CH. ADDC A, #3BH ;C ng c nh byte cao 2 vo A, A = 78H. MOV R7, A ;Lu byte cao c a t ng vo R7.
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V d 18: Vi t o n l nh tnh t ng c a 5 d li u BCD c lu trong RAM n i t i a ch b t u t 40H nh sau: (40H) = 71H, (41H) = 11H, (42H) = 65H, (43H) = 59H, (44H) = 37H. K t qu c lu vo thanh ghi R7 (byte cao) v thanh ghi A (byte th p) d i d ng s BCD. Gi i MOV R0, #40H ;N p a ch b t u ch a trong RAM. MOV R1, #5 ;N p gi tr b m (s l ng nh ). CLR A ;Xo ACC, A = 0. MOV R7, A ;Xo thanh ghi R7, R7 = 0 LOOP: ADD A, @R0 ;C ng n i dung nh do R0 tr n vo A. DA A ;Hi u ch nh thnh s BCD. JNC NO_CY ;Nh y n u khng c nh , CY = 0. INC R7 ;Tng thanh ghi R7 n u c nh , CY = 1. NO_CY: INC R0 ;Tng con tr n nh k ti p. DJNZ R1, LOOP ;L p l i cho n khi b m = 0. V d 19: Vi t o n l nh nh n d li u d i d ng s HEX trong ph m vi 00H FFH t Port 1 v chuy n i v d ng th p phn. Lu cc s vo cc thanh ghi R7 (LSB), R6 v R5 (MSB). Gi i MOV P1, #0FFH ;C u hnh P1 l port nh p. MOV A, P1 ; c d li u t P1. MOV B, #10 ;N p B = 10. DIV AB ;Chia cho 10, tch l y s cao/s th p. MOV R7, B ;Lu gi tr hng n v vo R7. MOV B, #10 ;N p B = 10. DIV AB ;Chia cho 10, tch l y s cao/s th p. MOV R6, B ;Lu gi tr hng ch c vo R6. MOV R5, A ;Lu gi tr hng trm vo R5. V d 20: Vi t o n l nh c v ki m tra Port 1 xem c ch a gi tr 45H hay khng? N u (P1) = 45H th xu t gi tr 99H ra Port 2, ng c l i th thot kh i o n l nh. Gi i MOV P2, #00H ;Xo P2, P2 = 0. MOV P1, #0FFH ;C u hnh P1 l port nh p. MOV R0, #45H ;N p R0 = 45H, gi tr c n ki m tra. MOV A, P1 ; c d li u t P1. XRL A, R0 ;Ki m tra d li u c b ng 45H, n u b ng th JNZ EXIT ;A = 0, khng b ng th A ? 0. MOV P2, #99H ;N p P2 = 99H n u P1 = 45H (A = 0). EXIT: V d 21: Vi t o n l nh l y b 2 gi tr ch a trong thanh ghi R0. Gi i MOV A, R0 ;N p d li u c n l y b vo A. CPL A ;L y b 1. ADD A, #1 ;C ng thm 1 c b 2.
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V d 22: Vi t o n l nh ki m tra thanh ghi A xem c ch a gi tr 99H hay khng? N u (A) = 99H th n p gi tr FFH vo thanh ghi R1, ng c l i th n p gi tr 00H vo thanh ghi R1. Gi i MOV R1, #0 ;N p R0 = 00H. CJNE A, #99H, NEXT ;So snh A v i gi tr 99H, n u khng ;b ng th nh y n NEXT. MOV R1, #0FFH ;N p R0 = FFH n u A = 99H. NEXT: V d 23: Gi s m t c m bi n nhi t c n i t i ng vo P1. Hy vi t o n l nh c nhi t v so snh v i gi tr 75. D a vo k t qu ki m tra t gi tr nhi t vo cc thanh ghi nh sau: N u t = 75OC th (A) = 75. N u t < 75OC th (R1) = t. N u t > 75OC th (R2) = t. Gi i MOV P1, #0FFH ;C u hnh P1 l port nh p. MOV A, P1 ; c d li u (t) t P1. CJNE A, #75, OVER ;So snh d li u (t) v i gi tr 75, n u ;khng b ng th nh y n OVER. SJMP EXIT ;N u A = 75 th thot chng trnh. OVER: ;Tr ng h p khi d li u (t) khc 75. JNC NEXT ;Nh y n NEXT n u d li u (t) > 75, C=0. MOV R1, A ;N u d li u (t) < 75 th n p d li u vo SJMP EXIT ;R1 (R1 = A = t) v thot chng trnh. NEXT: ;Tr ng h p khi d li u (t) > 75. MOV R2, A ;N p d li u vo R2 (R2 = A = t). EXIT: V d 24: Vi t o n l nh lin t c ki m tra gi tr t i Port 1 n u gi tr ny khc 63H. N u (P1) = 63H th thot o n l nh khng ki m tra n a. Gi i MOV P1, #0FFH ;C u hnh P1 l port nh p. HERE: MOV A, P1 ; c d li u t P1. CJNE A, #63H, HERE ;Duy tr ki m tra n khi P1 = 63H.
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V d 25: Gi s cc nh trong RAM n i c a ch t 40H 44H ch a nhi t c a cc ngy c ch ra d i y. Hy vi t o n l nh ki m tra xem c gi tr no b ng 65 khng? N u c th t a ch c a nh vo R4, ng c l i th t R4 = 0. (40H) = 76, (41H) = 79, (42H) = 69, (43H) = 65, (44H) = 64 Gi i MOV R4, #0 ;Xo R4 = 0. MOV R0, #40H ;N p a ch b t u ch a trong RAM. MOV R1, #5 ;N p gi tr b m (s l ng nh ). MOV A, #65 ;N p gi tr c n tm vo A, A = 65. BACK: CJNE A, @R0, NEXT ;So snh d li u do R0 tr n v i 65. MOV R4, R0 ;N u b ng th lu a ch nh vo R4. SJMP EXIT ;Thot chng trnh. NEXT: ;Tr ng h p d li u do R0 tr n khc 65. INC R0 ;Tng con tr n nh k ti p. DJNZ R2, BACK ;L p l i cho n khi b m b ng 0. EXIT: V d 26: Vi t o n l nh tm t ng cc ch s 1 trong thanh ghi R0. Gi i MOV R1, #0 ;Xo R1 = 0, lu s ch s 1. MOV R2, #8 ;N p gi tr b m (s bit ki m tra). MOV A, R0 ;N p d li u c n ki m tra t R0 vo A. LOOP: RLC A ;Xoay tri, a bit c n ki m tra vo c CY. JNC NEXT ;Ki m tra c CY. INC R1 ;Tng gi tr c a R1 n u c CY = 1. NEXT: DJNZ R2, LOOP ;L p l i cho n khi b m b ng 0. V d 27: Vi t o n l nh chuy n i s BCD nn ch a trong thanh ghi A thnh hai s ASCII v ch a hai s ny trong thanh ghi R2 v R3. Gi i MOV A, #29H ;N p A = 29H, m BCD nn c a s 29. MOV R2, A ;Lu l i s BCD c n chy n i trong R2. ANL A, #0FH ;Xo (che) 4 bit cao c a s BCD (A = 09H). ORL A, #30H ;Chuy n thnh m ASCII (A = 39H). MOV R3, A ;C t vo R3 (R3 = 39H m ASCII c a 9). MOV A, R2 ;L y l i s BCD lc ban u (A = 29H). ANL A, #0F0H ;Xo (che) 4 bit th p c a s BCD (A=20H). SWAP A ;Hon chy n v tr 4 bit cao v p bit th p. ORL A, #30H ;Chuy n thnh m ASCII (A = 32H). MOV R2, A ;C t vo R2 (R2 = 32H m ASCII c a 2).
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V d 28: Gi s bit P2.3 l m t u vo v bi u di n nhi t c a m t l s y. N u P2.3 = 1 c ngha l l qu nng. Hy lin t c ki m tra bit ny, n u nhi t qu cao th hy g i m t xung m c cao n P1.5 b t ci bo hi u. Gi i JNB P2.3, $ ;Duy tr ki m tra u vo. SETB P1.5 ;Khi P2.3 = 1, t o m c cao cho P1.5 r i CLR P1.5 ;t o m c th p cho P1.5, pht m t xung. V d 29: Vi t o n l nh ki m tra xem thanh ghi A c ch a m t s ch n hay khng? N u c th chia cho 2, n u khng th tng ln 1 ch n ho s r i chia n cho 2. Gi i MOV B, #2 ;Gn s chia, B = 2. JNB ACC.0, OK ;Ki m tra n u l s ch n th nh y n OK. INC A ;Ch n ho n u l s l . OK: DIV AB ;Chia A cho 2. V. PH N BI T P: Truy xu t RAM n i (theo 2 cch: nh a ch nh tr c ti p v gin ti p): Bi 1: Vi t o n l nh ghi (chuy n) gi tr 40H vo nh 30H c a RAM n i. Bi 2: Vi t o n l nh xa n i dung nh 31H c a RAM n i. Bi 3: Vi t o n l nh ghi (chuy n) n i dung thanh ghi A vo nh 32H c a RAM n i. Bi 4: Vi t o n l nh ghi (chuy n) n i dung nh 33H c a RAM n i vo thanh ghi A. Bi 5: Vi t o n l nh ghi (chuy n) n i dung nh 34H c a RAM n i vo nh 35H c a RAM n i. Bi 6: Vi t o n l nh ghi (chuy n) n i dung thanh ghi R4 vo nh 36H c a RAM n i. Bi 7: Vi t o n l nh ghi (chuy n) n i dung nh 37H c a RAM n i vo thanh ghi R5. Bi 8: Vi t o n l nh ghi (chuy n) n i dung thanh ghi A vo thanh ghi R1. Bi 9: Vi t o n l nh ghi (chuy n) n i dung thanh ghi R2 vo thanh ghi A. Bi 10: Vi t o n l nh ghi (chuy n) gi tr ABH vo thanh ghi A. Bi 11: Vi t o n l nh ghi (chuy n) gi tr CDH vo thanh ghi R3. Truy xu t RAM ngoi: Bi 1: Vi t o n l nh ghi (chuy n) gi tr 40H vo nh 30H c a RAM ngoi (RAM ngoi c dung l ng 256 byte). Bi 2: Vi t o n l nh xa nh 31H c a RAM ngoi (RAM ngoi c dung l ng 256 byte). Bi 3: Vi t o n l nh ghi (chuy n) n i dung nh 32H c a RAM ngoi vo thanh ghi A (RAM ngoi c dung l ng 256 byte). Bi 4: Vi t o n l nh ghi (chuy n) n i dung thanh ghi A vo nh 33H c a RAM ngoi (RAM ngoi c dung l ng 256 byte). Bi 5: Vi t o n l nh chuy n d li u nh 34H c a RAM ngoi vo nh 35H c a RAM ngoi (RAM ngoi c dung l ng 256 byte). Gio trnh Vi x l. 114 Bin so n: Ph m Quang Tr
Bi 6: Vi t o n l nh ghi (chuy n) gi tr 40H vo nh 1230H c a RAM ngoi (RAM ngoi c dung l ng > 256 byte). Bi 7: Vi t o n l nh xa nh 1231H c a RAM ngoi (RAM ngoi c dung l ng > 256 byte). Bi 8: Vi t o n l nh ghi (chuy n) n i dung nh 1232H c a RAM ngoi vo thanh ghi A (RAM ngoi c dung l ng > 256 byte). Bi 9: Vi t o n l nh ghi (chuy n) n i dung thanh ghi A vo nh 1233H c a RAM ngoi (RAM ngoi c dung l ng > 256 byte). Bi 10: Vi t o n l nh chuy n d li u nh 1234H c a RAM ngoi vo nh 1235H c a RAM ngoi (RAM ngoi c dung l ng > 256 byte). Truy xu t Port: Bi 1: Vi t o n l nh xu t (ghi) gi tr 0FH ra Port 1. Bi 2: Vi t o n l nh xu t (ghi) gi tr F0H ra Port 2. Bi 3: Vi t o n l nh xu t (ghi) n i dung thanh ghi A ra Port 1. Bi 4: Vi t o n l nh nh p ( c) t Port 1 vo thanh ghi A. Bi 5: Vi t o n l nh nh p ( c) t Port 1 v xu t ra Port 2. Bi 6: Vi t o n l nh xu t (ghi) n i dung nh 37H c a RAM n i ra Port 3. Bi 7: Vi t o n l nh nh p ( c) t Port 2 vo nh 38H c a RAM n i. Bi 8: Vi t o n l nh xu t m c 1 (m c logic cao) ra chn P1.0 Bi 9: Vi t o n l nh xu t m c 0 (m c logic th p) ra chn P1.1 Truy xu t RAM n i, RAM ngoi v Port: Bi 1: Vi t o n l nh chuy n nh 40H (RAM n i) vo nh 2000H (RAM ngoi). Bi 2: Vi t o n l nh chuy n n i dung nh 2001H (RAM ngoi) vo nh 41H (RAM n i). Bi 3: Vi t o n l nh nh p ( c) t Port 1 vo nh 42H (RAM n i). Bi 4: Vi t o n l nh nh p ( c) t Port 1 vo nh 2002H (RAM ngoi). Bi 5: Vi t o n l nh xu t (ghi) n i dung nh 43H (RAM n i) ra Port 1. Bi 6: Vi t o n l nh xu t (ghi) n i dung nh 2003H (RAM ngoi) ra Port 1. S d ng vng l p: Bi 1: Vi t o n l nh xa 20 nh RAM n i c a ch b t u l 30H. Bi 2: Vi t o n l nh xa cc nh RAM n i t a ch 20H n 7FH. Bi 3: Vi t o n l nh xa 250 nh RAM ngoi c a ch b t u l 4000H. Bi 4: Vi t o n l nh xa 2500 nh RAM ngoi c a ch b t u l 4000H. Bi 5: Vi t o n l nh xa cc nh RAM ngoi t a ch 2000H n 205FH. Bi 6: Vi t o n l nh xa cc nh RAM ngoi t a ch 2000H n 3FFFH. Bi 7: Vi t o n l nh xa ton b RAM ngoi c dung l ng 8KB, bi t r ng a ch u l 2000H. Gio trnh Vi x l. 115 Bin so n: Ph m Quang Tr
Bi 8: Vi t o n l nh chuy n m t chu i d li u g m 10 byte trong RAM n i c a ch u l 30H n vng RAM n i c a ch u l 40H. Bi 9: Vi t o n l nh chuy n m t chu i d li u g m 100 byte trong RAM ngoi c a ch u l 2000H n vng RAM ngoi c a ch u l 4000H. Bi 10: Vi t o n l nh chuy n m t chu i d li u g m 1000 byte trong RAM ngoi c a ch u l 2000H n vng RAM ngoi c a ch u l 4000H. Bi 11: Vi t o n l nh chuy n m t chu i d li u g m 10 byte trong RAM n i c a ch u l 30H n vng RAM ngoi c a ch u l 4000H. Bi 12: Vi t o n l nh chuy n m t chu i d li u g m 10 byte trong RAM ngoi c a ch u l 5F00H n vng RAM n i c a ch u l 40H. Bi 13: Cho m t chu i d li u g m 20 byte lin ti p trong RAM n i, b t u t a ch 20H. Hy vi t o n l nh l n l t xu t cc d li u ny ra Port 1. Bi 14: Gi s Port 1 c n i n m t thi t b pht d li u (v d nh 8 nt nh n). Hy vi t o n l nh nh n lin ti p 10 byte d li u t thi t b pht ny v ghi vo 10 nh (RAM n i) lin ti p b t u t nh 50H. T o tr : Bi 1: Vi t chng trnh con delay 100s, bi t r ng fOSC dng trong h th ng l: a. 6 MHz. b. 11,0592 MHz. c. 12 MHz. d. 24 MHz Bi 2: Vi t chng trnh con delay 100ms, bi t r ng fOSC dng trong h th ng l: a. 6 MHz. b. 11,0592 MHz. c. 12 MHz. d. 24 MHz Bi 3: Vi t chng trnh con delay 1s, bi t r ng fOSC dng trong h th ng l: a. 6 MHz. b. 11,0592 MHz. c. 12 MHz. d. 24 MHz T o xung: ) t i chn P1.0 v i r ng xung 1ms, bi Bi 1: Vi t o n l nh t o m t xung dng ( r ng fOSC =12 MHz. Bi 2: Vi t o n l nh t o chu i xung vung c f = 100 KHz t i chn P1.1 (fOSC =12 MHz). Bi 3: Vi t o n l nh t o chu i xung vung c f = 100 KHz v c chu k lm vi c D = 40% t chn P1.2 (fOSC =12 MHz). Bi 4: Vi t o n l nh t o chu i xung vung c f = 10 KHz t i chn P1.3 (fOSC =24 MHz). Bi 5: Vi t o n l nh t o chu i xung vung c f = 10 KHz v c chu k lm vi c D = 30% t chn P1.3 (fOSC =24 MHz). Bi 6: Vi t o n l nh t o chu i xung vung c f = 10 Hz t i chn P1.4 (fOSC =12 MHz). Bi 7: Vi t o n l nh t o chu i xung vung c f = 10 Hz v c chu k lm vi c D = 25% t chn P1.5 (fOSC =11,0592 MHz). Cc php ton: Gio trnh Vi x l. 116 Bin so n: Ph m Quang Tr t
Bi 1: Cho m t chu i s 8 bit khng d u trong RAM n i g m 10 s b t u t nh 30H. Hy vi t chng trnh con c ng chu i s ny v ghi k t qu vo nh 2FH trong RAM n i (gi s k t qu nh hn ho c b ng 255). Bi 2: Cho m t chu i s 8 bit khng d u trong RAM n i g m 10 s b t u t nh 30H. Hy vi t chng trnh con c ng chu i s ny v ghi k t qu vo hai nh 2EH:2FH trong RAM n i ( nh 2EH ch a byte cao c a k t qu v nh 2FH ch a byte th p c a k t qu ). Bi 3: Cho m t chu i s 16 bit khng d u trong RAM n i g m 10 s b t u t nh 30H theo nguyn t c nh c a ch nh hn ch a byte cao v nh c a ch l n hn ch a byte th p. (V d : byte cao c a s 16 bit u tin c c t t i nh 30H v byte th p c a s 16 bit u tin c c t t i nh 31H; byte cao c a s 16 bit th hai c c t t i nh 32H v byte th p c a s 16 bit th hai c c t t i nh 33H). Hy vi t chng trnh con c ng chu i s ny v c t k t qu vo hai nh 2EH:2FH trong RAM n i. Bi 4: Tng t nh cc bi 1, 2, 3 nhng th c hi n i v i php tr . Bi 5: Vi t chng trnh con l y b 2 s 16 bit ch a trong hai thanh ghi R2:R3. So snh: Bi 1: Cho hai s 8 bit, s th nh t ch a trong nh 30H, s th hai ch a trong nh 31H. Vi t chng trnh con so snh hai s ny. N u s th nh t l n hn ho c b ng s th hai th set c F0, n u ng c l i th xa c F0. Bi 2: Cho hai s 16 bit, s th nh t ch a trong hai nh 30H:31H, s th hai ch a trong hai nh 32H:33H. Vi t chng trnh con so snh hai s ny. N u s th nh t l n hn ho c b ng s th hai th set c F0, n u ng c l i th xa c F0. Bi 3: Cho m t chu i k t d i d ng m ASCII trong RAM n i, di 20 byte, b t u t a ch 50H. Vi t o n l nh xu t cc k t in hoa c trong chu i ny ra Port 1. Bi t r ng m ASCII c a k t in hoa l t 65H (ch A) n 90H (ch Z). Bi 4: Vi t o n l nh nh p m t chu i k t t Port 1 d i d ng m ASCII v ghi vo RAM ngoi, b t u t a ch 0000H. Bi t r ng chu i ny k t thc b ng k t CR (c m ASCII l 0DH) v ghi c k t ny vo RAM. Bi 5: Vi t o n l nh nh p m t chu i k t t Port 1 d i d ng m ASCII v ghi vo RAM ngoi, b t u t a ch 0000H. Bi t r ng chu i ny k t thc b ng k t CR (c m ASCII l 0DH) v khng ghi k t ny vo RAM. Bi 6: Vi t o n l nh nh p m t chu i k t t Port 1 d i d ng m ASCII v ghi vo RAM ngoi, b t u t a ch 0000H. Bi t r ng chu i ny k t thc b ng k t CR (c m ASCII l 0DH) v khng ghi k t ny vo RAM m thay b ng k t NULL (c m ASCII l 00H). Bi 7: Cho m t chu i k t d i d ng m ASCII trong RAM n i, di 20 byte, b t u t a ch 50H. Vi t o n l nh i cc k t in hoa c trong chu i ny thnh k t th ng. Bi t r ng m ASCII c a k t th ng b ng m ASCII c a k t in hoa c ng thm 32H. Bi 8: Cho m t chu i k t s d i d ng m ASCII trong RAM n i, di 20 byte, b t u t a ch 50H. Vi t o n l nh i cc k t s ny thnh m BCD. Bi t r ng m ASCII c a cc k t s l t 30H (s 0) n 39H (s 9). S d ng l nh nh y c i u ki n: Bi 1: Cho m t chu i d li u d i d ng s c d u trong RAM ngoi, di 100 byte, b t u t a ch 0100H. Vi t o n l nh l n l t xu t cc d li u trong chu i ra Port 1 n u l s dng (xem s 0 l dng) v xu t ra Port 2 n u l s m. Bi 2: Cho m t chu i d li u d i d ng s c d u trong RAM ngoi, b t u t a ch 0100H v k t thc b ng s 0. Vi t o n l nh l n l t xu t cc d li u trong chu i ra Port 1 n u l s dng v xu t ra Port 2 n u l s m.
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Bi 3: Cho m t chu i d li u d i d ng s khng d u trong RAM ngoi, b t u t a ch 0100H v di chu i l n i dung nh 00FFH. Vi t o n l nh m s s ch n (chia h t cho 2) c trong chu i v c t vo nh 00FEH. Bi 4: Cho m t chu i d li u d i d ng s khng d u trong RAM ngoi, b t u t a ch 0100H v di chu i l n i dung nh 00FFH. Vi t o n l nh ghi cc s ch n (xem s 0 l s ch n) c trong chu i vo RAM n i b t u t a ch 30H cho n khi g p s l th d ng. Bi 5: Vi t chng trnh con c nhi m v l y m t byte t m t chu i data g m 20 byte c t trong RAM ngoi b t u t a ch 2000H v xu t ra Port1. M i l n g i chng trnh con ch xu t m t byte, l n g i k th xu t byte k ti p, l n g i th 21 th l i xu t byte u, ...
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GIO TRNH VI X
Chng 4: Ho t ng c a b nh th i (Timer).
CHNG 4 HO T NG C A B NH TH I (TIMER)
I. M U:
Bo nh thi (TIMER)
La chuoi cac FF (moi FF la 1 mach chia 2). Ngo vao: nhan tn hieu xung clock t nguon xung. Ngo ra: truyen tn hieu xung clock cho FF bao tran (c tran).
T n s : t n s xung ng ra b ng t n s xung ng vo chia cho 2N. Gi tr : gi tr nh phn trong cc FF c a b nh th i l s m c a cc xung clock t i ng vo t khi b nh th i b t u m. Trn: x y ra hi n t ng trn (c trn = 1) khi s m chuy n t gi tr l n nh t xu ng gi tr nh nh t c a b nh th i. V d : B nh th i 16 bit (ch a 16 FF bn trong). f f o T ns : f = IN = IN OUT 216 65536 o Gi tr : s m n m trong kho ng 0 (0000H) 65535 (FFFFH). o Trn: c trn b ng 1 khi s m t FFFFH chuy n xu ng 0000H. Hnh minh h a n gi n ho t ng c a b nh th i 3 bit:
Ho t ng c a m t b nh th i 3 bit n gi n c minh h a trong hnh trn. M i m t t ng l D FF kch kh i c nh m ho t ng nh m t m ch chia 2 do ta n i ng ra Q v i ng vo D. Flipflop c (Flag FF) l m t m ch ch t D c set b ng 1 b i t ng cu i c a b nh th i. Gi n th i gian cho Gio trnh Vi x l. 119 Bin so n: Ph m Quang Tr
th y t ng th nh t (Q0) chia 2 t n s xung clock, t ng th hai (Q1) chia 4 t n s xung clock, S m c ghi d ng th p phn v c ki m tra d dng b ng cch kh o st tr ng thi c a 3 flipflop. V d , s m l 4 xu t hi n khi Q2 = 1, Q1 = 0, Q0 = 0. Cc flipflop trn l cc flipflop tc ng c nh m (ngha l tr ng thi c a cc flipflop s thay i theo c nh m c a xung clock). Khi s m trn t 111 xu ng 000, ng ra Q2 c c nh m lm cho tr ng thi c a flipflop c i t 0 ln 1 (ng vo D c a flipflop ny lun lun logic 1).
ng d ng nh th i gian (TIMER): b nh th i c l p trnh sao cho s trn sau m t kho ng th i gian qui nh v khi c trn c a b nh th i s b ng 1. ng d ng m s ki n (COUNTER): xc nh s l n xu t hi n c a m t kch thch t bn ngoi t i m t chn c a chip 8051 (kch thch l s chuy n tr ng thi t 1 xu ng 0). ng d ng t o t c baud cho port n i ti p: xem thm trong chng Chng 5: Ho t ng port n i ti p..
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II. THANH GHI CH NH TH I (TMOD): Thanh ghi TMOD (Timer Mode Register) ch a cc bit dng thi t l p ch ho t ng cho b nh th i 0 v b nh th i 1. Thanh ghi TMOD c n p gi tr m t l n t i th i i m b t u c a chng trnh qui nh ch ho t ng c a cc b nh th i. C u trc thanh ghi TMOD:
Bit 7 6 5 4 3 2 1 0
TMOD: Timer Mode Register

M0: Bit chon che o hoat ong cho bo nh thi. M1: Bit chon che o hoat ong cho bo nh thi.
C/T: Bit chon chc nang em hoac nh thi. C/T=1: Bo nh thi la bo em (Counter). C/T=0: Bo nh thi la bo nh khoang thi gian (Timer).
GATE: Bit ieu khien cong. GATE=0: Bo nh thi hoat ong khi bit TR0=1 (ieu khien bang phan mem). GATE=1: Bo nh thi hoat ong khi chan INT0\=1 (ieu khien bang phan cng). M0: Bit chon che o hoat ong cho bo nh thi. M1: Bit chon che o hoat ong cho bo nh thi.
C/T: Bit chon chc nang em hoac nh thi. C/T=1: Bo nh thi la bo em (Counter). C/T=0: Bo nh thi la bo nh khoang thi gian (Timer).
Hnh 4.2.1: Thanh ghi chon che o nh thi.
GATE: Bit ieu khien cong. GATE=0: Bo nh thi hoat ong khi bit TR1=1 (ieu khien bang phan mem). GATE=1: Bo nh thi hoat ong khi chan INT1\=1 (ieu khien bang phan cng).
Cc ch ho t ng c a b nh th i:
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V d 1: Cho bi t gi tr c n n p cho thanh ghi TMOD o Timer 0: l b nh th i gian 16 bit, c i u khi n b ng ph n m m (bit TR0). o Timer 1: l b m xung 13 bit, c i u khi n b ng ph n c ng (chn INT 1 ).
Gi i
Phn tch: (1): Ch 16 bit. (2): B nh th i gian. (3): i u khi n b ng ph n m m. (4): Ch 13 bit. (5): B m xung. (6): i u khi n b ng ph n c ng.
M1 = 0, M0 = 1. C / T = 0. GATE = 0. M1 = 0, M0 = 0. C / T = 1. GATE = 1.
T ta c: (TMOD) = 11000001B = C1H. V d 2: Cho bi t gi tr c n n p cho thanh ghi TMOD o Timer 0: khng s d ng. o Timer 1: l b nh th i gian 8 bit t n p l i, c i u khi n b ng ph n m m (bit TR1).
Gi i Phn tch: (1): Khng s d ng. M1 = 0, M0 = 0. (2): Khng s d ng. C / T = 0. (3): Khng s d ng. GATE = 0. Do Timer 0 khng s d ng, nn ta c thi t l p n b t c ch no. Thng th ng d dng ta nn cho: GATE=0, C / T = 0, M1 = 0 v M0 = 0. (4): Ch 8 bit t ng n p l i. M1 = 1, M0 = 0. (5): B nh th i gian. C / T = 0. (6): i u khi n b ng ph n m m. GATE = 0.
T ta c: (TMOD) = 00100000B = 20H.
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V d 3: Cho bi t (TMOD) = A5H. Hy cho bi t ch ho t ng c a cc Timer 0 v Timer 1.

Gi i
Ta c: (TMOD) = A5H = 10100101B.
Gi i thch: M1 = 1, M0 = 0. C / T = 0. GATE = 1. M1 = 0, M0 = 1. C / T = 1. GATE = 0.
(4): Ch 8 bit t ng n p l i. (5): B nh th i gian. (6): i u khi n b ng ph n c ng. (1): Ch 16 bit. (2): B m xung. (3): i u khi n b ng ph n m m.
T ta c: o Timer 0: l b m xung 16 bit, c i u khi n b ng ph n m m (bit TR0). o Timer 1: l b nh th i gian 8 bit t n p l i, c i u khi n b ng ph n c ng (chn INT 1 ). V d 4: Cho bi t (TMOD) = 21H. Hy cho bi t ch ho t ng c a cc Timer 0 v Timer 1.
Gi i
Ta c: (TMOD) = 21H = 00100001B.
Gi i thch: M1 = 1, M0 = 0. C / T = 0. GATE = 0. M1 = 0, M0 = 1. C / T = 0. GATE = 0.
(4): Ch 8 bit t ng n p l i. (5): B nh th i gian. (6): i u khi n b ng ph n m m. (1): Ch 16 bit. (2): B nh th i gian. (3): i u khi n b ng ph n m m.
T ta c: o Timer 0: l b nh th i gian 16 bit, c i u khi n b ng ph n m m (bit TR0). o Timer 1: l b nh th i gian 8 bit t n p l i, c i u khi n b ng ph n m m (bit TR1).
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III. THANH GHI I U KHI N NH TH I (TCON): Thanh ghi TCON (Timer Control Register) ch a cc bit dng i u khi n v bo tr ng thi c a b nh th i 0 v b nh th i 1. C u trc thanh ghi TCON:
Lu : Cc bit IT0, IT1, IE0, IE1 khng dng i u khi n cc b nh th i. Cc bit ny c dng pht hi n v kh i ng cc ng t ngoi. Vi c th o lu n cc bit ny s c trnh by trong Chng 6: Ho t ng ng t..
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Chng 4: Ho t ng c a b nh th i (Timer). IV. CC CH NH TH I V C TRN:
1. Ch nh th i 13 bit (Ch 0):
Ch 0 (Mode 0): Ch nh th i 13 bit. S d ng 8 bit c a thanh ghi THx v 5 bit th p c a thanh ghi TLx t o ra b nh th i. S m: 0000H 1FFFH ngha l t 0 8191. Th i gian nh th i: t 1.TTimer 213.TTimer ngha l t 1.TTimer 8192.TTimer. Thanh ghi THx v TLx ch a gi tr c a b nh th i. Khi c xung clock, b nh th i b t u m ln t gi tr ch a trong THx/TLx. X y ra trn (c trn TFx=1) khi s m chuy n t 1FFFH sang 0000H v vi c m s ti p t c m ln t gi tr 0000H.
Ki n trc c a Timer 0
ch 0 (Mode 0).
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Chng 4: Ho t ng c a b nh th i (Timer). 2. Ch nh th i 16 bit (Ch 1):
Ch
1 (Mode 1): Ch nh th i 16 bit. S d ng thanh ghi THx v TLx t o ra b nh th i. S m: 0000H FFFFH ngha l t 0 65535. Th i gian nh th i: t 1.TTimer 216.TTimer ngha l t 1.TTimer 65536.TTimer. Thanh ghi THx v TLx ch a gi tr c a b nh th i. Khi c xung clock, b nh th i b t u m ln t gi tr ch a trong THx/TLx. X y ra trn (c trn TFx=1) khi s m chuy n t FFFFH sang 0000H v vi c m s ti p t c m ln t gi tr 0000H.
ch 1 (Mode 1).
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Chng 4: Ho t ng c a b nh th i (Timer). 3. Ch nh th i 8 bit t n p l i (Ch 2):
Ch
2 (Mode 2): Ch nh th i 8 bit t n p l i. S d ng thanh ghi TLx t o ra b nh th i. S m: 00H FFH ngha l t 0 255. Th i gian nh th i: t 1.TTimer 28.TTimer ngha l t 1.TTimer 256.TTimer. Thanh ghi TLx ch a gi tr c a b nh th i v thanh ghi THx ch a gi tr s c dng n p l i cho b nh th i. Khi c xung clock, b nh th i b t u m ln t gi tr ch a trong TLx (THx khng thay i gi tr ). X y ra trn (c trn TFx=1) khi s m chuy n t FFH sang 00H, ng th i gi tr trong THx s c n p vo TLx v vi c m s ti p t c m ln t gi tr ch a trong thanh ghi TLx (gi tr ny b ng v i gi tr c a THx).
ch 2 (Mode 2).
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Chng 4: Ho t ng c a b nh th i (Timer). 4. Ch nh th i chia x (Ch 3):

TH1 TL1
Timer clock Timer clock /12FOSC
TF0
TL0
TF1 Overflow flag
TH0
x = 0, 1: Bo nh thi 0, 1. Timer clock: Xung clock cho bo nh thi. Overflow flag: C tran.
Ch 3 (Mode 3) l: Ch nh th i chia x . B nh th i 0 c chia ra: o B nh th i 8 bit th I: S d ng thanh ghi TL0 t o ra b nh th i. S m: 00H FFH ngha l t 0 255. Th i gian nh th i: t 1.TTimer 28.TTimer ngha l t 1.TTimer 256.TTimer. Thanh ghi TL0 ch a gi tr c a b nh th i. Khi c xung clock, b nh th i b t u m ln t gi tr ch a trong TL0. X y ra trn (c trn TF0=1) khi s m chuy n t FFH sang 00H v vi c m s ti p t c m ln t gi tr 00H. o B nh th i 8 bit th II: S d ng thanh ghi TH0 t o ra b nh th i. S m: 00H FFH ngha l t 0 255. Th i gian nh th i: t 1.TTimer 28.TTimer ngha l t 1.TTimer 256.TTimer. Thanh ghi TH0 ch a gi tr c a b nh th i. Khi c xung clock, b nh th i b t u m ln t gi tr ch a trong TH0. X y ra trn (c trn TF1=1) khi s m chuy n t FFH sang 00H v vi c m s ti p t c m ln t gi tr 00H. B nh th i 1: o L b nh th i 16 bit. o Khng ho t ng ch 3 nhng c th ho t ng cc ch khc (ch 0, 1, 2). o Khng c c bo trn nh cc b nh th i khc.
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Ki n trc c a Timer 0 V. NGU N XUNG CLOCK CHO B
ch 3 (Mode 3).
NH TH I:
Ngu n xung cho b nh th i c t o ra t : M ch dao ng trn chip dng cho tnh nng nh th i gian. Xung kch thch bn ngoi dng cho tnh nng m s ki n. 1. Tr ng h p nh th i gian:
N u C/T=0 th: B nh th i c dng nh th i gian (Timer). Ngu n xung clock nh th i c l y t m ch dao ng trn chip. Lu : o T n s xung clock cung c p cho b nh th i b ng 1/12 t n s c a m ch dao ng trn chip 8051. o Th i gian nh th i l kho ng th i gian c tnh t lc b nh th i b t u m ln (t gi tr ch a trong cc thanh ghi THx/TLx) cho n lc b nh th i b t u trn (th i gian ny ph thu c vo gi tr ban u c n p cho cc thanh ghi THx v TLx).
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V d : Tm t n s xung clock v chu k c a b nh th i i v i tr ng h p cc h th ng vi i u khi n xy d ng trn chip 8051 v i t n s th ch anh nh sau: 11,0592 MHz, 12 MHz v 16 MHz.
Gi i
G i fTIMER l t n s xung clock c a b nh th i, fOSC l t n s xung clock c a th ch anh. Theo nh trn trnh by, ta c:
f f 11,0592(MHz ) = 11,0592(MHz ) f = OSC = = 921,6(KHz ) TIMER OSC 12 12 1 1 T = = = 1,085(s ) TIMER f 921,6(KHz ) TIMER
f 12(MHz ) = 12(MHz ) f = OSC = = 1(MHz ) TIMER OSC 12 12 1 1 T = = = 1(s ) TIMER f 1(MHz ) TIMER
f 16(MHz ) = 16(MHz ) f = OSC = = 1,333(MHz ) TIMER OSC 12 12 1 1 T = = = 0,75(s ) TIMER f 1,333(MHz ) TIMER
2. Tr ng h p m s ki n:
N u C/T=1 th: B nh th i c dng m s ki n (Counter). Ngu n xung clock nh th i c l y t xung kch thch bn ngoi t i hai chn T0 v T1 c a chip 8051. Lu :
o T n s kch thch t i a cho php t i chn T0 v T1:
f = TIMER T 0,T 1( MAX ) 2
fTIMER: t n s xung clock nh th i. fT0,T1(MAX): t n s kch thch t i a cho php t i T0 v T1.

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V d : Tnh t n s kch thch t i a cho php t i chn T0 v T1 i v i tr ng h p cc h th ng vi i u khi n xy d ng trn chip 8051 v i t n s th ch anh nh sau: 11,0592 MHz, 12 MHz v 16 MHz. Gi i
f f
f
OSC
= 11,0592(MHz ) f
f 921,6(KHz ) = TIMER = = 460,8(KHz ) T 0,T 1( MAX ) 2 2
f 1(MHz ) = 12(MHz ) f = TIMER = = 500(KHz ) OSC T 0,T 1( MAX ) 2 2

f 1,333(MHz ) = 16(MHz ) f = TIMER = = 666,5(KHz ) OSC T 0,T 1( MAX ) 2 2
o S l ng s ki n (s xung) m b nh th i m c s c ch a trong cc thanh ghi THx/TLx, gi tr trong cc thanh ghi ny s tng theo m i xung kch thch bn ngoi t i T0 v T1 c a chip 8051. o M t kch thch c g i l m t s ki n (m t xung) khi x y ra s chuy n tr ng thi t 1 xu ng 0 chn T0 ho c T1. VI. KH I NG, D NG V I U KHI N CC B NH TH I:
Cch 1: (th ng c dng nh th i gian).

i u ki n s d ng: bit GATE = 0
(Phng php i u khi n b ng ph n m m)
B nh th i x ch y khi bit TRx = 1. B nh th i x d ng khi bit TRx = 0.

V d : kh i ng b nh th i 0 ta dng l nh: d ng b nh th i 0 ta dng l nh:
SETB TR0 CLR TR0
Cch 2: (th ng c dng o r ng xung t i chn INTx\ ).

i u ki n s d ng: bit GATE = 1 v bit /TRx = 1
(Phng php i u khi n b ng ph n c ng)
B nh th i x ch y khi chn INTx\ = 1. B nh th i x d ng khi chn INTx\ = 0.

V d : o r ng xung (tnh b ng s) t i chn INT0, v i fOSC = 12MHz.
INT0\ t ( s)
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Gi i Ta kh i ng b nh th i 0 nh sau: Ch nh th i 16 bit (ch 1). Gi tr trong TH0/TL0 l 0000H. GATE = 1 v TR0 = 1 (i u khi n ho t ng c a Timer 0 b ng ph n c ng, t c i u khi n b ng tn hi u t i chn INT0\).
r ng xung (tnh b ng s) = S m ch a trong TH0/TL0. Hnh minh h a Timer 1 ho t ng

12 MHz On-chip Osc. T1 (P3.5) C/T TR1 GATE INT1 (P3.3) 12
ch 1 (Timer 16 bit):
8051
TL1 TH1 0 = Up 1 = Down 0 = Up 1 = Down TF1
Hoat ong che o 1 cua Timer 1

VII. KH I NG V TRUY XU T THANH GHI NH TH I:
Tr c khi cc b nh th i ho t ng c n ph i: Qui nh ch c a b nh th i thanh ghi TMOD. Qui nh i m b t u m c a b nh th i (kho ng th i gian nh th i) thanh ghi THx/TLx.
o V d 1: Kh i ng b nh th i 1 ho t ng ch 16 bit, xung clock c l y t m ch dao ng trn chip (ngha l b nh c dng nh th i m t kho ng th i gian), c kh i ng b ng bit TR1 (i u khi n b ng ph n m m).
Gi i Ta dng l nh:
MOV TMOD, #10H
ho c
MOV TMOD, #00010000B
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Gi i thch:
GATE = 0 i u khi n b ng ph n m m (bit TR1). C/T = 0 s d ng m ch dao ng trn chip (dng nh m t kho ng th i gian). M1 = 0, M1 = 1 TIMER1 ho t ng ch 1 (ch nh th i 16 bit).
o V d 2: Dng b nh th i 1 i u khi n s d ng th ch anh 12 MHz.
v d trn nh m t kho ng th i gian l 100 s. Gi s vi Gi i
Ta dng l nh:
MOV TL1, #9CH MOV TH1, #0FFH
ho c
MOV TL1, #LOW(-100) MOV TH1, #HIGH(-100)
Gi i thch:
f f 12 = 12(MHz ) f = OSC = = 1(MHz ) TIMER OSC 12 12 1 1 T = = = 1(s ) TIMER f 1(MHz ) TIMER
fOSC: t n s th ch anh. fTIMER: t n s xung clock nh th i. TTIMER: chu k xung clock nh th i. V y c m i 1 s (t c l sau m i chu k c a xung clock nh th i) th b nh th i s tng gi tr m t l n. Trong : M ta bi t: th i gian nh th i l kho ng th i gian c tnh t lc b nh th i b t u m ln cho n lc b nh th i b t u trn. V y b nh th i trn s trn sau kho ng th i gian 100 s th ta ph i kh i ng b nh th i t i th i i m cch i m trn (theo chi u m v b nh th i ch m ln) 100 chu k xung clock nh th i. V i m trn c gi tr l 0 cho nn gi tr c n n p cho cc thanh ghi TH1/TL1 l -100 (hay FF9CH).
$
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T ng qut, ta c cng th c tnh gi tr c n n p cho b nh th i c th i gian nh th i nh mong mu n l:
f N = OSC t 12 DELAY
Trong : N: gi tr c n n p cho b nh th i. fOSC (MHz): t n s th ch anh. tDELAY ( s): th i gian c n nh th i.
2. Truy xu t gi tr c a b nh th i ang ho t ng:
Trong cc ng d ng th c t , ta c n ph i c gi tr (n i dung) ch a trong cc thanh ghi nh th i THx/TLx trong khi b nh th i v n ang ho t ng. Do gi tr c a b nh th i c ch a trong c hai thanh ghi THx/TLx. Cho nn ta ph i c hai thanh ghi ny b ng hai dng l nh lin ti p nhau (do khng c l nh no c th c ng th i c hai thanh ghi nh th i ny). M t s sai pha (phase error) c th xu t hi n n u c s trn t byte th p chuy n sang byte cao gi a hai l n c v do v y ta khng th c ng c gi tr c n c. V d : Minh h a v s sai pha (phase error) c th xu t hi n n u c s trn t byte th p chuy n sang byte cao gi a hai l n c gi tr lm cho ta khng th c ng c gi tr c n c c a THx/TLx trong khi b nh th i ang ho t ng. Gi i
Gi i php a ra l tr c tin ta ph i c byte cao, k n c byte th p v r i c byte th p l n n a. N u byte cao thay i gi tr , ta l p l i thao tc c v a nu. Lu gi i thu t dng c chnh xc gi tr (n i dung) ch a trong cc thanh ghi nh th i THx/TLx c a b nh th i ang ho t ng:
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V d : c n i dung c a cc thanh ghi TH1/TL1 trong khi b nh th i 1 ang ho t ng. N i dung sau khi c c a thanh ghi TH1 ch a trong R7, c a thanh ghi TL1 ch a trong R6. AGAIN: MOV A, TH1 MOV R6, TL1 CJNE A, TH1, AGAIN MOV R7, A
VIII. CC KHO NG TH I GIAN NH TH I:
Kh o st tr ng h p 8051 dng th ch anh 12 MHz: Kho ng th i gian nh th i ng n nh t (s): 1 Kho ng th i gian nh th i di nh t (s): o 10 Dng cc l nh. Dng b nh th i 8 bit t ng n p l i. o 256 o 65536 Dng b nh th i 16 bit. Dng b nh th i 16 bit + cc vng l p. o Khng gi i h n Kh o st tr ng h p t ng qut: Kho ng th i gian nh th i ng n nh t: 1.TTIMER Kho ng th i gian nh th i di nh t: o 10.TTIMER Dng cc l nh. o 256.TTIMER Dng b nh th i 8 bit t ng n p l i. Dng b nh th i 16 bit. o 65536.TTIMER o Khng gi i h n Dng b nh th i 16 bit + cc vng l p. v i TTIMER = f
12 OSC
TTIMER(s): chu k xung clock nh th i. fOSC (MHz): t n s th ch anh.
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IX. CC B C C B N KH I NG TIMER V COUNTER: 1. Cc b c c b n kh i ng Timer: Ch n ch ho t ng cho Timer, cho bit GATE=0 v C/T=0: MOV TMOD, #...(1) Ch n gi tr thch h p (kho ng th i gian nh th i) cho Timer: MOV THx, #...(2) MOV TLx, #...(3) Cho Timer ch y: SETB TRx Ki m tra c bo trn (ki m tra th i gian nh th i): JNB TFx, $ ho c WAIT: JNB TFx, WAIT Xa c bo trn (chu n b cho l n nh th i ti p theo): CLR TFx D ng Timer (sau khi hon t t qu trnh nh th i): CLR TRx Lu : x: S th t c a Timer s d ng. (1): Gi tr ny ph thu c vo Timer c ch n v ch ho t ng c a Timer . (2), (3): Gi tr ny ph thu c vo kho ng th i gian c n nh th i. Cng c n lu thm, vi c ch n gi tr cho khng ph i lc no ta cng ph i ch n gi tr cho c hai thanh ghi ny m n ty thu c vo t ng ch ho t ng c a Timer (Mode 0: THx/TLx, Mode 1: THx/TLx, Mode 2: THx, Mode 3: THx ho c TLx). Cc gi tr trn ph i tho mn i u ki n sau: o Ch 8 bit: gi tr trong kho ng t -255 n -1 (tng ng t 255.TTIMER n 1.TTIMER).
V d : V d :
MOV TH1, #(-255) nh th i 255.TTIMER MOV TL1, #LOW(-8000) nh th i 8000.TTIMER MOV TH1, #HIGH(-8000) MOV TL1, #LOW(-10000) nh th i 10000.TTIMER MOV TH1, #HIGH(-10000)
o Ch 13 bit: gi tr trong kho ng t -8191 n -1 (tng ng t 8191.TTIMER n 1.TTIMER).
o Ch 16 bit: gi tr trong kho ng t -65535 n -1 (tng ng t 65535.TTIMER n 1.TTIMER).
V d :
Tr ng h p c bi t n u gi tr (N) n p vo thanh ghi THx/TLx l gi tr 0 th th i gian nh th i s l l n nh t cho t ng ch . Ch 8 bit: N = 0 tDELAY = 256.TTIMER. Ch 13 bit: N = 0 tDELAY = 8192.TTIMER. Ch 16 bit: N = 0 tDELAY = 65536.TTIMER.
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2. Cc b c c b n kh i ng Counter: Ch n ch ho t ng cho Counter, cho bit GATE=0 v C/T=1: MOV TMOD, #...(1) Xo cc gi tr ch a trong thanh ghi THx v TLx (ngha l cho s xung ban u b ng 0): MOV THx, #00H MOV TLx, #00H Cho Counter ch y: SETB TRx Ki m tra c bo trn (ki m tra s m b trn) x l tr ng h p s m b trn. Xa c bo trn (sau khi x l cho tr ng h p s m b trn): CLR TFx D ng Counter (sau khi hon t t qu trnh m xung): CLR TRx c s xung m c trong thanh ghi THx v TLx.
Lu :
x: S th t c a Counter s d ng. (1): Gi tr ny ph thu c vo Counter c ch n v ch ho t ng c a Counter. Gi tr ny ph i tho mn i u ki n sau: o o o Ch 8 bit: s l ng xung t i a m Counter m c t 0 n 255. Ch 13 bit: s l ng xung t i a m Counter m c t 0 n 8191. Ch 16 bit: s l ng xung t i a m Counter m c t 0 n 65535.
Trong qu trnh c s xung m c ch a trong cc thanh ghi THx/TLx ta ph i ch n tr ng h p Counter b trn. V khi gi tr trong thanh ghi THx/TLx (ni ch a s xung m c) s tr v 0. Cho nn n u ta khng c bi n php x l cho tr ng h p ny th k t qu l s xung m ta nh n c s b sai. V th , n u ta gi s ban u Counter c kh i ng v i gi tr l 0 th c m i l n Counter b trn th ta ph i c ng thm vo s xung c v 256 xung (tr ng h p 8 bit) ho c 8192 xung (tr ng h p 13 bit) ho c 65536 xung (tr ng h p 16 bit).
X. CC V D MINH H A: 1. V d 1: (T o d ng xung) Vi t chng trnh t o d ng xung tu n hon trn chn P1.0 c t n s cao nh t c th c. T n s v chu k nhi m v c a d ng xung ny l bao nhiu?
Gi i
LOOP: ORG 8100H SETB P1.0 CLR P1.0 SJMP LOOP END
;1 chu k my ;1 chu k my ;2 chu k my
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Chu k xung: 4 s T n s xung: 250 KHz. Th i gian m c cao: 1 s. Th i gian m c th p: 3 s. Chu k nhi m v : 25%.
2. V d 2: (T o th i gian tr ) Vi t chng trnh con t o th i gian tr tDelay, s d ng phng php dng cc l nh (khng dng Timer). Bi t r ng t n s th ch anh l 12 MHz. a. Th i gian tr tDelay = 100 s. b. Th i gian tr tDelay = 10 ms. c. Th i gian tr tDelay = 1 s.
Gi i Phng php: Phng php th c hi n l s d ng l nh vng l p DJNZ t o th i gia tr tDelay nh mong mu n. V d m u: DELAY: ;tDelay = 10 x 20 x 30 x 2.TTimer MOV R0, #10 BBB: MOV R1, #20 AAA: MOV R2, #30 DJNZ R2, $ ;l nh 2.TTimer DJNZ R1, AAA DJNZ R0, BBB RET T ng qut, ta c cng th c tnh th i gian tr tDelay nh sau:
t Trong : Delay = [Rn ] [Rm] ... [Rv ] 2. 12 f Osc (1)
tDelay (s): th i gian tr . fOsc (MHz): t n s th ch anh. 12 . = TTimer (s): chu k Timer T Timer f Osc [Rn], [Rm], , [Rv]: gi tr c a cc vng l p (s l n l p l i l nh
DJNZ). Lu : Gi tr c a cc vng l p ph i th a i u ki n 0 [Rn] 255. c bi t n u ch n [Rn] = 0 th i u ny s tng ng v i tr ng h p ta ch n [Rn] = 256 (tng t cho cc [Rm], , [Rv] khc). Tnh ton: Tm gi tr c n n p cho cc thanh ghi vng l p: 12 = [Rn ] [Rm ] ... [Rv ] 2. Ta c: t Delay f Osc V i tDelay = 100 s, fOsc = 12 MHz th ta ch n: [Rn] = 50 12 t = 50 2. = 100 s Delay 12
V i tDelay = 10 ms, fOsc = 12 MHz th ta ch n: [Rn] = 20 v [Rm] = 250 12 = 20 250 2. = 10000 s t Delay 12 V i tDelay = 1 s, fOsc = 12 MHz th ta ch n: [Rn] = 10, [Rm] = 200 v [Ro] = 250 12 = 10 200 250 2. = 1000000 s t Delay 12
Chng trnh: D a vo nh ng tnh ton trn, ta c: V i tDelay = 100 s: DELAY: MOV R0, #50 DJNZ R0, $ RET V i tDelay = 10 ms: DELAY: MOV R0, #20 AAA: MOV R1, #250 DJNZ R1, $ DJNZ R0, AAA RET V i tDelay = 1 s: DELAY: MOV R0, #10 BBB: MOV R1, #200 AAA: MOV R2, #250 DJNZ R2, $ DJNZ R1, AAA DJNZ R0, BBB RET ;tDelay = 50 x 2.TTimer ;l nh 1.TTimer ;l nh 2.TTimer ;l nh 2.TTimer ;tDelay = 20 x 250 x 2.TTimer ;l nh 1.TTimer ;l ;l ;l ;l nh 1.TTimer nh 2.TTimer nh 2.TTimer nh 2.TTimer
;tDelay = 10 x 200 x 250 x 2.TTimer ;l nh 1.TTimer ;l nh 1.TTimer ;l ;l ;l ;l ;l nh 1.TTimer nh 2.TTimer nh 2.TTimer nh 2.TTimer nh 2.TTimer
Lu v chnh xc c a tDelay: Khi s d ng phng php t o th i gian tr nh trn (phng php dng l nh, khng dng Timer) th vi c nh th i gian th ng c m t sai s nh t nh. V y, n gi n trong vi c tnh ton m ta b qua khng tnh n th i gian c n thi t th c hi n t ng l nh trong chng trnh, ch quan tm n th i gian th c hi n c a l nh DJNZ (2TTimer) v s l n th c hi n c a n. Cng th c trnh by trn (1) ch l cng th c tnh th i gian tDelay c chnh xc tng i, mu n tnh th i gian tDelay chnh xc th ta c n ph i tnh t ng th i gian th c hi n (ngha l tnh s chu k my hay s chu k Timer) c a t t c cc l nh c trong chng trnh. chnh xc c a chng trnh t o th i gian tr theo phng php tnh tng i ny ph thu c vo s l n l p l i v s vng l p. V i tDelay = 100 s, fOsc = 12 MHz th tDelay chnh xc l:
Delay (cx)
= 1.T + 2.T 50 + 2.T = 103.T Timer Timer Timer Timer
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V i tDelay = 10 ms, fOsc = 12 MHz th tDelay chnh xc l:
t Delay ( cx )

20 + 2.T = 10065 .T Timer Timer
10 + 2.T Timer
= 1.T + 1.T + 2.T 250 + 2.T Timer Timer Timer Timer
V i tDelay = 1 s, fOsc = 12 MHz th tDelay chnh xc l:

t Delay (cx ) 200 + 2.T = 1.T + 1.T + 1.T + 2.T 250 + 2.T Timer Timer Timer Timer Timer Timer = 1006033 .T Timer
3. V d 3: (T o th i gian tr ) Vi t chng trnh con t o th i gian tr 100 s dng Timer 0. Bi t r ng t n s th ch anh l 12 MHz. Gi i
Tnh ton: Tm gi tr c n n p cho b nh th i v ch ho t ng c a b nh th i ny: = 12 (MHz ) Theo bi ta c: t = 100 (s ) v f Osc Delay Gi tr c n n p cho b nh th i c tnh theo cng th c: f 12.106 = 100.10 6 = 100 N = Osc t Delay 12 12 V y: N = -100 ho c N = 9CH. t = 100 (s ) Ta c: Delay 1 12 12 TTimer = = = =106 (s )=1 (s ) fTimer fOsc 12.106 256.T (hay N n m trong kho ng t -255 n -1) nn ta c th ch n Timer V t Timer Delay ch 1 (ch 16 bit) ho c ch 2 (ch 8 bit t ng n p l i). Chng trnh: D a vo nh ng tnh ton trn, ta c: Chng trnh con hon ch nh khi s d ng Timer 0 ch 2: DELAY: MOV TMOD, #02H MOV TH0, #(-100) ho c MOV TH0, #9CH SETB TR0 JNB TF0, $ CLR TF0 CLR TR0 RET Chng trnh con hon ch nh khi s d ng Timer 0 ch 1: DELAY: MOV TMOD, #01H MOV TH0, #HIGH(-100) ho c MOV TH0, #0FFH MOV TL0, #LOW(-100) ho c MOV TL0, #9CH SETB TR0 JNB TF0, $ CLR TF0 CLR TR0 RET
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chnh xc (xt v m t th i gian) c a chng trnh: Khi s d ng phng php t o th i gian tr nh trn (phng php dng Timer) th vi c nh th i gian cng xu t hi n m t sai s . V y, n gi n trong vi c tnh ton m ta b qua khng tnh n th i gian c n thi t th c hi n t ng l nh trong chng trnh, ch quan tm n gi tr c n ph i n p cho b nh th i sao cho Timer nh c kho ng th i gian m ta yu c u. chnh xc c a chng trnh nh th i khi s d ng phng php ny khng ph thu c vo gi tr c n n p cho Timer (N) m n ch ph thu c vo s l ng l nh s d ng trong chng trnh. V i d ng th nh t (ch 2) th tDelay chnh xc l: t V i d ng th hai (ch 1) th tDelay chnh xc l: t
Delay(cx)
= 11.T +t = 111(s ) Timer Delay
Delay(cx)
= 13.T +t = 113(s ) Timer Delay
4. V d 4: (T o th i gian tr ) Vi t chng trnh con t o th i gian tr 10 ms dng Timer 1. Bi t r ng t n s th ch anh l 12 MHz. Gi i

Tnh ton: Tm gi tr c n n p cho b nh th i v ch ho t ng c a b nh th i ny: = 10 (ms) v f = 12 (MHz ) Theo bi ta c: t Osc Delay Gi tr c n n p cho b nh th i c tnh theo cng th c: f 12.106 = 10.103 = 10000 N = Osc t Delay 12 12 V y: N = -10000 ho c N = D8F0H. t = 10 (ms ) = 10000 (s ) Ta c: Delay 1 12 12 = = = = 106 (s ) = 1(s ) T Timer f 6 f Timer Osc 12.10 V t 65536.T (hay N n m trong kho ng t -65535 n -1) nn ta ch n Timer Timer Delay ch 1 (ch 16 bit).
Chng trnh: D a vo nh ng tnh ton trn, ta c: Chng trnh con hon ch nh khi s d ng Timer 1 ch 1: DELAY: MOV TMOD, #10H MOV TH1, #HIGH(-10000) ho c MOV TH1, #0D8H MOV TL1, #LOW(-10000) ho c MOV TL1, #0F0H SETB TR1 JNB TF1, $ CLR TF1 CLR TR1 RET chnh xc (xt v m t th i gian) c a chng trnh: V i v d trn (ch 1) th tDelay chnh xc l: t
Delay (cx)
= 13.T +t = 10013(s ) Timer Delay
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5. V d 5: (T o th i gian tr ) Vi t chng trnh con t o th i gian tr 1s dng Timer 1. Bi t r ng t n s th ch anh l 12 MHz. Gi i
Tnh ton: Tm gi tr c n n p cho b nh th i v ch ho t ng c a b nh th i ny: Theo bi ta c: t = 1 (s ) v f = 12 (MHz ) Osc Delay Gi tr c n n p cho b nh th i c tnh theo cng th c: f 12.10 6 = 1 = 1000000 N = Osc t Delay 12 12 V y: N = -1000000 (gi tr qu l n khng th n p tr c ti p vo cc thanh ghi THx/TLx). Ta c: t = 1(s ) = 1000000 (s ) Delay 1 12 12 = = =106 (s )=1(s ) TTimer = 6 fTimer fOsc 12.10 nn ta ch n ph i Timer ch 1 (ch 16 bit) k t h p v i cc V t > 65536.T Timer Delay thanh ghi t o vng l p. G i: N l gi tr c n n p cho cc thanh ghi nh th i. [Rn] l gi tr c n n p cho thanh ghi k t h p (vng l p). N = [Rn] x N Ta t ch n: N = -10000 [Rn] = 100
o Lu : N' c ch n sao cho ph h p v i qui nh ch n gi tr c n n p cho cc thanh ghi nh th i ch 1. [Rn] 255, c bi t n u ch n [Rn] = 0 th i u ny s tng ng v i tr ng h p ta ch n [Rn] = 256.
Gi tr c n n p cho cc thanh ghi nh th i l -10000 v gi tr c n n p cho thanh ghi k t h p l 100. Chng trnh: D a vo nh ng tnh ton trn, ta c: Chng trnh con hon ch nh khi s d ng Timer 1 ch 1: DELAY: PUSH 00H MOV TMOD, #10H MOV R0, #100 AAA: MOV TH1, #HIGH(-10000) ho c MOV TH1, #0D8H MOV TL1, #LOW(-10000) ho c MOV TL1, #0F0H SETB TR1 JNB TF1, $ CLR TF1 CLR TR1 DJNZ R0, AAA POP 00H RET
chnh xc (xt v m t th i gian) c a chng trnh: Tr ng h p ny cng tng t nh cc tr ng h p nh th i s d ng Timer nu cc v d trn. Tuy nhin y, chnh xc c a chng trnh nh th i khi s d ng phng php ny khng ph thu c vo gi tr c n n p cho Timer (N) m n ph thu c vo s l ng l nh s d ng trong chng trnh, s l n l p l i v s vng l p . V i v d trn (ch 1 + vng l p) th tDelay chnh xc l:
= 5.T + 11.T +t 100 + 4.T Delay (cx) Timer Timer Timer Delay (Timer ) = 1001109(s ) = 1,001109(s )
V i tDelay(Timer): th i gian nh th i c a Timer (10000 s).
6. V d 6: (T o th i gian tr ) Vi t chng trnh con t o th i gian tr 60s dng Timer 0. Bi t r ng t n s th ch anh l 12 MHz. Gi i
Tnh ton: Tm gi tr c n n p cho b nh th i v ch ho t ng c a b nh th i ny: Theo bi ta c: = 12 (MHz ) t = 60 (s ) v f Osc Delay Gi tr c n n p cho b nh th i c tnh theo cng th c: f 12.106 Osc t = 60 = 60000000 N = Delay 12 12 V y: N = -60000000 (gi tr qu l n khng th n p tr c ti p vo cc thanh ghi THx/TLx). Ta c: t = 60 (s ) = 60000000 (s ) Delay 1 12 12 T = = = = 106 (s ) = 1(s ) Timer f 6 f Timer Osc 12.10 nn ta ch n ph i Timer ch 1 (ch 16 bit) k t h p v i cc V t > 65536.T Timer Delay thanh ghi t o vng l p. G i: N l gi tr c n n p cho cc thanh ghi nh th i. [Rn] l gi tr c n n p cho thanh ghi k t h p (vng l p 1). [Rm] l gi tr c n n p cho thanh ghi k t h p (vng l p 2). N = [Rn] x [Rm] x N Ta t ch n: N = -10000 [Rm] = 100 [Rn] = 60
o Lu : N' c ch n sao cho ph h p v i qui nh ch n gi tr c n n p cho cc thanh ghi nh th i ch 1. [Rn], [Rm] 255, c bi t n u ch n [Rn], [Rm] = 0 th i u ny s tng ng v i tr ng h p ta ch n [Rn], [Rm] = 256.
Gi tr c n n p cho cc thanh ghi nh th i l -10000 v gi tr c n n p cho cc thanh ghi k t h p l 60 (cho vng l p 1), 100 (cho vng l p 2).
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Chng trnh: D a vo nh ng tnh ton trn, ta c: Chng trnh con hon ch nh khi s d ng Timer 0 ch 1: DELAY: PUSH 00H PUSH 01H MOV TMOD, #01H MOV R0, #60 AAA: MOV R1, #100 BBB: MOV TH0, #HIGH(-10000) ho c MOV TH0, #0D8H MOV TL0, #LOW(-10000) ho c MOV TL0, #0F0H SETB TR0 JNB TF0, $ CLR TF0 CLR TR0 DJNZ R1, BBB DJNZ R0, AAA POP 01H POP 00H RET chnh xc (xt v m t th i gian) c a chng trnh: Tr ng h p ny cng tng t nh cc tr ng h p nh th i s d ng Timer nu cc v d trn. Tuy nhin y, chnh xc c a chng trnh nh th i khi s d ng phng php ny khng ph thu c vo gi tr c n n p cho Timer (N) m n ph thu c vo s l ng l nh s d ng trong chng trnh, s l n l p l i v s vng l p . V i v d trn (ch 1 + vng l p) th tDelay chnh xc l:
100 + 2.T = 7.T + 1.T + 11.T +t 60 + 6.T Delay(cx) Timer Timer Timer Delay(Timer ) Timer Timer = 60066193(s ) = 60,066193(s )
V i tDelay(Timer): th i gian nh th i c a Timer (10000 s).
7. V d 7: (T o sng vung) Vi t chng trnh t o sng vung c t n s 10 KHz ng ra P1.0 v c chu k lm vi c D=50%. Bi t r ng t n s th ch anh l 12 MHz v s d ng b nh th i 0. Gi i
Tnh ton:
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Theo bi, ta c chu k lm vi c D=50% cho nn: 1 1 = 5.10 5 (s ) = 50(s ) t = 50% T = 50% = 0,5 H 3 f 10.10 tH = 50 (s) v tL = 50 (s). V y y ta ph i dng Timer 0 t o th i gian tr 50(s) cho th i gian sng m c cao v 50(s) cho th i gian sng m c th p. Theo nh trn, ta c: t = 50 (s ) v f = 12 (MHz ) Osc Delay Gi tr c n n p cho b nh th i c tnh theo cng th c: f 12.106 = 50.106 = 50 N = Osc t Delay 12 12 V y: N = -50 ho c N = CEH. Ta c: t = 50(s ) Delay 1 12 12 T = = = = 106 (s ) = 1(s ) Timer f 6 f Timer Osc 12.10 (hay N n m trong kho ng t -255 n -1) nn ta c th ch n Timer V t 256.T Timer Delay ch 1 (ch 16 bit) ho c ch 2 (ch 8 bit t ng n p l i). Chng trnh: D a vo nh ng tnh ton trn, ta c: MAIN: SETB P1.0 ACALL DELAY50US CLR P1.0 ACALL DELAY50US SJMP MAIN DELAY50US: MOV TMOD , #02H MOV TH0, #(-50) ho c MOV TH0, #0CEH SETB TR0 JNB TF0, $ CLR TR0 CLR TF0 RET END
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8. V d 8: (T o sng vung) Vi t chng trnh t o sng vung c t n s 1 KHz ng ra P1.0 v c chu k lm vi c D=50%. Bi t r ng t n s th ch anh l 12 MHz v s d ng b nh th i 0. Gi i
Tnh ton:
8051
f = 1 KHz
P1.0
50% 50%
fOSC=12 MHz
tH T tL
Theo bi, ta c chu k lm vi c D=50% cho nn: 1 1 t = 50% T = 50% = 0,5 = 5.10 4 (s ) = 500(s ) H 3 f 1.10 tH = 500 (s) v tL = 500 (s). V y y ta ph i dng Timer 0 t o th i gian tr 500(s) cho th i gian sng m c cao v 500(s) cho th i gian sng m c th p. Theo nh trn, ta c: t = 500 (s ) v f = 12 (MHz ) Osc Delay Gi tr c n n p cho b nh th i c tnh theo cng th c: f 12.106 = 500.106 = 500 N = Osc t Delay 12 12 V y: N = -500 ho c N = FE0CH. t = 500 (s ) Ta c: Delay 1 12 12 T = = = = 106 (s ) = 1(s ) Timer f 6 f Timer Osc 12.10 V t 65536.T (hay N n m trong kho ng t -65535 n -1) nn ta ch n Timer ch Timer Delay 1 (ch 16 bit). Chng trnh: D a vo nh ng tnh ton trn, ta c: MAIN: SETB P1.0 ACALL DELAY500US CLR P1.0 ACALL DELAY500US SJMP MAIN DELAY500US: MOV TMOD , #01H MOV TH0, #HIGH(-500) ho c MOV TH0, #0FEH MOV TL0, #LOW(-500) ho c MOV TL0, #0CH
Chng 4: Ho t ng c a b nh th i (Timer). SETB TR0 JNB TF0, $ CLR TR0 CLR TF0 RET END
9. V d 9: (T o sng vung) Vi t chng trnh t o sng vung c t n s 100 Hz ng ra P1.0 v c chu k lm vi c D=30%. Bi t r ng t n s th ch anh l 12 MHz v s d ng b nh th i 0. Gi i
Tnh ton:
8051
f = 100 Hz
P1.0
30% 70%
fOSC=12 MHz
tH T tL
Theo bi, ta c chu k lm vi c D=30% cho nn: 1 1 t = 30% T = 30% = 0,3 = 3.10 3 (s ) = 3000(s ) H f 100 tH = 3000 (s) v tL = 7000 (s). V y y ta ph i dng Timer 0 t o th i gian tr 3000(s) cho th i gian sng m c cao v 7000(s) cho th i gian sng m c th p. Theo nh trn, ta c (xt tr ng h p tH): t = 3000 (s ) v f = 12 (MHz ) Osc Delay Gi tr c n n p cho b nh th i c tnh theo cng th c: f 12.106 = 3000.106 = 3000 N = Osc t Delay 12 12 V y: N = -3000 ho c N = F448H. Ta c: t = 3000 (s ) Delay 1 12 12 T = = = = 106 (s ) = 1(s ) Timer f 6 f Timer Osc 12.10 (hay N n m trong kho ng t -65535 n -1) nn ta ch n Timer ch V t 65536.T Timer Delay 1 (ch 16 bit). Tng t nh trn, ta c (xt tr ng h p tL): = 12 (MHz ) t = 7000 (s ) v f Osc Delay
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Gi tr c n n p cho b nh th i c tnh theo cng th c: f 12.106 Osc t = 7000.106 = 7000 N = Delay 12 12 V y: N = -7000 ho c N = E4A8H. Ta c: t = 7000 (s ) Delay 1 12 12 T = = = = 106 (s ) = 1(s ) Timer f 6 f Timer Osc 12.10 65536.T (hay N n m trong kho ng t -65535 n -1) nn ta ch n Timer V t Timer Delay 1 (ch 16 bit). Chng trnh: D a vo nh ng tnh ton trn, ta c: MAIN: SETB P1.0 ACALL DELAY3000US CLR P1.0 ACALL DELAY7000US SJMP MAIN DELAY3000US: MOV TMOD , #01H MOV TH0, #HIGH(-3000) ho c MOV TL0, #LOW(-3000) ho c SETB TR0 JNB TF0, $ CLR TR0 CLR TF0 RET DELAY7000US: MOV TMOD , #01H MOV TH0, #HIGH(-7000) ho c MOV TL0, #LOW(-7000) ho c SETB TR0 JNB TF0, $ CLR TR0 CLR TF0 RET END
ch
MOV TH0, #0F4H MOV TL0, #48H
MOV TH0, #0E4H MOV TL0, #0A8H
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10. V d 10: (Giao ti p v i thi t b ngo i vi) M t ci c n i v i chn P1.7 v m t chuy n m ch (c ch ng d i) c n i v i chn P1.6 c a chip 8051 (xem trong hnh v ). Vi t chng trnh i u khi n c m c logic cung c p b i chuy n m ch (khi chuy n m ch thay i t v tr trn xu ng v tr d i th m t xung m c th p c t o ra t i chn P1.6) v h ci trong th i gian 1sec sau m i l n pht hi n s chuy n tr ng thi t 1 xu ng 0 t i chn P1.6.
Vcc Vcc
8051
10K
SW
Vcc
10K
P1.6
P1.7
P1.7=0 Hu coi. P1.7=1 Im lang.
fOSC=12 MHz
Gi i
HUNDRED EQU 100 ;Khai bo bi n COUNT EQU -10000 ORG 0000H MAIN: ;Ch logic 1 ng vo P1.6. JNB P1.6, $ JB P1.6, $ ;Ch logic 0 ng vo P1.6 SETB P1.7 ;Ci h . ACALL DELAY ;Th i gian 1 giy. CLR P1.7 ;T t ci. SJMP MAIN DELAY: PUSH 00H MOV TMOD, #10H MOV R0, # HUNDRED AAA: MOV TH1, #HIGH(COUNT) MOV TL1, #LOW(COUNT) SETB TR1 JNB TF1, $ CLR TF1 CLR TR1 DJNZ R0, AAA POP 00H RET END
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11. V d 11: ( m xung) M t chuy n m ch (c ch ng d i) c n i v i chn T0 (P3.4) c a chip 8051. Vi t chng trnh i u khi n m s l ng xung c t o ra b i chuy n m ch (khi chuy n m ch thay i t v tr (1) sang v tr (2) th m t xung m c th p c t o ra t i chn T0). S xung m c s ch a trong RAM n i (d ng s HEX) t i cc nh c a ch b t u t i 40H. Bi t r ng s l ng xung t o ra c kh ng ch n m trong kho ng 0 255 xung.
Gi i Tnh ton: Theo yu c u c a bi: o Vi t chng trnh m xung C u hnh cho Timer 0 l m t b m xung (Counter). o S xung n m trong kho ng 0 255 xung Ch n ch 8 bit (ch 2). Chng trnh: D MAIN: MOV MOV SETB SETB LOOP: MOV MOV JNB
CLR CLR END
a vo nh ng tnh ton trn, ta c:

TMOD, #06H TH0, #00H P3.4 TR0 A, TL0 40H, A TF0, LOOP TF0 TR0
;Ch Counter 8 bit (ch 2). ;Gi tr ban u c a b m. ;C u hnh P3.4 l ng vo. ;Kh i ng b m. ; c s xung t b m. ;C t s xung m c vo 40H. ;Ti p t c qu trnh m xung n u ;b m cha b trn. ;Xo c trn. ;D ng b m. ;K t thc chng trnh.
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12. V d 12: ( m xung) M t chuy n m ch (c ch ng d i) c n i v i chn T0 (P3.4) c a chip 8051. Vi t chng trnh i u khi n m s l ng xung c t o ra b i chuy n m ch (khi chuy n m ch thay i t v tr (1) sang v tr (2) th m t xung m c th p c t o ra t i chn T0). S xung m c s ch a trong RAM n i (d ng s HEX) t i cc nh c a ch b t u t i 50H. Bi t r ng s l ng xung t o ra c kh ng ch n m trong kho ng 0 65535 xung.
Gi i Tnh ton: Theo yu c u c a bi: o Vi t chng trnh m xung C u hnh cho Timer 0 l m t b m xung (Counter). o S xung n m trong kho ng 0 65535 xung Ch n ch 16 bit (ch 1). Chng trnh: D MAIN: MOV MOV MOV SETB SETB LOOP: MOV MOV CJNE
MOV JNB CLR CLR END
a vo nh ng tnh ton trn, ta c:

TMOD, #05H TH0, #00H TL0, #00H P3.4 TR0 A, TH0 50H, TL0 A, TH0, LOOP 51H, A TF0, LOOP TF0 TR0
;Ch Counter 16 bit (ch 1). ;Gi tr ban u c a b m (cao). ;Gi tr ban u c a b m (th p). ;C u hnh P3.4 l ng vo. ;Kh i ng b m. ; c gi tr c a b m ang ho t ng. ; c s xung m c (ph n cao). ;C t s xung m c (ph n th p). ; c s xung m c (ph n cao) ;l n n a ki m tra. ;C t s xung m c (ph n cao). ;Ti p t c qu trnh m xung n u ;b m cha b trn. ;Xo c trn. ;D ng b m. ;K t thc chng trnh.
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Chng 4: Ho t ng c a b nh th i (Timer). XI. PH N BI T P:
T o tr : Bi 1: Vi t chng trnh con mang tn DELAY500US c nhi m v t o tr 0,5ms dng Timer. (fOSC=6MHz). Bi 2: Vi t chng trnh con mang tn DELAY10MS c nhi m v t o tr 10ms dng Timer. (fOSC=12MHz). Bi 3: Vi t chng trnh con mang tn DELAY10S c nhi m v t o tr 10s dng Timer. (fOSC=12MHz). Bi 4: Vi t chng trnh con mang tn DELAY1S c nhi m v t o tr 1s dng Timer. (fOSC=11,0592MHz). Bi 5: Vi t chng trnh con delay 100s, bi t r ng fOSC dng trong h th ng l: a. 6 MHz. b. 11,0592 MHz. c. 12 MHz. d. 24 MHz Bi 6: Vi t chng trnh con delay 100ms, bi t r ng fOSC dng trong h th ng l: a. 6 MHz. b. 11,0592 MHz. c. 12 MHz. d. 24 MHz Bi 7: Vi t chng trnh con delay 1s, bi t r ng fOSC dng trong h th ng l: a. 6 MHz. b. 11,0592 MHz. c. 12 MHz. d. 24 MHz Bi 8: Vi t o n l nh t o m t xung dng ( r ng fOSC =12 MHz. T o xung: Bi 1: Dng chng trnh con DELAY500US (Bi 1 ph n t o tr ) vi t o n l nh t o sng vung f=1KHz t i P1.0. Bi 2: Dng chng trnh con DELAY10MS (Bi 2 ph n t o tr ) vi t o n l nh t o sng vung f=50Hz t i P1.1. Bi 3: Dng chng trnh con DELAY500US (Bi 1 ph n t o tr ) vi t o n l nh t o sng vung f=500Hz (D=25%) t i P1.2. Bi 4: Dng chng trnh con DELAY10MS (Bi 2 ph n t o tr ) vi t o n l nh t o sng vung f=20Hz (D=20%) t i P1.3. Bi 5: Vi t o n l nh t o chu i xung vung c f = 100 KHz t i chn P1.1 (fOSC =12 MHz). Bi 6: Vi t o n l nh t o chu i xung vung c f = 100 KHz v c chu k lm vi c D = 40% t i chn P1.2 (fOSC =12 MHz). Bi 7: Vi t o n l nh t o chu i xung vung c f = 10 KHz t i chn P1.3 (fOSC =24 MHz).
) t i chn P1.0 v i r ng xung 1ms, bi t
Bi 8: Vi t o n l nh t o chu i xung vung c f = 10 KHz v c chu k lm vi c D = 30% t i chn P1.3 (fOSC =24 MHz). Bi 9: Vi t o n l nh t o chu i xung vung c f = 10 Hz t i chn P1.4 (fOSC =12 MHz). Bi 10: Vi t o n l nh t o chu i xung vung c f = 10 Hz v c chu k lm vi c D = 25% t i chn P1.5 (fOSC =11,0592 MHz). Bi 11: Vi t o n l nh dng Timer t o sng vung f=500Hz t i P1.4. (fOSC=12MHz). Bi 12: Vi t o n l nh dng Timer t o sng vung f=20KHz t i P1.5. (fOSC=24MHz). Bi 13: Vi t o n l nh dng Timer t o 2 sng vung c cng f=1KHz t i P1.6 v P1.7. Bi t r ng sng vung t i P1.7 ch m pha hn sng vung t i P1.6 l 100 s. (fOSC=12MHz). Bi 14: Vi t o n l nh dng Timer i u khi n n giao thng t i m t giao l . Cho bi t r ng:
n Bit i u khi n Th i gian
Xanh 1 Vng 1 1 Xanh 2 Vng 2 2
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5
25s 3s 33s 3s
n sng khi bit i u khi n b ng 0 (fOSC=12MHz).
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GIO TRNH VI X
Chng 5: Ho t ng c a port n i ti p (Serial Port).
CHNG 5 HO T NG C A PORT N I TI P (SERIAL PORT)

I. M ti p. Truy n song song: S d ng nhi u dy d n truy n d li u gi a cc thi t b c kho ng cch g n nhau (kho ng vi mt). Phng php ny cho php truy n d li u v i t c cao nh s d ng nhi u dy d n truy n d li u ng th i nn t i m t th i i m c th truy n c nhi u bit thng tin nhng kho ng cch truy n th c nhi u h n ch . Truy n n i ti p: S d ng m t dy d n truy n d li u (m t dy pht i v m t dy thu v ) gi a cc thi t b c kho ng cch xa nhau (kho ng vi trm mt tr ln). Phng php ny s truy n d li u v i t c ch m hn (so v i phng php truy n song song) v ch s d ng m t dy d n truy n d li u nn t i m t th i i m ch c th truy n c m t bit thng tin nhng kho ng cch truy n th khng b h n ch nh phng php song song. Chip 8051 c m t port n i ti p (serial port) v i cc tnh nng nh sau: U: My tnh truy n d li u theo hai phng php: truy n d li u song song v truy n d li u n i
Lu : tr ng h p c trng th hai th d li u th nh t s khng b m t n u CPU c xong d li u th nh t tr c khi d li u th hai c nh n y . Cc thanh ghi ch c nng c bi t c a port n i ti p:
i l ng c trng cho t c truy n d li u nhanh hay ch m l t c baud (baud rate) hay cn g i l t n s ho t ng c a port n i ti p c th l gi tr c nh hay thay i ty theo yu c u c a ng i l p trnh. Khi ch t c baud thay i c s d ng, b nh th i 1 cung c p xung clock t c baud v ta ph i l p trnh sao cho ph h p. phin b n chip 8031/8052, b nh th i 2 cng c th c l p trnh cung c p xung clock t c baud. Gio trnh Vi x l. 154 Bin so n: Ph m Quang Tr
Chng 5: Ho t ng c a port n i ti p (Serial Port). II. THANH GHI M PORT N I TI P (SBUF):
Thanh ghi SBUF (Serial Buffer Register): c dng lu gi d li u c n pht i v d li u nh n c. Vi c ghi d li u vo thanh ghi SBUF s n p d li u pht i v vi c c d li u t thanh ghi SBUF s truy xu t d li u thu c. Thanh ghi SBUF bao g m 2 thanh ghi: Thanh ghi pht (b m pht): dng lu gi d li u c n pht i. Thanh ghi thu (b m thu): dng lu gi d li u nh n c. C u trc c a thanh ghi SBUF:
V d : Cc l MOV MOV MOV MOV
nh ghi d li u vo SBUF v c d li u t SBUF. SBUF, #45H ;Pht gi tr 45H qua port n i ti SBUF, #D ;Pht gi tr 44H qua port n i ti SBUF, A ;Pht n i dung c a A qua port n A, SBUF ; c d li u thu c t port n
p. p. i ti p. i ti p.
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Chng 5: Ho t ng c a port n i ti p (Serial Port). III. THANH GHI I U KHI N PORT N I TI P (SCON):
Thanh ghi SCON (Serial Control Register): ch a cc bit dng i u khi n ch ho t ng v bo tr ng thi c a port n i ti p. C u trc c a thanh ghi SCON:
Bit 7 6 5 4 3 2 1 0
SCON: Serial Control Register

9F 9E 9D 9C 9B 9A 99 98 SM1 REN RB8 RI SM0 SM2 TB8 TI a ch bit (HEX) Ky hieu
RI: Receive Interrupt C ngat thu. RI = 1 ngay khi ket thuc viec thu mot d lieu, RI c xoa bi phan mem. TI: Transmit Interrupt C ngat phat. TI = 1 ngay khi ket thuc viec phat mot d lieu, TI c xoa bi phan mem. RB8: Receive bit 8 Bit th 9 nhan c (che o 2 va 3). TB8: Transmit bit 8 Bit th 9 c phat (che o 2 va 3). Bit nay c set (1) hoac xoa (0) bi phan mem. REN: Receive Enable e nhan cac d lieu. Cho phep thu. Bit nay phai c set
SM2: Serial Mode 2 Bit 2 chon che o cua port noi tiep. Bit nay cho phep truyen thong a x ly che o 2 va 3; bit RI se khong c tch cc neu bit th 9 nhan c la 0. SM1: Serial Mode 1 SM0: Serial Mode 0 Bit 1 chon che o cua port noi tiep. Bit 0 chon che o cua port noi tiep.
Cc ch c a port n i ti p:
Tr c khi s d ng port n i ti p c n ph i:
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Chng 5: Ho t ng c a port n i ti p (Serial Port). V d : Kh i ng port n i ti p li u t chn TxD. Ta dng l nh: MOV SCON, #52H Gi i thch:
ch 1, cho php port thu d li u t chn RxD v s n sng pht d Gi i
SM0 = 0, SM1 = 1 cho php port ho t ng ch 1. REN = 1 cho php port n i ti p c php thu d li u. TI = 1 chu n b port n i ti p s n sng pht d li u qua chn TxD. RI = 0 chu n b port n i ti p s n sng thu d li u qua chn RxD. IV. CC CH HO T NG C A PORT N I TI P: 1. Ch 0 Thanh ghi d ch 8 bit:
Qu trnh pht d li u: Qu trnh kh i ng: Ghi d li u c n pht vo SBUF Vi c pht d li u b t u: D li u t SBUF c d ch ra chn RxD ng th i v i cc xung clock d ch bit c g i ra chn TxD (m i bit c truy n i trn chn RxD trong 1 chu k my).
ri t e
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Chng 5: Ho t ng c a port n i ti p (Serial Port). Gi n th i gian pht d li u:
Qu trnh thu d li u: Qu trnh kh i ng: Set bit cho php thu (REN=1) Xa c ng t thu (RI=0) Vi c thu d li u b t u: Cc xung clock d ch bit c g i ra chn TxD v d li u t thi t b bn ngoi c d ch vo chn RxD b i cc xung clock d ch bit ny (vi c d ch d li u vo chn RxD x y ra c nh ln c a xung clock d ch bit).
Gi n th i gian thu d li u:
ng d ng: M t ng d ng kh thi c a ch 0 (ch thanh ghi d ch bit) l m r ng thm cc ng ra cho chip 8051. M t vi m ch thanh ghi d ch n i ti p song song c th c n i v i cc chn TxD v RxD c a chip 8051 cung c p thm 8 ng xu t (xem hnh v bn d i). Cc thanh ghi d ch bit khc c th ghp cascade v i thanh ghi d ch bit u tin m r ng thm n a.
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Data
A1H
W ri t e
8051
Shift register: Thanh ghi dch bit. 8 extra outputs: 8 ngo ra m rong.
8 Extra outputs
D7 D0 DATA
SBUF 10100001B Serial port
RxD
10100001
SHIFT CLOCK
Shift Register Data Clock
TxD
Che o thanh ghi dch bit cua port noi tiep.
2. Ch 1 UART 8 bit c t c baud thay i: Trong ch 1, port n i ti p c a 8051 ho t ng nh m t b thu pht khng ng b 8 bit c t c baud thay i (UART - Universal Asynchronous Receiver Transmitter).
UART l m t b thu pht d li u n i ti p v i m i k t d li u c ng tr c b i m t bit START (logic 0) v c ng sau b i m t bit STOP (logic 1). Th nh tho ng, m t bit ch n l (Parity bit) c chn vo gi a bit d li u sau cng v bit stop. Ho t ng ch y u c a UART l bi n i d li u pht t song song thnh n i ti p v bi n i d li u thu t n i ti p thnh song song. Hnh v khung d ng d li u khi c s d ng
[1] [0] START BIT (Mc 0) D0 D1 D2 D3 D4
ch UART:
D5 D6 D7 PARITY STOP BIT BIT (Mc 1)
DATA BIT
Bit nay co the co hoac khong co tuy theo yeu cau s dung
Khung d ng c a m t d li u khi s d ng ch UART 8 bit:
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Qu trnh pht d li u: Qu trnh kh i ng: Ghi d li u c n pht vo SBUF Vi c pht d li u b t u: D li u t SBUF c d ch ra chn TxD (theo th t : Start bit 8 bit data (D0 .. D7) Stop bit) c TI=1.
rit e
T c baud: do ng i l p trnh thi t l p v c qui nh b i t c trn c a Timer 1. Th i gian c a 1 bit trn ng truy n: b ng ngh ch o c a t c baud (1 / Baud rate). C ng t pht TI = 1: khi bit stop c xu t hi n trn chn TxD. Qa trnh thu d li u: Qu trnh kh i ng: M t s chuy n tr ng thi t m c 1 xu ng m c 0 t i chn RxD (t c xu t hi n bit Start) Vi c thu d li u b t u: 8 bit d li u c d ch vo trong SBUF (theo th t : D0D1D7) Stop bit (bit th 9) c a vo bit RB8 (thu c thanh ghi SCON) c RI=1.
T c baud: do ng i l p trnh thi t l p v c qui nh b i t c trn c a Timer 1. Hai i u ki n b t bu c th c hi n qu trnh thu d li u nh trn: o RI = 0 Yu c u ny c ngha l chip 8051 c xong d li u tr c v xo c RI.. o (SM2 = 1 v Stop bit = 1) ho c SM2 = 0 ch p d ng trong ch truy n thng a x l. Yu c u ny c ngha l khng set c RI b ng 1 trong ch truy n thng a x l khi bit d li u th 9 l 0. C ng t thu RI = 1: khi 8 bit d li u c n p vo SBUF. Lu : Tr ng h p cc tn hi u nhi u xu t hi n trn ng truy n (lm cho ng truy n xu t hi n m c th p) d n n lm cho b thu nh n d ng sai, cho l s xu t hi n c a START bit (logic 0) v ti n hnh th c hi n qu trnh thu d li u, t d n n k t qu nh n vo s khng ng. trnh i u ny x y ra th khi ng truy n c s chuy n tr ng thi t 1 xu ng 0, b thu yu c u m c 0 ny ph i Gio trnh Vi x l. 160 Bin so n: Ph m Quang Tr
c duy tr trn ng truy n trong m t kho ng th i gian xc nh. N u khng m b o c nh th , b thu c gi s r ng nh n c nhi u thay v nh n c START bit h p l . Lc b thu s c thi t l p l i, quay v tr ng thi ngh v ch s chuy n tr ng thi t 1 xu ng 0 k ti p trn ng truy n. 3. Ch 2 UART 9 bit c t c baud c nh: (Tng t nh UART 8 bit, ch khc s bit d li u l 9 bit)
4. Ch 3 UART 9 bit c t c baud thay i: (Tng t nh UART 9 bit, ch khc
t c baud c th thay i)
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Transmit
Receive
Trans
V. KH I NG V TRUY XU T CC THANH GHI: 1. Bit cho php thu (nh n) d li u (REN: Receive Enable): Cng d ng: dng cho php (ho c khng cho php) nh n cc k t d li u. REN = 1: Cho php nh n d li u l nh th c hi n: SETB REN REN = 0: Khng cho php d li u l nh th c hi n: CLR REN 2. Bit d li u th 9: Cng d ng: ty thu c vo c tnh k thu t c a thi t b n i ti p m c th yu c u ho c khng yu c u bit d li u th 9. Khi pht d li u: bit d li u th 9 ph i c n p vo bit TB8 c a SCON tr c khi pht i. Khi thu d li u: bit d li u th 9 s c n p vo bit RB8 c a SCON sau khi thu xong. 3. Bit ki m tra ch n / l (P: Parity): Cng d ng: Trong chip 8051 th bit Parity c dng thi t l p vi c ki m tra ch n cho 8 bit d li u ch a trong thanh ghi A (th ng dng ki m tra l i khi truy n d li u). P = 1 S l ng bit 1 trong thanh ghi A l s l . P = 0 S l ng bit 1 trong thanh ghi A l s ch n. ho c S l ng bit 1 trong thanh ghi A v bit P l m t s ch n. ch 1 (UART 8 bit) th bit ch n/l do chip 8051 t o ra c th c thm vo t i bit th 8 (v tr D7) v khi ta ch c th truy n d li u ch c 7 bit.
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Recei
ch 2, 3 (UART 9 bit) th bit ch n/l do chip 8051 t o ra c th c thm vo t i bit th 9 (ngha l thm vo bit TB8 c a SCON) v khi ta c th truy n d li u c 8 bit.
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP
Bit th 9
DATA (8 bit)
V d : Truy n d li u (ch 2, 3 UART 9 bit) ch a trong thanh ghi A thng qua port n i ti p v i yu c u truy n 8 bit d li u + 1 bit ki m tra ch n (bit P). Chu i l nh th c hi n: MOV C, P ;Chuy n bit ki m tra ch n (bit P) vo TB8 v MOV TB8, C ;bit ny tr thnh bit th 9. MOV SBUF, A ;Truy n 8 bit d li u trong A thng qua port. V d : Truy n d li u (ch 2, 3 UART 9 bit) ch a trong thanh ghi A thng qua port n i ti p v i yu c u truy n 8 bit d li u + 1 bit ki m tra l (l y b bit P). Chu i l nh th c hi n: MOV C, P ;Bi n i bit ki m tra ch n (bit P) thnh bit CPL C ;ki m tra l , chuy n bit ki m tra l vo TB8 v MOV TB8, C ;bit ny tr thnh bit th 9. MOV SBUF, A ;Truy n 8 bit d li u trong A thng qua port. V d : Truy n d li u (ch 1 UART 8 bit) ch a trong thanh ghi A thng qua port n i ti p v i yu c u truy n 7 bit d li u + 1 bit ki m tra ch n (bit P). Chu i l nh th c hi n: CLR ACC.7 MOV C, P MOV ACC.7, C MOV SBUF, A 4. Cc c ng t c a port n i ti p: ;Xo bit th 8 (D7) trong thanh ghi A. ;Sao chp bit ki m tra ch n vo C. ; t bit ki m tra ch n vo bit th 8 trong A. ;Truy n 7 bit d li u c ng bit ki m tra ch n.
T ph n trnh by trn y, ta c th th y r ng: Thng qua vi c ki m tra c ng t TI c th bi t c chip 8051 s n sng truy n m t byte d li u hay cha. C n ch r ng, y c TI c t (TI = 1) khi 8051 hon t t vi c truy n m t byte d li u, cn c xo (TI=0) th ph i do ng i l p trnh th c hi n b ng l nh (CLR TI). Cng nn nh r ng, n u ghi m t byte vo thanh ghi SBUF tr c khi c TI c t (TI = 1) th s c nguy c b m t ph n d li u tr c do cha k p truy n i. C TI c th c ki m tra b ng l nh (JNB TI,) ho c s d ng phng php ng t (s c trnh by trong chng ti p theo).
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Thng qua vi c ki m tra c ng t RI c th bi t c chip 8051 nh n xong m t byte d li u hay cha. C n ch r ng, y c RI c t (RI = 1) khi 8051 hon t t vi c nh n m t byte d li u, cn c xo (RI=0) th ph i do ng i l p trnh th c hi n b ng l nh (CLR RI). Cng nn nh r ng, n u khng ti n hnh c t n i dung c a thanh ghi SBUF vo ni an ton th s c nguy c b m t d li u v a nh n c do d li u ti p theo c chuy n vo. C RI c th c ki m tra b ng l nh (JNB RI,) ho c s d ng phng php ng t (s c trnh by trong chng ti p theo). Lu v o n l nh ki m tra v thu m t d li u n i ti p t thi t b bn ngoi vo chip 8051 (ch a vo A):
Lu v o n l nh ki m tra v pht m t d li u n i ti p t chip 8051 (ch a trong A) ra thi t b bn ngoi:
VI. TRUY N THNG A X
L:
Cc ch 2 v 3 l cc ch d phng cho vi c truy n thng a x l. Trong cc ch ny, 9 bit d li u c thu v bit th 9 a n RB8. Port c th c l p trnh sao cho khi bit stop c nh n, ng t do port n i ti p ch c tch c c n u RB8=1. c trng ny c th c b ng cch set bit SM2 trong thanh ghi SCON b ng 1. M t ng d ng cho i u ny l m t mi tr ng m ng s d ng nhi u 8051 c s p x p theo m hnh ch /t (master/slave) nh hnh d i y.
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Khi b vi x l ch (master) mu n truy n m t khi d li u n m t trong nhi u b x l t (slave), tr c tin b vi x l ch pht i m t byte a ch nh n d ng b vi x l t ch. M t byte a ch khc v i m t byte d li u ch bit th 9 l 1 ( i v i byte a ch ) v l 0 ( i v i byte d li u). M t byte a ch ng t t t c cc b vi x l t cho m i m t b vi x l t c th kh o st byte nh n c ki m tra xem c ph i l b vi x l t ang c nh a ch khng. B vi x l t c nh a ch s xo bit SM2 c a mnh v chu n b nh n cc byte d li u theo sau. Cc b vi x l t khng c nh a ch c cc bit SM2 c a chng c set b ng 1 v th c thi cc cng vi c c a ring chng, b qua khng nh n cc byte d li u. Cc b vi x l ny s c ng t l n n a khi b vi x l ch pht ti p byte a ch k . Cc s c th c th c nu ra sao cho m t khi lin k t ch t c thi t l p, b vi x l t cng c th pht n b vi x l ch . Mu m o y l khng s d ng bit d li u th 9 sau khi lin k t v a c thi t l p (ng c l i cc b vi x l t khc c th c ch n m t cch khng c ). SM2 khng nh h ng n ch 0, v trong ch 1 th bit ny c th c dng ki m tra s h p l c a bit stop. ch 1 thu, n u SM2 = 1, ng t thu s khng c tch c c tr khi bit stop thu c l h p l . VII. T C BAUD C A PORT N I TI P: 1. T c baud cho ch 0:
Baud rate =
2. T c baud cho ch 1, 3:
f OSC 12
Timer I overflow rate 16
Baud rate =
Baud rate =
3. T c baud cho ch 2:
Timer I overflow rate 32
Baud rate =
f OSC 32
Baud rate =
f OSC 64
Lu : o Sau khi h th ng reset th bit SMOD = 0 (ch m c nh). o V thanh ghi PCON khng c nh a ch t ng bit, nn tng g p i t c baud (t c lm cho SMOD=1) ta ph i th c hi n b ng nh ng dng l nh sau: MOV A, PCON ;L y gi tr t thanh ghi PCON. SETB ACC.7 ;SMOD = 1. MOV PCON, A ;Chuy n gi tr m i vo PCON.
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4. S d ng Timer 1 lm xung clock t c baud cho port n i ti p: K thu t t o xung clock t c baud b ng Timer 1:
V ch n ch : th ng dng Timer 1 ch 8 bit t ng n p l i (Mode 2). Cc t c baud r t ch m c th nh n c b ng cch s d ng ch 16 bit (Mode 1). V d : Kh i ng thanh ghi TMOD dng T1 lm b t o xung t c baud (cho T1 ho t ng ch 2): MOV TMOD, #2xH x: dnh cho Timer 0 V ch n t c baud: G i M l gi tr c n n p cho thanh ghi TH1 c t c baud nh yu c u, ta c:
M=
f Timer Timer 1 overflow rate
M:
f f = Timer Timer 12
Baud rate =
Timer 1 overflow rate 16 (hoac 32)
V y ta c:
f 1 M = Osc 12 Baud rate 16 (hoac 32)
M=
f Osc
, ( SMOD = 1) ho c M =
f Osc 384 Baud rate
, ( SMOD = 0)
MHz.
192 Baud rate Trong : fOsc (Hz): t n s th ch anh. Baud rate (bps): t c baud c a port n i ti p. V d : T o t c baud l 1200 v i tr ng h p SMOD = 0 v chip 8051 dng th ch anh 12 G i M l gi tr c n n p cho thanh ghi TH1 c t c baud nh yu c u, ta c:
M=
12.10 6 = 26,0416 -26 (lm trn s ).
f Osc 384 Baud rate
, ( SMOD = 0)
M=
384 1200
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Chuy n gi tr ny vo thanh ghi TH1: MOV TH1, #(-26) ho c
Tr ng H Cng nghi p Tp.HCM. MOV TH1, #E6H
Ch : Do vi c lm trn cho nn s c m t sai s nh trong vi c xc nh chnh xc t c baud. Cho nn c t c baud chnh xc trong vi c truy n d li u thng qua port n i ti p th ng i ta th ng dng th ch anh dao ng c t n s 11,0592 MHz (thay v l 12 MHz). V d : 6 11,0592.10 M= = 24 (khng c n ph i lm trn s ) 384 1200
B ng tnh t c baud cho port n i ti p:
VIII. CC B C C B N L P TRNH PORT N I TI P:

Trong cc ch truy n d li u n i ti p c a 8051 nu trn th trn th c t s d ng, th c hi n vi c thu v pht d li u n i ti p gi a chip 8051 v i cc thi t b khc (8051, my tnh, cc thi t b SPI,) th ng ng i l p trnh ch s d ng hai ch sau : Mode 1 (UART 8 bit c t c baud thay i) ho c Mode 3 (UART 9 bit c t c baud thay i). Cn hai ch cn l i th r t t s d ng khi c n truy n d li u n i ti p. Cho nn y chng ta ch xem xt n trnh t th c hi n vi c l p trnh (bao g m thao tc kh i ng v i u khi n thu/pht d li u) 8051 c th truy n (pht) v nh n (thu) d li u thng qua port n i ti p theo hai ch UART nu trn.
1. L p trnh 8051 truy n (pht) d li u n i ti p: Ch n ch ho t ng cho port n i ti p: MOV SCON, #...(1) Ch n ch ho t ng Timer 1, cho bit GATE=0 v C/T=0: MOV TMOD, #...(2) Ch n gi tr thch h p (cn c vo t c baud) cho Timer 1: MOV TH1, #...(3) Cho Timer 1 ch y: SETB TR1 Ki m tra xem pht xong ton b d li u tr c hay cha? JNB TI, $ ho c WAIT: JNB TI, WAIT Xo c ng t pht TI (chu n b cho l n pht d li u ti p theo): CLR TI Gio trnh Vi x l. 167 Bin so n: Ph m Quang Tr

Ghi d li u c n pht vo port n i ti p pht i: MOV SBUF, ...(4) Quay tr l i b c 5 pht m t d li u ti p theo.
Lu :
(1): Gi tr dng qui nh ch ho t ng c a port n i ti p. n gi n trong vi c l p trnh, ta c th kh i ng thanh ghi SCON theo nh trnh by d i y:
Mode 1:
...(1) = 52H
Mode 3:
...(1) = D2H
(2): Gi tr dng qui nh ch ho t ng c a Timer 1 (dng t o t c baud cho vi c truy n d li u n i ti p). n gi n trong vi c l p trnh, ta c th kh i ng thanh ghi TMOD theo nh trnh by d i y (ch y u y ta ch c n s d ng Timer 1 Mode 2 Ch 8 bit t ng n p l i):
Mode 2:
...(2) = 20H
(3): Gi tr dng qui nh t c baud cho port n i ti p. Gi tr ny ph thu c vo t n s th ch anh, bit SMOD v t c baud m ng i l p trnh mong mu n (xem thm B ng tnh t c baud cho port n i ti p nh trn trnh by). ...(3) = M
M= f Osc 192 Baud rate
, ( SMOD = 1) ho c M =
f Osc 384 Baud rate
, ( SMOD = 0)
fOsc (Hz): t n s th ch anh. Baud rate (bps): t c baud c a port n i ti p. (4): D li u c n pht i thng qua port n i ti p. D li u ny c th l n i dung c a m t nh , thanh ghi ho c m t gi tr t c th i. Trong : Nn nh r ng, n u c yu c u th bit g i km theo (v d nh bit Parity) c n ph i thm vo tr c khi ti n hnh qu trnh pht d li u (Mode 1: km thm vo v tr c a bit D7, Mode 3: km thm vo v tr c a bit TB8).
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2. L p trnh 8051 nh n (thu) d li u n i ti p: Ch n ch ho t ng cho port n i ti p: MOV SCON, #...(1) Ch n ch ho t ng Timer 1, cho bit GATE=0 v C/T=0: MOV TMOD, #...(2) Ch n gi tr thch h p (cn c vo t c baud) cho Timer 1: MOV TH1, #...(3) Cho Timer 1 ch y: SETB TR1 Ki m tra xem thu ton b d li u hay cha? JNB RI, $ ho c WAIT: JNB RI, WAIT Xo c ng t thu RI (chu n b cho l n thu d li u ti p theo): CLR RI C t d li u v a thu c vo ni an ton (trnh b m t d li u): MOV ...(4), SBUF Quay tr l i b c 5 nh n m t d li u ti p theo. Lu : (1): Xem thm L p trnh 8051 truy n (pht) d li u n i ti p. (2): Xem thm L p trnh 8051 truy n (pht) d li u n i ti p. (3): Xem thm L p trnh 8051 truy n (pht) d li u n i ti p. (4): a ch c a m t nh , thanh ghi m d li u thu c t port n i ti p s lu gi vo trong .
Nn nh r ng, n u c yu c u th bit g i km theo (v d nh bit Parity) c n ph i c x l tr c khi ti n hnh vi c c t d li u thu c (Mode 1: n m t i v tr c a bit D7, Mode 3: n m t i v tr c a bit RB8).
IX. CC V D MINH H A: 1. V d 1: (Ch n t c baud) Chip 8051 s d ng th ch anh 11,0592MHz. Hy xc nh gi tr c n n p cho thanh ghi TH1 c c cc t c baud: 9600, 2400, 1200 (n u SMOD=0) v 19200 (n u SMOD=1).
Gi i Xt tr ng h p SMOD=0: G i M l gi tr c n n p cho thanh ghi TH1 c t c baud nh yu c u, ta c:
Baud rate = 9600

M=
11,0592 10 384 9600 6 = 3 (TH1) = -3 hay (TH1) = FDH.
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Baud rate = 2400
M=
11,0592 10 6
= 12 (TH1) = -12 hay (TH1) = F4H.
384 2400 Baud rate = 1200
M=
11,0592 10 384 1200
6 = 24 (TH1) = -24 hay (TH1) = F8H.
Xt tr ng h p SMOD=1: G i M l gi tr c n n p cho thanh ghi TH1 c t c baud nh yu c u, ta c:

Baud rate = 19200

M=
11,0592 10 6 = 3 (TH1) = -3 hay (TH1) = FDH.
19219200
2. V d 2: (Kh i ng port n i ti p) Vi t m t chu i l nh kh i ng port n i ti p sao cho port ny ho t ng nh m t UART 8 bit v i t c baud l 2400, s d ng Timer1 cung c p xung clock t c baud. Chip 8051 s d ng th ch anh 12MHz.
Gi i kh i ng port n i ti p c c u hnh nh trn ta c n tc ng n cc thanh ghi: SCON, TMOD, TCON v TH1.
SM0 = 0, SM1 = 1, SM2 = 0 ch UART 8 bit. REN = 1 cho php port n i ti p thu d li u. TI = 1 cho php port s n sng pht d li u (b m pht r ng). RI = 0 cho php port s n sng thu d li u (b m thu r ng).
GATE = 0, C/T = 0, M1 = 1, M0 = 0 Timer 1
ch nh th i 8 bit t n p l i.
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Chng 5: Ho t ng c a port n i ti p (Serial Port). TR1 = 1 cho php Timer 1 ho t ng.
G i M l gi tr c n n p cho thanh ghi TH1 c t c baud nh yu c u, ta c:

M= f Osc 384 Baud rate ( SMOD = 0)
M=
12.10
6 = 13,02 -13 (lm trn s ).
384 2400
Chuy n gi tr ny vo thanh ghi TH1: MOV TH1, #(-13)
ho c
MOV TH1, #F3H
Chu i l nh kh i ng port n i ti p c vi t nh sau: MOV SCON, #52H MOV TMOD, #20H MOV TH1, #-13 SETB TR1
3. V d 3: (Chng trnh con pht (xu t) d li u) Gi s port n i ti p c kh i ng (nh v d 1). Hy vi t m t chng trnh con pht d li u (d ng 7 bit) ch a trong thanh ghi A ra port n i ti p v i bit ki m tra l l bit th 8. Ch r ng, vi c tr v t chng trnh con ny khng c lm thay i n i dung thanh ghi A.
Gi i
Ba l nh u tin t bit ki m tra l vo bit 7 c a thanh ghi A (ACC.7). Do bit P trong thanh ghi PSW c thi t l p ki m tra ch n cho gi tr trong thanh ghi A, cho nn bit ny ph i c l y b tr thnh bit ki m tra l tr c khi t vo ACC.7. L nh JNB t o ra m t vng l p ch ki m tra c ng t pht TI cho n khi c ny c set b ng 1. Khi TI=1 (do vi c pht k t tr c v a k t thc), bit ny s c xa v sau k t trong thanh ghi A c ghi vo b m c a port n i ti p SBUF v
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vi c pht k t c b t u l n trn k c a b m t o xung clock cho port n i ti p. Sau cng bit ACC.7 s c xa gi tr tr v gi ng nh khi m 7 bit c chuy n n chng trnh con.
4. V d 4: (Chng trnh con thu (nh n) d li u) Gi s port n i ti p c kh i ng (nh v d 1). Hy vi t m t chng trnh con thu d li u t port n i ti p v n p gi tr thu c vo thanh ghi A (d li u thu c c d ng 7 bit d li u + 1 bit ki m tra l , tng t d li u t v d 2). S d ng bit th 8 thu c lm bit ki m tra l v set c nh C n u c l i ch n l .
Gi i
Chng trnh con ny b t u b ng vi c ch c ng t thu RI c set b ng 1 ch ra r ng k t s n sng trong b m thu SBUF ( c c). Khi RI=1, l nh JNB chuy n i u khi n n l nh ti p theo sau l nh ny. C RI c xa v m trong SBUF c ch a vo thanh ghi A. Do bit P trong thanh ghi PSW c thi t l p ki m tra ch n cho gi tr trong thanh ghi A. Cho nn bit ny s c set b ng 1 n u n i dung thanh ghi A (t c d li u v a thu c) c ch a bit ki m tra l bit th 7 c a thanh ghi ny v ng c l i th bit ny s c xo b ng 0 thng qua l nh CPL. Vi c di chuy n bit P vo trong c nh CY s lm cho CY=0 n u khng c l i ho c CY=1 n u c m t l i ch n l . Sau cng bit ACC.7 s c xa m b o r ng ch c m 7 bit c tr v cho chng trnh g i.
5. V d 5: (Truy n d li u) Vi t chng trnh cho 8051 (fOsc=11,0592MHz) truy n lin t c m t k t A thng qua port n i ti p v i t c 4800 baud (Mode 1).
Gi i
Tnh ton: D a vo nh ng cng th c h c, ta c: (SCON) = 52H Port n i ti p (Mode 1) Timer 1 (Mode 2) (TMOD) = 20H (TH1) = -6 v i (SMOD) = 0 Baud rate = 4800 v fOsc=11,0592MHz
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Chng trnh: D a vo nh ng tnh ton trn, ta c: MOV SCON, #52H ;UART 8 bit, t c baud thay i. MOV TMOD, #20H ;Ch 8 bit t n p l i. MOV TH1, #(-6) ;Baud rate = 4800. SETB TR1 ;Kh i ng Timer 1. LOOP: JNB TI, $ ;Ki m tra pht d li u tr c hon t t? CLR TI ;Xo c TI, chu n b cho l n pht k ti p. MOV SBUF, #A ;Pht k t A. SJMP LOOP ;L p l i qu trnh pht. END ;K t thc chng trnh.
6. V d 6: (Truy n d li u) Vi t chng trnh cho 8051 (fOsc=11,0592MHz) truy n lin t c chu i k t TTCNDT thng qua port n i ti p v i t c 19200 baud (Mode 1).
Gi i
Tnh ton: Port n i ti p (Mode 1) Timer 1 (Mode 2) Baud rate = 19200 v fOsc=11,0592MHz (SCON) = 52H (TMOD) = 20H (TH1) = -3 v i (SMOD) = 1
Chng trnh: D a vo nh ng tnh ton trn, ta c: MOV SCON, #52H ;UART 8 bit, t c baud thay i. MOV TMOD, #20H ;Ch 8 bit t n p l i. MOV TH1, #(-3) ;Baud rate = 19200. MOV A, PCON ;L y gi tr t thanh ghi PCON. SETB ACC.7 ;SMOD = 1. MOV PCON, A ;Chuy n gi tr m i vo PCON. SETB TR1 ;Kh i ng Timer 1. LOOP: MOV DPTR, #MYDATA ;N p con tr vng d li u. NEXT: CLR A ;Xo ACC, A = 0 MOVC A, @A+DPTR ;L y d li u t i nh ROM do ;(A+DPTR) tr n a vo A. JZ EXIT ;Thot n u l k t Null. JNB TI, $ ;Ki m tra pht d li u tr c hon t t? CLR TI ;Xo c TI, chu n b pht ti p. MOV SBUF, A ;Pht d li u ra port n i ti p. INC DPTR ;Tng con tr d li u. SJMP NEXT ;L p l i qu trnh pht k t k ti p. EXIT: SJMP LOOP ;L p l i t u. MYDATA: DB TTCNDT,0 ;D li u c n truy n i, c k t Null. END ;K t thc chng trnh.
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8. V d 8: (Nh n d li u) Vi t chng trnh cho 8051 (fOsc=11,0592MHz) nh n lin t c cc d li u thng qua port n i ti p v i t c 4800 baud (Mode 1) v g i cc d li u nh n c n P1.
Gi i
Chng trnh: D a vo nh ng tnh ton trn, ta c: MOV SCON, #52H ;UART 8 bit, t c baud thay i. MOV TMOD, #20H ;Ch 8 bit t n p l i. MOV TH1, #(-6) ;Baud rate = 4800. SETB TR1 ;Kh i ng Timer 1. LOOP: JNB RI, $ ;Ki m tra thu d li u hon t t? CLR RI ;Xo c RI, chu n b cho l n thu k ti p. MOV A, SBUF ;Thu v c t d li u vo ACC. MOV P1, A ;G i d li u thu c ra P1. SJMP LOOP ;L p l i qu trnh pht. END ;K t thc chng trnh.
9. V d 9: (Thu v pht d li u) Cho port n i ti p c a 8051 (fOsc=11,0592MHz) c n i v i c ng COM c a my tnh PC (gi s r ng trn my tnh c s n chng trnh g i v nh n d li u n i ti p thng qua c ng COM). Hy vi t chng trnh cho 8051 th c hi n cc cng vi c sau: G i cu thng bo READY n my tnh. Lin t c nh n cc d li u n i ti p t my tnh g i n v chuy n cc d li u ny ra P1 c a 8051. Lin t c l y cc d li u t P2 c a 8051 v pht cc d li u ny n my tnh thng qua port n i ti p. Bi t r ng 8051 truy n d li u n i ti p Mode 1 v i t c baud l 9600.
Gi i
Chng trnh: D a vo nh ng tnh ton trn, ta c: MOV P2, #0FFH ;C u hnh P2 l c ng vo. MOV SCON, #52H ;UART 8 bit, t c baud thay i. MOV TMOD, #20H ;Ch 8 bit t n p l i. MOV TH1, #(-3) ;Baud rate = 4800. SETB TR1 ;Kh i ng Timer 1. MOV DPTR, #MYDATA ;N p con tr vng d li u. NEXT: ;Ph n pht cu thng bo CLR A ;Xo ACC, A = 0 MOVC A, @A+DPTR ;L y d li u t i nh ROM do
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Chng 5: Ho t ng c a port n i ti p (Serial Port). JZ ACALL INC SJMP EXIT: ACALL MOV MOV ACALL SJMP INDATA: JNB CLR MOV RET OUTDATA: JNB CLR MOV RET MYDATA: DB END EXIT OUTDATA DPTR NEXT INDATA P1, A A, P2 OUTDATA EXIT RI, $ RI A, SBUF
;(A+DPTR) tr n a vo A. ;Thot n u l k t Null. ;Pht d li u, cu thng bo. ;Tng con tr d li u. ;L p l i qu trnh pht k t k ti p. ;Ph n pht/thu d li u gi a 8051 v PC. ;Thu d li u t PC. ;Chuy n d li u ny n P1. ;L y d li u t P2. ;Pht d li u ny n PC. ;L p l i chu trnh lm vi c. ;Chng trnh con thu d li u. ;Ki m tra thu d li u hon t t? ;Xo c RI, chu n b cho l n thu ti p. ;Thu v c t d li u vo ACC.
;Chng trnh con pht d li u. TI, $ ;Ki m tra pht d li u tr c hon t t? TI ;Xo c TI, chu n b cho l n pht ti p. SBUF, A ;Pht d li u ch a trong ACC.
READY,0
;Cu thng bo, c k t Null. ;K t thc chng trnh.
X. PH N BI T P:
Bi 1: Vi t o n l nh c m t chu i data ch a trong RAM n i t a ch 30H n 50H v xu t ra m t thi t b (v d nh mn hnh tinh th l ng LCD) c n i v i port n i ti p c a 8051 (ch UART 8 bit, 2400 baud). Cho fOSC=11,0592 MHz. Bi 2: Vi t o n l nh nh n m t chu i data t m t thi t b ngoi (v d nh my c m v ch) n i v i 8051 qua port n i ti p (ch UART 8 bit, 4800 baud) v ghi data vo RAM n i t a ch 40H. Bi t r ng chu i data g m 20 byte v fOSC=11,0592 MHz. Bi 3: Vi t o n l nh l y m t chu i data ch a trong RAM ngoi b t u t a ch 2000H v xu t ra m t thi t b c n i v i port n i ti p c a 8051 (ch UART 8 bit, 1200 baud). Chu i k t thc b i k t EOT (c m ASCII l 04H) v k t ny cng c xu t ra (fOSC=11,0592 MHz). Bi 4: Lm l i bi 3 nhng khng xu t k t EOT. Bi 5: Vi t o n l nh nh n m t chu i data t m t thi t b ngoi n i v i 8051 qua port n i ti p (ch UART 8 bit, 9600 baud) v ghi data vo RAM ngoi b t u t a ch 4000H. Chu i data b t u b ng k t STX (02H) v k t thc b ng k t ETX (03H). Khng ghi hai k t ny vo RAM. Cho fOSC=11,0592 MHz. Bi 6: Vi t chng trnh con RAM ngoi xu t ra port n i ti p ch b ng k t NULL (00H). o n l nh g DPTR tr c khi g i chng trnh con mang tn XUAT c nhi m v l y m t chu i data ch a trong UART 9 bit. Bit th 9 l bit parity ch n. Chu i data k t thc i chng trnh con XUAT s t a ch b t u c a chu i vo XUAT. Gi s port n i ti p c kh i ng.
Bi 7: Vi t chng trnh con mang tn NHAP c nhi m v nh p m t chu i data g m 30 byte t port n i ti p ch UART 9 bit, bit th 9 l bit parity l . N u data nh n c khng b l i th ghi
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vo m t vng nh c a RAM n i, n u b l i th khng ghi. o n l nh g i chng trnh con NHAP s t a ch u c a vng nh vo thanh ghi R0 tr c khi g i chng trnh con NHAP. Gi s port n i ti p c kh i ng.
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GIO TRNH VI X
Chng 6: Ho t ng ng t (Interrupt).
CHNG 6 HO T NG NG T (INTERRUPT)
I. M U: 1 CPU CH TH C THI C 1 L NH T I M T TH I I M. Ng t (Interrupt) l vi c x y ra m t i u ki n (m t s ki n) lm cho chng trnh ang th c thi (chng trnh chnh) b t m d ng quay sang th c thi m t chng trnh khc (chng trnh x l ng t) r i sau quay tr v th c thi ti p chng trnh ang b t m d ng. Cc ng t ng vai tr quan tr ng trong vi c thi t k v hi n th c cc ng d ng c a b vi i u khi n. Cc ng t cho php h th ng p ng m t s ki n theo cch khng ng b v x l s ki n trong khi m t chng trnh khc ang th c thi. M t h th ng c i u khi n b i ng t cho ta o t ng nhi u cng vi c ang c vi x l th c hi n ng th i. CPU d nhin khng th th c thi nhi u hn m t l nh m t th i i m nhng CPU c th t m ngng vi c th c thi m t chng trnh th c thi m t chng trnh khc r i sau quay v th c thi ti p t c chng trnh ang b t m ngng, i u ny th tng t nh vi c CPU r i kh i chng trnh g i th c thi chng trnh con b g i r i sau quay tr v chng trnh g i. C n ph i phn bi t s gi ng v khc nhau gi a ng t v g i chng trnh con: Gi ng nhau: Khi x y ra i u ki n tng ng th CPU s t m d ng chng trnh chnh ang th c thi th c thi m t chng trnh khc (chng trnh con / chng trnh x l ng t) r i sau (sau khi x l xong chng trnh con / chng trnh x l ng t) th CPU s quay v th c thi ti p t c chng trnh chnh ang b t m d ng. Khc nhau: Ng t Th i i m x y ra s ki n Chng trnh con
Khng bi t tr c (hay x y ra khng Bi t tr c (hay x y ra ng b v i ng b v i chng trnh chnh). chng trnh chnh).
Nguyn nhn d n n s ki n
Do cc tn hi u i u khi n t Timer, Do l nh g i chng trnh con Serial port v bn ngoi chip. (ACALL, LCALL).
Chng trnh x l ng t (t c l chng trnh m CPU ph i th c hi n khi c m t ng t x y n) c g i l trnh ph c v ng t ISR (ISR: Interrupt Service Routine) hay trnh qu n l ng t (Interrupt Handler). ISR c th c thi nh m p ng m t ng t v trong tr ng h p t ng qut th c hi n vi c xu t nh p i v i m t thi t b . Khi m t ng t xu t hi n, vi c th c thi chng trnh chnh t m th i b d ng l i v CPU th c thi vi c r nhnh n trnh ph c v ng t ISR. CPU s th c thi ISR th c hi n m t cng vi c v k t thc vi c th c hi n cng vi c ny khi g p l nh quay v t trnh ph c v ng t (l nh RETI), sau chng trnh chnh ti p t c c th c thi t i ni b t m d ng. Ta c th ni chng trnh Gio trnh Vi x l. 177 Bin so n: Ph m Quang Tr
Chng 6: Ho t ng ng t (Interrupt). chnh c th c thi
Tr ng H Cng nghi p Tp.HCM. m c ng t (Interrupt level).
m c n n (Base level), cn ISR c th c thi
Bi u di n vi c th c thi chng trnh c ng t v khng c ng t:
M t v d v ng t i n hnh l nh p thng s i u khi n s d ng bn phm. Ta hy kh o st m t ng d ng c a l viba. Chng trnh chnh c th i u khi n thnh ph n cng su t c a l th c hi n vi c n u n ng. Tuy nhin trong khi ang n u, h th ng ph i p ng vi c nh p s li u b ng tay trn c a l (ch ng h n nh ta mu n yu c u rt ng n b t hay ko di thm th i gian n u), i u ny c th x y ra t i b t c th i i m no trong qu trnh n u. Tr ng h p ta khng s d ng ng t: Nh ta bi t, m t h th ng ch c th th c thi m t cng vi c t i m t th i i m. Cho nn khi h th ng ang th c thi vi c n u n ng th n khng th th c thi vi c p ng nh p s li u khi n x y ra v ng c l i. V th trong tr ng h p ny h th ng ph i th c hi n cho xong vi c n u n ng r i m i th c hi n ti p vi c p ng nh p s li u (i u ny v l v khi n u n ng xong th c n g ph i i u ch nh th i gian n a) ho c ng c l i h th ng ph i th c hi n cho xong vi c p ng nh p s li u r i m i th c hi n ti p vi c n u n ng (i u ny cng v l v khng th bi t tr c c vi c nh p s li u x y ra lc no, cho nn qu trnh h th ng ch i vi c nh p s li u s tr nn v ngha). Tr ng h p ta s d ng ng t: Ta nh n th y r ng vi c n u n ng l vi c di n ra lin t c t u n cu i, cn vi c p ng nh p s li u ch x y ra khi ta nh n bn phm (khng xc nh c th i i m x y ra). V th , ta phn c p cho chng trnh chnh (m c n n) s i u khi n thnh ph n cng su t c a l th c hi n vi c n u n ng, cn vi c p ng nh p s li u s do ng t i u khi n (m c ng t). Bnh th ng th l th c hi n vi c n u n ng nh xc nh, khi ng i s d ng nh n bn phm th m t tn hi u ng t c t o ra v chng trnh chnh s b t m th i d ng l i. ISR c th c thi c m phm v thay i cc i u ki n n u tng ng, sau k t thc b ng cch chuy n i u khi n tr v chng trnh chnh. Chng trnh chnh c th c thi ti p t ni t m d ng. i u quan tr ng trong v d nu trn l vi c nh p bn phm xu t hi n khng ng b ngha l xu t hi n cc kho ng th i khng bo tr c ho c c i u khi n b i ph n m m ang c th c thi trong h th ng. l m t ng t.
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Chng 6: Ho t ng ng t (Interrupt). II. PHNG PHP PH C V THI T B :
M t b vi i u khi n c th ph c v m t ho c nhi u thi t b . C hai phng php ph c v thi t b l: phng php ng t (Interrupt) v phng php thm d (Polling). phng php ng t, m i khi c m t thi t b c n c ph c v th thi t b s bo cho b vi i u khi n b ng cch g i n m t tn hi u ng t. Khi nh n c tn hi u ny, b vi i u khi n s ng ng m i cng vi c ang th c hi n chuy n sang ph c v cho thi t b ny. phng php thm d, b vi i u khi n lin t c ki m tra tnh tr ng c a m t thi t b v khi i u ki n c p ng th n s ti n hnh ph c v cho thi t b ny. Sau , b vi i u khi n chuy n sang ki m tra tr ng thi c a thi t b k ti p cho n khi t t c thi t b u c ph c v . i m m nh c a phng php ng t l m t b vi i u khi n c th ph c v c nhi u thi t b , nhng d nhin l khng cng m t th i i m. M i thi t b c th c b vi i u khi n ph c v d a theo m c u tin c gn. phng php thm d, th khng th gn m c u tin cho thi t b c v b vi i u khi n ti n hnh ki m tra cc thi t b theo ki u h i vng m t cch l n l t qua t ng thi t b . Ngoi ra, phng php ng t cho php b vi i u khi n che ho c b qua m t yu c u ph c v c a thi t b , i u m phng php thm d khng th th c hi n. Tuy nhin, l do chnh m phng php ng t c a chu ng hn l v phng php thm d lng ph ng k th i gian c a b vi i u khi n do ph i h i d t ng thi t b , ngay c khi chng khng c n c ph c v . lm r hn v n ny, chng ta c n xem l i cc v d v l p trnh b nh th i c trnh by trong chng 4. Trong c l nh JNB TF1, $ c s d ng ch i cho n khi b nh th i trn (TF=1). cc v d ny, trong khi ch i c TF=1 th b vi i u khi n khng th lm c cng vi c g khc, i u ny d n n vi c lng ph th i gian. Cng v i b nh th i ny, n u ta dng phng php ng t th b vi i u khi n c th th c hi n m t s cng vi c no trong khi ang ch i c TF=1. Khi c TF=1 th b vi i u khi n s b ng t cho d n ang lm vi c g i chng n a, i u ny s khng lm cho b vi i u khi n b lng ph th i gian m t cch v ngha. III. T CH C NG T C A 8051: 1. Cc ngu n ng t:
Lu : Khi ta reset h th ng th t t c cc ng t u b c m ho t ng. Cc ngu n ng t ny c cho php ho c c m ho t ng b ng l nh do ng i l p trnh thi t l p cho t ng ng t. Vi c x l cc ng t c th c hi n qua 2 s : o S u tin ng t c th thay i c v do ng i l p trnh thi t l p. o S chu i vng c nh, khng thay i c. Hai s ny gip CPU gi i quy t cc v n lin quan n ng t nh: hai hay nhi u ng t x y ra ng th i ho c m t ng t x y ra trong khi m t ng t khc ang c th c thi.
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Chng 6: Ho t ng ng t (Interrupt). Cc c ng t c a chip 8051:
Lu : M t ng t x y ra th c ng t tng ng s c set b ng 1. Khi ISR c a ng t c th c thi th c ng t tng ng s t ng b xa v 0 b ng ph n c ng (ngo i tr c ng t RI v TI ph i c xa v 0 b ng ph n m m). i v i ng t ngoi s c hai cch kch ho t t o ra m t tn hi u ng t: ng t ngoi kch ho t khi c m c th p v ng t ngoi kch ho t khi c c nh m t i chn INT0\ ho c INT1\. 2. Qui nh vi c ch n lo i kch ho t cho ng t ngoi: Vi c ch n l a lo i kch ho t cho cc ng t ngoi, thu c lo i kch ho t c nh hay thu c lo i kch ho t m c, th c l p trnh thng qua cc bit IT0 v IT1 c a thanh ghi TCON. IT0 = 0 Ng t ngoi 0 c kch kh i b i vi c pht hi n m c th p t i chn INT0\. IT0 = 1 Ng t ngoi 0 c kch kh i b i vi c pht hi n c nh m t i chn INT0\. IT1 = 0 Ng t ngoi 1 c kch kh i b i vi c pht hi n m c th p t i chn INT1\. IT1 = 1 Ng t ngoi 1 c kch kh i b i vi c pht hi n c nh m t i chn INT1\. Lu : Khi t o tn hi u ng t t i chn INT0\ ho c INT1\ ta c n ph i ch n th i gian duy tr tc ng c a tn hi u ng t. i v i lo i ng t kch ho t c nh m (th i gian t i thi u):
(1) (0) Tm Tm
8051 INTx x = 0, 1
fOSC (MHz): tan so thach anh. Tm ( s): chu ky may.

Tm = 12 f OSC
i v i lo i ng t kch ho t m c th p (th i gian t i a):
8051 INTx (1) (0) (*) (**) x = 0, 1
(*): Duy tr trang thai (0) cho en khi ISR tng ng c thc hien. (*) = 4 Tm (**):Tr ve trang thai (1) trc khi ISR tng ng c thc hien xong hoac trc khi co mot ngat khac c tao ra.
180 Bin so n: Ph m Quang Tr
Gio trnh Vi x l.
Chng 6: Ho t ng ng t (Interrupt). 3. Thanh ghi cho php ng t (IE):
Thanh ghi cho php ng t (IE: Interrupt Enable): ch a cc bit dng cho php ho c c m cc ng t ho t ng. C u trc c a thanh ghi IE:
Hai i u ki n m t ng t c php ho t ng l: Bit EA = 1. Bit ng t tng ng = 1. V d : ng t c a Timer 1 c php ho t ng ta dng l nh: SETB ET1 SETB EA ho c MOV IE, #10001000B M c d c cch trn u cho ta m t k t qu nh nhau sau khi h th ng c thi t l p l i tr ng thi ban u (reset h th ng). Tuy nhin trong khi chng trnh ang ho t ng th nh h ng c a hai cch ny c khc nhau v cch th hai ghi ln thanh ghi IE. Cch th nh t, s d ng hai l nh SETB nn ch nh h ng n 2 bit c n tc ng m khng gy nh h ng n 5 bit cn l i c a thanh ghi IE. Trong khi , cch th hai ch s d ng l nh MOV nn s lm cho 5 bit cn l i ny bit xa m t. T t nh t ta nn kh i ng thanh ghi IE b ng l nh MOV u chng trnh ngay sau khi h th ng c thi t l p l i. Vi c cho php ho c khng cho php cc ng t trong chng trnh nn s d ng cc l nh SETB ho c CLR trnh nh h ng n cc bit khc trong thanh ghi IE. 4. Thanh ghi u tin ng t (IP): Khi ni m u tin ng t gip 8051 gi i quy t v n hai tn hi u ng t xu t hi n ng th i v v n m t tn hi u ng t xu t hi n trong khi m t ng t khc ang c th c thi. Ng t u tin m c cao Ng t u tin m c th p Thanh ghi u tin ng t (IP: Interrupt Priority): ch a cc bit dng thi t l p m c u tin (m c cao hay m c th p) cho t ng ng t ring r . Gio trnh Vi x l. 181 Bin so n: Ph m Quang Tr
Chng 6: Ho t ng ng t (Interrupt). C u trc c a thanh ghi IP:
Khi h th ng c thi t l p l i tr ng thi ban u th t t c cc ng t u s c m c nh m c u tin th p. t ng cc m c u tin cho php m t trnh ph c v ng t c t m d ng b i m t ng t khc n u ng t m i ny c m c u tin cao hn m c u tin c a ng t hi n ang c ph c v . i u ny hon ton h p l i v i 8051 v ta ch c hai m c u tin. N u c ng t c m c u tin cao xu t hi n, trnh ph c v ng t cho ng t c m c u tin th p ph i t m d ng (ngha l b ng t). Ta khng th t m d ng m t chng trnh phuc v ng t c m c u tin cao. Chng trnh chnh do c th c thi m c n n v khng c k t h p v i m t ng t no nn lun lun b ng t b i cc ng t cho d cc ng t c m c u tin th p hay m c u tin cao. N u c hai ng t v i m c u tin ng t khc nhau xu t hi n ng th i, ng t c m c u tin cao s c ph c v tr c. 5. Th t chu i vng ng t (Interrupt Polling Sequence): Khi ni m chu i vng gip 8051 gi i quy t v n hai hay nhi u tn hi u ng t c m c u tin gi ng nhau xu t hi n ng th i. Chu i vng ny s l ( c s p x p theo th t t th p n cao): Ng t ngoi 0 Ng t Timer 0 Ng t ngoi 1 Ng t Timer 1 Ng t port n i ti p Ng t Timer 2 (ch c 8052)
Hnh d i y minh h a 5 nguyn nhn ng t, c ch cho php ring r v ton c c, chu i vng v cc m c u tin. Tr ng thi c a t t c cc nguyn nhn ng t c th hi n thng qua cc bit c tng ng trong cc thanh ghi ch c nng c bi t c lin quan. D nhin n u m t ng t no khng c php, nguyn nhn ng t tng ng khng th t o ra m t ng t nhng ph n m m v n c th ki m tra c ng t . L y th d b nh th i v port n i ti p trong hai chng tr c s d ng cc c ng t m t cch r ng ri d khng c ng t tng ng x y ra, ngha l khng s d ng cc ng t. Ng t do port n i ti p l k t qu OR c a c ng t khi thu RI (c ng t thu) v c ng t khi pht TI (c ng t pht).
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Chng 6: Ho t ng ng t (Interrupt). C u trc ng t c a 8051:
IV. X
L NG T V CC VECT NG T:
1. Qui trnh x l ng t: Cc thao tc s x y ra khi c m t ng t xu t hi n v n c CPU ch p nh n: Hon t t th c thi l nh t i th i i m v d ng chng trnh chnh. Gi tr c a thanh ghi PC c c t vo stack. Tr ng thi c a ng t t i th i i m c lu gi l i. Cc ng t c gi l i m c ng t. a ch c a ISR c a ng t tng ng c n p vo thanh ghi PC. ISR c a ng t tng ng c th c thi. (ISR th c thi xong khi g p l nh RETI). Gi tr trong stack (c a PC c) c ph c h i l i vo thanh ghi PC. Tr ng thi cc ng t c ph c h i l i. Chng trnh chnh ti p t c c th c thi t i ch b t m d ng.
ISR c th c thi p ng cng vi c c a ng t. Vi c th c thi ISR k t thc khi g p l nh RET (tr v t m t trnh ph c v ng t). L nh ny l y l i gi tr c c a b m chng trnh PC t stack v ph c h i tr ng thi c a ng t c. Vi c th c thi chng trnh chnh c ti p t c ni b t m ngng. Gio trnh Vi x l. 183 Bin so n: Ph m Quang Tr
Chng 6: Ho t ng ng t (Interrupt). 2. Cc vect ng t:
Khi m t ng t c ch p nh n, gi tr c n p cho b m chng trnh PC c g i l vect ng t. Vect ng t l a ch b t u c a chng trnh ph c v ng t (ISR) c a ng t tng ng. Vect reset h th ng cng c xem nh l m t ng t: chng trnh chnh b ng t v b m chng trnh PC c n p gi tr m i. Khi m t trnh ph c v ng t c tr n, c gy ra ng t s t ng b xa v 0 b i ph n c ng. Cc ngo i l bao g m cc c RI v TI i v i cc ng t do port n i ti p, cc nguyn nhn ng t thu c lo i ny do c hai kh nng t o ra ng t nn trong th c t CPU khng xa c ng t. B ng qui nh a ch b t u c a cc ISR (b ng vect ng t):
V. THI T K CC CHNG TRNH S 1. T ng quan:
D NG NG T:
Khi thi t k cc chng trnh khng s d ng ng t th ta s g p ph i nh ng tr ng h p CPU hon ton tiu ph th i gian vo vi c ch i cc tc nhn c n thi t x y ra (V d : s trn c a c TF0, TF1; vi c thu xong m t d li u v c RI=1; vi c pht xong m t k t v c TI=1; v.v) sau m i ti p t c th c hi n cng vi c. i u ny khng thch h p cho cc ng d ng i u khi n i h i ph i tc ng qua l i v i nhi u thi t b cng lc. gi i quy t v n trn ta c n thi t k cc chng trnh c s d ng n ng t. V n gip cho CPU khng t n th i gian ch i tc nhn m ch khi no tc nhn x y n th CPU m i th c hi n vi c x l tc nhn , kho ng th i gian tc nhn khng x y ra th CPU s lm vi c khc.
Gio trnh Vi x l.
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Chng 6: Ho t ng ng t (Interrupt). T ch c b nh khi s d ng ng t:
Khung m u cho m t chng trnh c s d ng ng t: ORG 0000H ;i m nh p c a reset h th ng. LJMP MAIN ;L nh nh y v t qua cc ISR. ;i m nh p c a cc ISR. ORG 0030H ;i m nh p c a chng trnh chnh. MAIN: ;Chng trnh chnh b t u. END 2. Thi t k cc chng trnh ISR kch th c nh : i u ki n: Khi ISR c kch th c khng qu 8 byte (k c l nh RETI). ISR ph i c vi t trong ph m vi i m nh p tng ng c a n trong b nh chng trnh (xem ph n t ch c b nh khi s d ng ng t). Lu : N u ch c m t nguyn nhn ng t c s d ng th ISR c a n c th c vi t trn sang i m nh p c a cc ISR khc (ngha l ISR c kch th c l n hn 8 byte, nhng ph i nh hn 46 byte). V khi vng nh c a cc ISR khc khng c dng n nn ta c th t n d ng s d ng cho ISR ny. N u c nhi u nguyn nhn ng t c s d ng th ta ph i c n th n m b o cho cc ISR c b t u ng v tr m khng trn sang ISR k (ngha l ISR c kch th c khng qu 8 byte).
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Khung m u chng trnh: (V d : dng ng t Timer0 v ng t ngoi 1) ORG 0000H ;i m nh p c a reset h th ng. LJMP MAIN ;L nh nh y v t qua cc ISR. ORG 000BH ;i m nh p cho ISR c a Timer 0. ;ISR c a Timer 0. RETI ;K t thc ISR c a Timer 0. ORG 0013H ;i m nh p cho ISR c a ng t ngoi 1. ;ISR c a ng t ngoi 1. RETI ;K t thc ISR c a ng t ngoi 1. ORG 0030H ;i m nh p c a chng trnh chnh. MAIN: ;Chng trnh chnh b t u. END 3. Thi t k cc chng trnh ISR kch th c l n: i u ki n: Khi ISR c kch th c v t qu 8 byte. ISR khng th vi t vo i m nh p tng ng c a n trong b nh chng trnh (v kch th c i m nh p ch c 8 byte) ta ph i chuy n ISR ny n m t ni khc trong b nh chng trnh ho c c th vi t l n qua i m nh p c a ISR k ti p (n u ISR khng s d ng). Khung m u chng trnh: (V d : dng ng t Timer0 v ng t ngoi 1) ORG 0000H ;i m nh p c a reset h th ng. LJMP MAIN ;L nh nh y v t qua cc ISR. ORG 000BH ;i m nh p cho ISR c a Timer 0. LJMP T0ISR ;L nh nh y n ISR c a Timer 0. ORG 0013H ;i m nh p cho ISR c a ng t ngoi 1. LJMP EX1ISR ;L nh nh y n ISR c a ng t ngoi 1. ORG 0030H ;i m nh p c a chng trnh chnh. MAIN: ;Chng trnh chnh b t u. SJMP $ ;L nh cch ly chng trnh. T0ISR: ;ISR c a ng t Timer 0. RETI ;K t thc ISR c a Timer 0. EX1ISR: ;ISR c a ng t ngoi 1. RETI ;K t thc ISR c a ng t ngoi 1. END
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Nh n xt t ng qut: o n gi n, cc chng trnh c a chng ta ch lm vi c th i i m b t u. Chng trnh chnh kh i ng port n i ti p, b nh th i v cc thanh ghi ng t sao cho thch h p v i yu c u t ra v r i khng lm g c . Cng vi c hon ton c th c hi n bn trong cc ISR. Sau cc l nh kh i ng, chng trnh chnh ch a v th c hi n l nh sau y (l nh nh y t i ch khng lm g c ): SJMP $ o Khi c m t tn hi u ng t xu t hi n, chng trnh chnh t m th i b d ng l i trong khi ISR c th c thi. L nh RETI cu i c a cc ISR s tr i u khi n v cho chng trnh chnh v chng trnh chnh ti p t c khng lm g c (l nh nh y t i ch ). i u ny khng c g l khng t nhin i v i chng ta. Trong nhi u ng d ng h ng i u khi n, ph n l n cng vi c c th c hi n trong trnh ph c v ng t. Cc v d minh h a d i y s cho ta th y i u ny. VI. CC V D MINH H A: 1. V d minh h a x l ng t Timer: V d 1: Vi t chng trnh s d ng Timer 0 v cc ng t t o ra m t sng vung c t n s 10 KHz trn chn P1.0, fOsc = 12MHz.
Gi i ORG LJMP ORG T0ISR: CPL RETI ORG MAIN: MOV MOV SETB MOV SJMP END TMOD, #02H TH0, #(-50) TR0 IE, #82H $ P1.0 0030H 0000H MAIN 000BH ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR c a Timer 0. ;ISR c a Timer 0. ;L y b. ;K t thc ISR c a Timer 0. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;Ch n ch 2 cho Timer 0. ; nh th i 50 s. ;Cho Timer 0 ho t ng. ;Cho php ng t Timer 0 . ;Khng lm g (nh y t i ch ). ;K t thc chng trnh.
Lu : L nh SJMP$ c th c thay th b ng m t o n l nh th c thi nh ng cng vi c khc. Vi c thay th ny khng nh h ng g n vi c t o sng vung f=10KHz t i chn P1.0. V c sau m i 50 s th nh ng cng vi c s b t m d ng (ng t Timer 0 xu t hi n) CPU th c hi n vi c t o sng vung r i quay v th c hi n ti p nh ng cng vi c . Ngay sau khi reset h th ng, b m chng trnh PC c n p 0000H. L nh u tin c th c thi l LJMP MAIN, l nh ny r nhnh n chng trnh chnh a ch 0030H trong b nh chng trnh. Ba l nh u tin c a chng trnh chnh s kh i ng Timer 0 ch 8 bit t ng n p l i (Mode 2), sao cho Timer 0 s trn sau m i 50 s. L nh MOV IE, #82H cho php cc ng t do Timer0 t o ra. M i m t l n trn, Timer s t o ra m t ng t. D nhin l l n trn u tin s khng xu t hi n sau Gio trnh Vi x l. 187 Bin so n: Ph m Quang Tr
50 s do chng trnh chnh ang trong vng l p khng lm g. Khi ng t xu t hi n sau m i 50 s, chng trnh chnh b ng t v ISR cho Timer0 c th c thi. v d trn ISR ny ch n gi n l y b bit c a port v quay tr v chng trnh chnh ni vng l p khng lm g c th c thi ch m t ng t m i sau m i 50 s. Lu l c trn TF0 khng c n c xa b i ph n m m do khi cc ng t c cho php th c ny t ng c xa b i ph n c ng khi CPU tr n trnh ph c v ng t. V d 2: Vi t chng trnh s d ng cc ng t t o ng th i cc d ng sng vung c t n s 7 KHz v 500 Hz t i cc chn P1.7 v P1.6 (khng quan tm n l ch pha c a hai sng ny), fOsc = 12MHz.
Gi i ORG LJMP ORG LJMP ORG LJMP ORG MAIN: MOV MOV SETB SETB MOV SJMP T0ISR: CPL RETI T1ISR: CLR MOV MOV SETB CPL RETI END ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR c a Timer 0. ;L nh nh y n ISR Timer 0. ;i m nh p ISR c a Timer 1. ;L nh nh y n ISR Timer 1. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. TMOD, #12H ;Ch n ch 2 cho Timer 0. ;Ch n ch 1 cho Timer 1. TH0, #-71 ; nh th i 71 s. TR0 ;Cho Timer 0 ho t ng. TF1 ;Bu c Timer 1 ng t. IE, #8AH ;Cho php cc ng t ho t ng. $ ;Khng lm g (nh y t i ch ). ;ISR c a ng t Timer 0. P1.7 ;L y b. ;K t thc ISR c a Timer 0. ;ISR c a ng t Timer 1. TR1 ;D ng Timer 1. TH1, #HIGH(-1000) ; nh th i 1ms. TL1, #LOW(-1000) TR1 ;Cho Timer 1 ho t ng. P1.6 ;L y b. ;K t thc ISR c a Timer 1. ;K t thc chng trnh. 188 Bin so n: Ph m Quang Tr 0000H MAIN 000BH T0ISR 001BH T1ISR 0030H
Gio trnh Vi x l.
Lu : L nh SJMP$ c th c thay th b ng m t o n l nh th c thi nh ng cng vi c khc. Vi c thay th ny khng nh h ng g n vi c t o sng vung f = 7KHz v f = 500Hz t i chn P1.7 v chn P1.6. V c sau m i 71 s v 1ms th nh ng cng vi c s b t m d ng (ng t Timer 0 v ng t Timer 1 xu t hi n) CPU th c hi n vi c t o sng vung r i quay v th c hi n ti p nh ng cng vi c . Vi c t h p cc ng ra ny r t kh t o ra c trn m t h th ng khng s d ng i u khi n ng t. Timer 0 ho t ng ch 2, c s d ng t o ra d ng sng 7 KHz trn chn P1.7. Timer 1 ho t ng ch 1, c s d ng t o ra d ng sng 500 Hz trn chn P1.6. S d trong tr ng h p ny, Timer 1 ph i c thi t l p ho t ng ch 1 l do d ng sng 500Hz yu c u th i gian m c cao v th i gian m c th p l 1ms, ch 2 khng s d ng c trong tr ng h p ny. Cng c n ch l cc thanh ghi TH1/TL1 khng c kh i ng u chng trnh chnh nh tr ng h p c a thanh ghi TH0. Do TH1/TL1 ph i c n p l i sau m i l n b nh th i trn, TF1 c set b ng 1 trong chng trnh chnh b i ph n m m (l nh SETB TF1) c s d ng bu c ph i c m t ng t ban u ngay tr c khi cc ng t c cho php. i u ny c hi u qu cho vi c b t u d ng sng 500Hz. V d 3: Vi t chng trnh lin t c nh n d li u 8 bit c ng P0 v sau g i d li u ny n c ng P1. Trong th i gian ny c n t o ra trn chn P2.1 m t sng vung c chu k l 200 s. S d ng Timer 0 t o sng vung, fOsc = 11,0592MHz.
Gi i ORG LJMP ORG CPL RETI ORG MAIN: MOV MOV MOV MOV SETB BACK: MOV MOV SJMP END 0000H MAIN 000BH P2.1 0030H TMOD, #02H P0, #0FFH TH0, #(-92) IE, #82H TR0 A, P0 P1, A BACK ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR c a Timer 0. ; o tr ng thi chn P2.1, t o xung. ;K t thc ISR c a Timer 0. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;Ch n ch 2 cho Timer 0. ;C u hnh Port 0 l c ng vo. ; nh th i 100 s (n a chu k). ;Cho php ng t Timer 0 ho t ng. ;Cho Timer 0 ho t ng. ;Nh n d li u t P0. ;Xu t d li u v a nh n c ra P1. ;K t thc chng trnh. 189 Bin so n: Ph m Quang Tr
Gio trnh Vi x l.
V d 4: Vi t chng trnh lin t c nh n d li u 8 bit c ng P0 v sau g i d li u ny n c ng P1. Trong th i gian ny c n t o ra trn chn P2.1 m t sng vung v i yu c u: th i gian sng m c cao l 1085 s v th i gian sng m c th p l 15 s. S d ng Timer 1 t o sng vung, fOsc=11,0592MHz.
T tH tL
1085 s 8051 11,0592MHz P2.1 T = 200 s P0.0

DATA 8 BIT
15 s
P1.0
DATA 8 BIT
P0.7
P1.7
Gi i ORG LJMP ORG LJMP ORG MAIN: MOV MOV MOV MOV MOV SETB BACK: MOV MOV SJMP T1ISR: CLR CLR MOV DJNZ MOV MOV SETB SETB RETI END 0000H MAIN 001BH T1ISR 0030H TMOD, #10H P0, #0FFH TL1, #18H TH1, #0FCH IE, #88H TR1 A, P0 P1, A BACK TR1 P2.1 R2, #4 R2, $ TL1, #18H TH1, #0FCH TR1 P2.1 ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR c a Timer 1. ;L nh nh y n ISR Timer 1. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;Ch n ch 1 cho Timer 1. ;C u hnh Port 0 l c ng vo. ; nh th i 1085 s (cho n a chu k u). ; ;Cho php ng t Timer 1 ho t ng. ;Cho Timer 1 ho t ng. ;Nh n d li u t P0. ;Xu t d li u v a nh n c ra P1. ;L p l i lin t c hai thao tc trn. ;ISR c a ng t Timer 1. ;D ng Timer 1. ; o tr ng thi chn P2.1, t o xung. ; nh th i 8TMachine (t ng th i gian: 15 s), ;t o th i gian tr (cho n a chu k sau). ; nh th i 1085 s (cho n a chu k u). ; ;Cho Timer 1 ho t ng. ; o tr ng thi chn P2.1, t o xung. ;K t thc ISR c a Timer 1. ;K t thc chng trnh. 190 Bin so n: Ph m Quang Tr
Gio trnh Vi x l.
Chng 6: Ho t ng ng t (Interrupt). 2. V d minh h a x l ng t port n i ti p:
Cc ng t do port n i ti p xu t hi n khi c ng t pht TI ho c c ng t thu RI c set b ng 1. M t ng t pht xu t hi n khi vi c pht m t k t ghi vo SBUF hon t t. M t ng t thu xu t hi n khi m t k t c thu nh n y v ang trong SBUF ch c c. Nh v y, ng t pht x y ra khi b m pht SBUF r ng, ng t thu x y ra khi b m thu SBUF y. Cc ng t do port n i ti p c khc v i cc ng t do b nh th i. C gy ra ng t port n i ti p khng c xa b i ph n c ng khi CPU tr t i trnh ph c v ng t. L do l v y ta c hai ngyn nhn t o ra ng t port n i ti p, c th l hai ng t t o ra b i hai c TI v RI. Nguyn nhn ng t ph i c xc nh trong trnh ph c v ng t v c t o ra ng t c xa b i ph n m m. C n nh c l i l v i cc ng t do b nh th i, c t o ra ng t c xa b i ph n c ng khi CPU tr t i trnh ph c v ng t. V d 1: Vi t chng trnh s d ng cc ng t lin t c pht i m ASCII (c gi tr t 20H n 7EH) n m t thi t b u cu i n i v i 8051 qua port n i ti p. Bi t r ng fOsc=11,0592MHz. Gi i ORG LJMP ORG LJMP ORG MAIN: MOV MOV MOV SETB MOV MOV SJMP SPISR: CJNE MOV SKIP: MOV INC CLR RETI END SBUF, A A TI ;Truy n k t ra port n i ti p. ;L y m c a k t k ti p. ;Xa c ng t pht. ;K t thc ISR c a port n i ti p. ;K t thc chng trnh. A, #7FH, SKIP A, #20H SCON, #42H TMOD, #20H TH1, #(-24) TR1 A, #20H IE, #90H $ 0000H MAIN 0023H SPISR 0030H ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR port n i ti p. ;L nh nh y n ISR port n i ti p. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;Ch n ch 1 cho port n i ;ti p, TI=1 bu c c ng t ;v g i k t u tin. ;Ch n ch 2 cho Timer 1. ;T c baud = 1200. ;Cho Timer 1 ho t ng. ;N p m cho k t u tin. ;Cho php ng t port n i ti p. ;Khng lm g (nh y t i ch ). ;ISR c a ng t port n i ti p. ;Ki m tra k t thc b ng m. ;Tr l i k t u tin.
Lu : L nh SJMP$ c th c thay th b ng m t o n l nh th c thi nh ng cng vi c khc. Vi c thay th ny khng nh h ng g n vi c pht m ASCII thng qua port n i ti p. V c sau m i l n port n i ti p truy n xong m t k t th nh ng cng vi c s b t m d ng (ng t port n i ti p xu t hi n) CPU th c hi n vi c ki m tra k t k t thc b ng m v l y m c a k t k ti p ti p t c pht i r i quay v th c hi n ti p nh ng cng vi c . B ng m ASCII bao g m 128 m 7 bit (xem thm trong ph n ph l c Ph l c 4 B ng m ASCII). Sau khi nh y n nhn MAIN a ch 0030H, ba l nh u tin dng kh i ng Timer 1 cung c p xung clock 1200 baud cho port n i ti p, l nh MOV SCON,#42H kh i ng port n i ti p Gio trnh Vi x l. 191 Bin so n: Ph m Quang Tr
ch 1 (UART 8 bit c t c baud thay i) v cho TI=1 bu c t o ra m t ng t tr c khi cc ng t c cho php ho t ng. Sau m ASCII u tin (20H) c n p cho thanh ghi A v cc ng t do port n i ti p c cho php. Cu i cng ph n chnh c a chng trnh i vo vng l p khng lm g (t c l l nh SJMP $). Trnh ph c v ng t c a port n i ti p lm t t c cng vi c m t khi chng trnh chnh thi t l p cc i u ki n ban u. Hai l nh u tin ki m tra thanh ghi A v n u m ASCII t n 7FH (ngha l m v a m i c pht i l 7EH) th thanh ghi A s c thi t l p l i v i n i dung l 20H. Sau m ASCII c g i n b m c a port n i ti p (l nh MOV SBUF,A) c pht i. Th c hi n vi c tng gi tr trong thanh ghi A c m k ti p, c pht c xa (l nh CLR TI) v trnh ph c v ng t k t thc (l nh RETI). i u khi n s tr v chng trnh chnh v l nh SJMP $ c th c thi cho n khi TI l i c set b ng 1 cho l n pht d li u k ti p. N u ta so snh t c c a CPU v i t c truy n d li u, ta nh n th y r ng l nh SJMP $ c th c thi v i ph n trm t l th i gian r t l n trong chng trnh ny. Ph n trm t l ny l bao nhiu? t c 1200 baud, m i m t bit c truy n i trong m t kho ng th i gian l 0,8333ms. Nh v y 8 bit d li u c ng v i 1 bit start, 1 bit stop (m t l n truy n m t d li u g m 10 bit) chi m 8,333ms. Th i gian th c thi t nh t c a trnh ph c v ng t SPISR l t ng c a s chu k cho m i l nh nhn v i 1,085 s (t c 1TMachine), th i gian ny tnh c l 8 x 1,085 s = 8,68 s. Do v y, v i 8333 s dng truy n m t d li u m ch c 8,68 s dnh cho trnh ph c vu ng t SPISR. L nh SJMP $ th c thi trong kho ng th i gian 8333 s - 8,68 s = 8324,32 s t c l kho ng 99,9% th i gian. Do v y ng t c n c s d ng c th lo i b c kho ng th i gian khng lm g ny (chi m n 99,9% th i gian ho t ng c a chng trnh truy n d li u ny. Mu n v y th l nh SJMP $ c th c thay b i cc l nh khc th c hi n nh ng cng vi c khc theo yu c u c a ng d ng. Cc ng t v n xu t hi n v cc k t v n c pht t port n i ti p sau m i 8,333ms. V d 2: Vi t chng trnh i u khi n 8051 c d li u t c ng P1 v ghi lin t c t i c ng P2. ng th i a m t b n sao d li u t i port n i ti p th c hi n vi c truy n d li u n i ti p. Bi t r ng t c truy n l 9600 baud v fOsc = 11,0592MHz Gi i ORG LJMP ORG LJMP ORG MAIN: MOV MOV MOV MOV MOV SETB BACK: MOV MOV SJMP SPISR: CLR MOV 0000H MAIN 0023H SPISR 0030H P1, #0FFH SCON, #42H TMOD, #20H TH1, #(-3) IE, #90H TR1 A, P1 P2, A BACK TI SBUF, A ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR port n i ti p. ;L nh nh y n ISR port n i ti p. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;C u hnh Port 1 l c ng vo. ;Ch n ch 1 cho port n i ti p, c m thu. ;Ch n ch 2 cho Timer 1. ;T c baud = 9600. ;Cho php ng t port n i ti p. ;Cho Timer 1 ho t ng. ; c d li u t P1. ;Xu t d li u nh n c ra P2. ;L p l i cc thao tc trn. ;ISR c a ng t port n i ti p. ;Xa c ng t pht TI. ;Xu t d li u nh n c ra port n i ti p. 192 Bin so n: Ph m Quang Tr
Gio trnh Vi x l.
Chng 6: Ho t ng ng t (Interrupt). RETI END
Tr ng H Cng nghi p Tp.HCM. ;K t thc ISR c a port n i ti p. ;K t thc chng trnh.
V d 3: Vi t chng trnh i u khi n 8051 c d li u t c ng P1 v ghi lin t c t i c ng P2. Trong khi d li u nh n c t port n i ti p th c g i n c ng P0. Bi t r ng t c truy n l 9600 baud v fOsc = 11,0592MHz Gi i ORG LJMP ORG LJMP ORG MAIN: MOV MOV MOV MOV MOV SETB BACK: MOV MOV SJMP SPISR: CLR MOV MOV RETI END 0000H MAIN 0023H SPISR 0030H P1, #0FFH SCON, #52H TMOD, #20H TH1, #(-3) IE, #90H TR1 A, P1 P2, A BACK RI A, SBUF P0, A ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR port n i ti p. ;L nh nh y n ISR port n i ti p. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;C u hnh Port 1 l c ng vo. ;Ch n ch 1 cho port n i ti p. ;Ch n ch 2 cho Timer 1. ;T c baud = 9600. ;Cho php ng t port n i ti p. ;Cho Timer 1 ho t ng. ; c d li u t P1. ;Xu t d li u nh n c ra P2. ;L p l i cc thao tc trn. ;ISR c a ng t port n i ti p. ;Xa c ng t thu RI. ;Nh n d li u t port n i ti p. ;Xu t d li u nh n c ra P0. ;K t thc ISR c a port n i ti p. ;K t thc chng trnh.
V d 4: Vi t chng trnh c s d ng cc ng t th c hi n cc c ng vi c sau: Nh n d li u t port n i ti p, sau th g i d li u ny n c ng P0. Nh n d li u t c ng P1, sau th g i d li u ny n port n i ti p v c ng P2. S d ng Timer 0 t o sng vung c t n s 5KHz t i P0.1. Gi i ORG LJMP ORG CPL RETI ORG LJMP ORG MAIN: MOV 0000H MAIN 000BH P0.1 0023H SPISR 0030H P1, #0FFH ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR Timer 0. ;L y b chn P1.0, t o xung. ;K t thc ISR c a port n i ti p. ;i m nh p ISR port n i ti p. ;L nh nh y n ISR port n i ti p. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;C u hnh Port 1 l c ng vo. 193 Bin so n: Ph m Quang Tr
Bi t r ng t c truy n l 4800 baud v fOsc = 11,0592MHz
Gio trnh Vi x l.
Chng 6: Ho t ng ng t (Interrupt). MOV MOV MOV MOV MOV SETB SETB BACK: MOV MOV SJMP SPISR: JB CLR MOV MOV RETI TRANS: CLR MOV RETI END SCON, #52H TMOD, #22H TH1, #(-6) TH0, #(-92) IE, #92H TR1 TR0 A, P1 P2, A BACK TI, TRANS RI A, SBUF P0, A TI SBUF, A
Tr ng H Cng nghi p Tp.HCM. ;Ch n ch 1 cho port n i ti p. ;Ch n ch 2 cho Timer 0, Timer 1. ;T c baud = 4800. ; nh th i 100 s (n a chu k), f = 5KHz. ;Cho php ng t port n i ti p v Timer 0. ;Cho Timer 1 ho t ng. ;Cho Timer 0 ho t ng. ; c d li u t P1. ;Xu t d li u nh n c ra P2. ;L p l i cc thao tc trn. ;Ki m tra thu xong (RI) hay pht ;xong (TI), n u thu xong (RI = 1) th: ;Xa c ng t thu RI. ;Nh n d li u t port n i ti p. ;Xu t d li u nh n c ra P0. ;K t thc ISR c a port n i ti p. ;N u pht xong (TI = 1) th: ;Xa c ng t pht TI. ;Xu t d li u nh n c ra port n i ti p. ;K t thc ISR c a port n i ti p. ;K t thc chng trnh.
3. V d minh h a x l ng t ngoi: Ng t ngoi x y ra khi c m c th p ho c c c nh m tc ng ln chn INT0\ ho c chn INT1\ c a 8051. Khi m t ng t ngoi c t o ra, c t o ra ng t (IE0 v IE1) c xa b i ph n c ng khi CPU tr n trnh ph c v ng t n u ng t thu c lo i tc ng c nh m, cn n u ng t thu c lo i tc ng m c th p th nguyn nhn ng t ngoi s i u khi n m c c a c thay v l ph n c ng trn chip. V d 1: Vi t chng trnh s d ng cc ng t thi t k b i u khi n l nung sao cho nhi t trong l duy tr m c 120OC 5OC. Gi i Gi s ta dng m ch giao ti p nh hnh bn d i. Cu n dy i u khi n t t/m l c n i v i P1.7 sao cho: P1.7 = 1 th m l v P1.7 = 0 th t t l B c m bi n nhi t c n i v i INT0\ v INT1\, cung c p cc tn hi u HOT\ v COLD\ nh sau: HOT\ = 0 n u T > 125OC v COLD\ = 0 n u T < 115OC Chng trnh s cho l ho t ng (m l) khi T < 115OC v cho l ngng ho t ng (t t l) khi T > 125OC.
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ORG LJMP ORG EX0ISR: CLR RETI ORG EX1ISR: SETB RETI ORG MAIN: MOV SETB SETB SETB JB CLR SKIP: SJMP END
0000H MAIN 0003H P1.7 0013H P1.7 0030H IE, #85H IT0 IT1 P1.7 P3.2, SKIP P1.7 $
;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR ng t ngoi 0. ;T t l. ;K t thc ISR c a ng t ngoi 0. ;i m nh p ISR ng t ngoi 1. ;M l. ;K t thc ISR c a ng t ngoi 1. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;Cho php ng t ngoi 0 v 1. ;Ng t ngoi kch kh i c nh m.
i u khi n t t/m l ty
;M l. thu c tr ng thi nhi t hi n t i c a l. ;N u t > 125OC. ;T t l. ;Khng lm g (nh y t i ch ). ;K t thc chng trnh.
Lu : L nh SJMP$ c th c thay th b ng m t o n l nh th c thi nh ng cng vi c khc. Vi c thay th ny khng nh h ng g n vi c i u khi n ho t ng t t m l theo nhi t . V c sau m i l n c tn hi u tc ng t c m bi n th nh ng cng vi c s b t m d ng (ng t ngoi 0 v 1 xu t hi n) CPU th c hi n vi c i u khi n t t m l theo nhi t qui nh r i quay v th c hi n ti p nh ng cng vi c . Ba l nh u tin trong chng trnh chnh cho php cc ng t ngoi v xc nh cc ng t ngoi thu c lo i tc ng c nh m. Do tr ng thi hi n t i c a cc ng vo HOT\ v COLD\ cha bi t c nn ba l nh ti p theo s i u khi n l t t/m ty thu c vo tr ng thi nhi t hi n t i c a l. Tr c tin, l c m (l nh SETB P1.7) v ng vo HOT c l y m u (l nh JB P3.2, SKIP). N u ng vo HOT m c cao, ngha l T < 125OC, th l nh k c b qua v l v n ti p t c c m . Ng c l i, n u ng vo HOT m c th p, ngha l T > 125OC, th l nh k ti p CLR P1.7 c th c thi t t l tr khi i vo vng l p khng lm g.
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V d 2: Vi t chng trnh s d ng cc ng t thi t k m t h th ng bo ng t o m thanh 400 Hz trong vng 1 giy (s d ng m t loa c n i v i chn P1.7) m i khi b c m bi n t c a (n i v i chn INT0\) t o ra m t s chuy n tr ng thi t m c cao xu ng m c th p.
Cam bien 8051 INT0 Ca ong Ca m
LOA
1s
Cam bien = 0 Cam bien =
P1.7 440 Hz 2,5 ms
P1.7
7404
Ca ra vao
Gi i ORG LJMP ORG LJMP 000BH LJMP ORG LJMP ORG 0000H MAIN 0003H EX0ISR T0ISR 001BH T1ISR 0030H IT0 TMOD, #11H IE, #81H $ R7, #20 TF0 TF1 ET0 ET1 TR0 R7, SKIP ET0 ET1 EXIT ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR ng t ngoi 0. ;L nh nh y n ISR ng t ngoi 0 ;i m nh p ISR c a Timer 0. ;L nh nh y n ISR Timer 0. ;i m nh p ISR c a Timer 1. ;L nh nh y n ISR Timer 1. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;Ng t ngoi kch kh i c nh m. ;Ch n ch 1 cho Timer 0, 1. ;Cho php ng t ngoi 0. ;Khng lm g (nh y t i ch ). ;ISR c a ng t ngoi 0. ;20 l n x 50000 s = 1s. ;Bu c Timer 0 ng t. ;Bu c Timer 1 ng t. ;Cho php ng t Timer 0. ;Cho php ng t Timer 1. ;K t thc ISR c a ng t ngoi 0. ;ISR c a ng t Timer 0. ;D ng Timer 0. ;Ki m tra 20 l n (1 giy). ;K t thc pht m n u .
ORG
MAIN: SETB MOV MOV SJMP EX0ISR: MOV SETB SETB SETB SETB RETI T0ISR: CLR DJNZ CLR CLR LJMP SKIP: MOV MOV SETB EXIT: RETI
TH0, #HIGH(-50000) ; nh th i 0,05 s. TL0, #LOW(-50000) TR0 ;Cho Timer 0 ho t ng. ;K t thc ISR c a ng t Timer 0. 196 Bin so n: Ph m Quang Tr
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Chng 6: Ho t ng ng t (Interrupt). T1ISR: CLR MOV MOV SETB RETI END
;ISR c a ng t Timer 1. TR1 ;D ng Timer 1. TH1, #HIGH(-1250) ; nh th i 1,25 ms. TL1, #LOW(-1250) TR0 ;Cho Timer 1 ho t ng. ;K t thc ISR c a ng t Timer 1. ;K t thc chng trnh.
Lu : L nh SJMP$ c th c thay th b ng m t o n l nh th c thi nh ng cng vi c khc. Vi c thay th ny khng nh h ng g n vi c i u khi n ho t ng c a loa pht ra m thanh theo tn hi u t b c m bi n c a m . V c sau m i l n c tn hi u tc ng t c m bi n th nh ng cng vi c s b t m d ng (ng t ngoi 0 xu t hi n) CPU th c hi n vi c i u khi n pht ra m thanh t i loa trong m t kho ng th i gian xc nh r i quay v th c hi n ti p nh ng cng vi c . Gi i php cho v d ny l s d ng ba ng t: ng t ngoi 0 (b c m bi n c a), ng t Timer 0 (m hi u 400Hz) v ng t Timer 1 ( nh th i 1s). Chng trnh g m nm ph n phn bi t: v tr cc vect ng t, chng trnh chnh v ba trnh ph c v ng t. Cc v tr vect ng t ch a cc l nh LJMP chuy n i u khi n n cc trnh ph c v ng t tng ng. Chng trnh chnh b t u a ch 0030H ch ch a b n l nh. L nh SETB IT0 cho php ng vo ng t ghp v i b c m bi n c a c kch kh i c nh m. L nh MOV TMOD,#11H xc nh ch ho t ng c a c hai b nh th i l ch nh th i 16 bit. Ch c ng t ngoi 0 c php b t u (l nh MOV IE,#81H) do i u ki n c a m l i u ki n c n ph i c tr c khi m t ng t no c ch p thu n. Cu i cng l nh SJMP $ t chng trnh vo vng l p khng lm g. Khi i u ki n c a m c pht hi n (b ng s chuy n tr ng ti t m c cao xu ng m c th p chn INT0\), ng t ngoi 0 c t o ra. Trnh ph c v cho ng t ngoi 0, EX0ISR, b t u b ng vi c n p h ng s 20 cho R7, r i set c trn c a c hai b nh th i b ng 1 bu c cc ng t do b nh th i xu t hi n. Tuy nhin cc ng t do b nh th i s ch xu t hi n khi cc bit tng ng trong thanh ghi IE c cho php. Hai l nh k ti p SETB ET0 v SETB ET1 cho php cc ng t do b nh th i. Cu i cng trnh ph c v cho ng t ngoi 0, EX0ISR, k t thc b ng l nh RETI tr v chng trnh chnh. B nh th i 0 dng t o ra kho ng th i gian nh th i 1s v b nh th i 1 dng t o ra m hi u 400Hz. Sau khi trnh ph c v cho ng t ngoi 0, EX0ISR, k t thc th cc ng t do b nh th i l p t c c t o ra (v c ch p nh n sau khi th c thi m t l nh SJMP $). D a vo th t trong chu i vng nn ng t do b nh th i 0 s c ph c v tr c tin. Kho ng th i gian nh th i 1s c t o ra b ng cch l p trnh l p l i 20 l n th i gian nh th i 50000 s (20 x 50000 s = 1s). Thanh ghi R7 ho t ng nh l m t b m. Trnh ph c v ng t T0ISR ho t ng nh sau: tr c tin b nh th i 0 c i u khi n ng ng ho t ng v R7 c gim i m t n v . K n TH0/TL0 c n p l i b i gi tr (-50000), sau b nh th i 0 c i u khi n ho t ng tr l i v trnh ph c v ng t c k t thc. l n ng t th 20, R7 c gim xu ng 0 (1s tri qua). Cc ng t do c hai b nh th i c v hi u (l nh CLR ET0 v CLR ET1) v trnh ph c v ng t k t thc. Khng cn ng t do b nh th i t o ra n a cho n khi i u ki n c a m xu t hi n m t l n n a. m hi u 400Hz c l p trnh b ng cch s d ng ng t do b nh th i 1. T n s 400Hz yu c u chu k l 2500 s, trong c 1250 s m c cao v 1250 s m c th p. Trnh ph c v ng t cho b nh th i 1 ch n gi n n p gi tr (-1250) cho TH1/TL1, sau l y b bit c a port kch loa v r i k t thc trnh ph c v ng t.
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V d 3: Ng t ngoi kch kh i m c th p - Cho m ch i n nh hnh v . Chn INT0\ c n i v i m t cng t c bnh th ng m c cao, m i khi chn ny c m c th p (nh n cng t c) th i u khi n b t LED (bnh th ng th LED t t). Khi LED c b t th ph i sng trong m t kho ng th i gian (vi tr m s) tr c khi t t, khi cng t c c nh n v gi th LED ph i sng lin t c.
Gi i ORG LJMP ORG CLR MOV DJNZ SETB RETI ORG MAIN: CLR MOV SJMP END 0000H MAIN 0003H P1.3 R3, #255 R3, $ P1.3 0030H TCON.0 IE, #81H $ ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR ng t ngoi 0. ;B t LED. ;Th i gian LED duy tr tr ng thi sng l ;255.TMachine. ;T t LED. ;K t thc ISR c a ng t ngoi 0. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;Ng t ngoi 0 kch kh i m c th p. ;Cho php ng t ngoi 0. ;Khng lm g (nh y t i ch ). ;K t thc chng trnh
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V d 4: Ng t ngoi kch kh i c nh m - Cho m ch i n nh hnh v . Chn INT0\ c n i v i m t cng t c bnh th ng m c cao, m i khi chn ny c s chuy n tr ng thi t m c cao xu ng m c th p (nh n cng t c) th i u khi n b t LED (bnh th ng th LED t t). Khi LED c b t th ph i sng trong m t kho ng th i gian (vi tr m s) tr c khi t t, khi cng t c c nh n v gi th LED khng c sng lin t c.
Gi i ORG LJMP ORG CLR MOV DJNZ SETB RETI ORG MAIN: SETB MOV SJMP END 0000H MAIN 0003H P1.3 R3, #255 R3, $ P1.3 0030H TCON.0 IE, #81H $ ;i m nh p reset. ;Nh y qua kh i cc vect ng t. ;i m nh p ISR ng t ngoi 0. ;B t LED. ;Th i gian LED duy tr tr ng thi sng l ;255.TMachine. ;T t LED. ;K t thc ISR c a ng t ngoi 0. ;i m nh p chng trnh chnh. ;Chng trnh chnh b t u. ;Ng t ngoi 0 kch kh i c nh m. ;Cho php ng t ngoi 0. ;Khng lm g (nh y t i ch ). ;K t thc chng trnh
VII. PH N BI T P: Bi 1: Vi t o n l nh dng ng t Timer t o sng vung f=2KHz t i P1.7. (fOSC=12MHz). Bi 2: Vi t o n l nh dng ng t Timer t o sng vung f=200Hz t i P1.6. (fOSC=12MHz). Bi 3: Vi t o n l nh dng ng t Timer t o ng th i hai sng vung 1KHz v 50Hz t i P1.0 v P1.1. (fOSC=6MHz) Bi 4: Vi t o n l nh l y m t chu i data ch a trong Ram ngoi b t u t a ch 6200H n a ch 62FFH v xu t ra Port 1, m i l n xu t cch nhau 50ms. S d ng ng t Timer. fOSC=12MHz. Bi 5: Vi t o n l nh nh p data t thi t b ngoi k t n i v i 8051 qua Port 1, m i l n nh p cch nhau 5s, data nh p v c ghi vo vng Ram n i b t u t a ch 50H n a ch 5FH. Bi t r ng sau khi ghi vo nh cu i cng th tr l i ghi vo nh u. S d ng ng t Timer. fOSC=12MHz. Bi 6: Vi t o n l nh pht lin t c chu i s t 0 n 9 ra port n i ti p theo ch UART 8 bit, 2400 baud. S d ng ng t serial. fOSC=12MHz. Gio trnh Vi x l. 199 Bin so n: Ph m Quang Tr
Bi 7: Vi t o n l nh ch nh n data t m t thi t b ngoi g i n 8051 qua port n i ti p (ch UART 8 bit, 19200 baud). N u nh n c k t STX (02H) th b t sng LED, n u nh n c k t ETX (03H) th t t LED, bi t r ng LED c i u khi n b ng ng P1.3 (LED sng khi bit i u khi n b ng 1). S d ng ng t serial. fOSC=11,059MHz. Bi 8: Vi t o n l nh ch nh n 1 xung c nh xu ng a vo chn /INT0 (P3.2), khi c xung th nh p data t Port 1 v pht ra port n i ti p ch UART 9 bit 4800 baud, bit th 9 l bit parity l . fOSC=6MHz. Bi 9: Vi t o n l nh m s xung a vo chn /INT1 (P3.3) v i u khi n relay thng qua chn P3.0 (relay ng khi P3.0 b ng 1), c t s m vo nh 40H c a Ram n i, n u s m cha n 100 th ng relay, n u s m t 100 th ng t relay.
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GIO TRNH VI X
Ph l c 1: Gi i m a ch .
PH L C 1 GI I M A CH
I. T NG QUT: - Tr ng h p 1: Khi c n xc nh t m a ch ho t ng cho m t b nh ho c ngo i vi c n c m ch gi i m a ch .
3FFH 1 KB 000H Khong dung giai ma a ch Giai ma a ch X + 1024 1 KB
X S dung giai ma a ch
- Tr ng h p 2: Khi b nh (ROM ho c RAM) ho c ngo i vi c dung l ng l n c k t h p t nhi u b nh ho c ngo i vi c dung l ng nh l i v i nhau c n c m ch gi i m a ch nh m xc nh chnh xc a ch c a t ng b nh ho c ngo i vi trn ton b khng gian nh .
4 KB 4 KB 2 KB 800H-FFFH
4 KB 000H-FFFH
Giai ma a ch
2 KB 000H-7FFH Khong dung giai ma a ch S dung giai ma a ch
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Ph l c 1: Gi i m a ch . II. PHNG PHP THI T K M CH GI I M A CH :
- M ch gi i m a ch : Dng c ng logic (AND, OR, NOT, ). Dng vi m ch gi i m (74LS138, 74LS154, ).

Mach giai ma a ch I1 I2 IN Cac ng a ch va tn hieu ieu khien O1 O2 O 2N Cac tn hieu CS\ cua cac bo nh
N ngo vao
2N ngo ra
- Qui trnh thi t k m ch gi i m a ch : B c 1: Xc nh s l ng vi m ch nh c n thi t c c dung l ng b nh nh yu c u. B c 2: Xc nh s ng a ch c n thi t cho t ng vi m ch nh . B c 3: L p b ng nh xc nh chnh xc v tr (t m a ch ) c a t ng vi m ch nh trong ton b khng gian nh . B c 4: Ch n l a phng n thi t k m ch gi i m a ch (dng c ng logic hay dng vi m ch gi i m). B c 5: Thi t k m ch gi i m theo phng n ch n. - L p b ng tr ng thi c a m ch gi i m. - N u dng c ng logic: Dng ba K n gi n ha tr ng thi cc ng ra hm s Boolean c a cc ng ra m ch gi i m a ch . S d ng cc c ng logic thi t k d a trn hm Boolean. - N u dng vi m ch gi i m: So snh b ng tr ng thi c a vi m ch gi i m v i b ng tr ng thi c a m ch gi i m thi t k m ch. B c 6: K t n i m ch gi i m vo h th ng.
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Tr ng H Cng nghi p Tp.HCM. 000H FFFH.
1. Bi ton d ng 1: Thi t k 4 KB b nh dng vi m ch 2732 sao cho c t m a ch ho t ng t Gi i B1: S vi m ch s d ng: 1 vi m ch
B2: S ng a ch c a vi m ch: 12 ng (A0-A11) do ch c 1 vi m ch nh v a ch ho t ng b t u t i 000H khng c n dng m ch gi i m a ch . B6: S k t n i:
2. Bi ton d ng 2: Thi t k 8 KB b nh dng vi m ch 6264 sao cho c t m a ch ho t ng t 4FFFH. Gi i B1: S vi m ch s d ng : 1 vi m ch
3000H
B2: S ng a ch c a vi m ch: 13 ng (A0-A12) do a ch ho t ng b t u t i 3000H (khc 0000H) c n dng m ch gi i m a ch . B3: L p b ng nh : Phn vng a ch : IC-6264: 3000H-4FFFH
B4: Phng n thi t k : dng c ng logic B5: Thi t k m ch gi i m:
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B6: S k t n i:
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Tr ng H Cng nghi p Tp.HCM. 0000H
3. Bi ton d ng 3: Thi t k 32 KB b nh dng vi m ch 2764 sao cho c t m a ch ho t ng t 7FFFH. Gi i B1: S vi m ch s d ng : 4 vi m ch B2: S ng a ch c a vi m ch: 13 ng (A0-A12) do s d ng nhi u vi m ch nh (4 vi m ch) c n dng m ch gi i m a ch . B3: L p b ng nh : Phn vng a ch : IC1-2764: 0000H-1FFFH IC2-2764: 2000H-3FFFH IC3-2764: 4000H-5FFFH IC4-2764: 6000H-7FFFH
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Ph l c 1: Gi i m a ch . B6: S k t n i:
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4. Bi ton d ng 4: Thi t k 48 KB b nh dng vi m ch 62128 sao cho c t m a ch ho t ng t FFFFH. Gi i B1: S vi m ch s d ng : 3 vi m ch
B2: S ng a ch c a vi m ch: 14 ng (A0-A13) do s d ng nhi u vi m ch nh (3 vi m ch) v a ch ho t ng b t u t i 8000H c n dng m ch gi i m a ch . B3: L p b ng nh : Phn vng a ch : IC1-62128: 4000H-7FFFH IC2-62128: 8000H-BFFFH IC3-62128: C000H-FFFFH
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Bo nh 48 KB A0 A13 D0 D7 OE WR A14 A15 IC1-62128 A0 4000H-7FFFH A13 D0 D7 OE WR

4000H-FFFFH IC2-62128 IC3-62128 A0 A0 A13 D0 D7 OE WR A13 D0 D7 OE WR C000H-FFFFH CS 8000H-BFFFH CS
CS
CS
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5. Bi ton d ng 5: Thi t k 64 KB b nh dng vi m ch 27128 v 2764 sao cho c t m a ch ho t ng t FFFFH. Gi i B1: S vi m ch s d ng : 3 vi m ch 27128 v 2 vi m ch 2764 B2: S ng a ch c a vi m ch: 27128 c 14 ng (A0-A13) 2764 c 13 ng (A0-A12) do s d ng nhi u vi m ch nh (5 vi m ch) c n dng m ch gi i m a ch . B3: L p b ng nh : Phn vng a ch : IC1-2764: 0000H-1FFFH IC2-2764: 2000H-3FFFH IC3-27128: 4000H-7FFFH IC4-27128: 8000H-BFFFH IC5-27128: C000H-FFFFH
B4: Phng n thi t k : dng c ng logic
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Ph l c 1: Gi i m a ch . B5: Thi t k m ch gi i m:
Bang trang thai
CS A15 A14 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 X X
A13 CSIC1 CSIC2 CSIC3 CSIC4 CSIC5 0 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 X 1 1 1 1 1
A13 A14 A15
Mach giai ma a ch dung cong logic
Dung ba Karnaugh n gian ta c: CSIC1 = A15+A14+A13+CS CSIC2 = A15+A14+A13\+CS CSIC3 = A15+A14\+CS CSIC4 = A15\+A14+CS CSIC5 = A15\+A14\+CS 74LS138 A Q0 A13 A14 Q1 B Q2 A15 C Q3 Vcc Q4 Q5 E1 Q6 CS E2A Q7 E2B Mach giai ma a ch dung vi mach CSIC1 CSIC2 CSIC3 CSIC4 CSIC5
CSIC1 CSIC2 CSIC3 CSIC4 CS CSIC5
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GIO TRNH VI X
Ph l c 2: Thi t k kit vi i u khi n 8051
PH L C 2 THI T K KIT VI I U KHI N 8051

I. C U TRC T NG TH C A 1 KIT VI I U KHI N: 1. Mini kit (B vi i u khi n s d ng b nh trong): C u trc n gi n (mini kit) l c u trc th ng c s d ng thi t k h th ng i u khi n dng vi i u khi n 8051 v t n d ng c t t c 4 port xu t nh p d li u.
8051 Mach dao ong XTAL1 XTAL2 P0.0 ... P0.7 P1.0 ... P1.7 RST ALE +5V PSEN EA P2.0 ... P2.7 P3.0 ... P3.7 Port 2 Port 3 Port 0 Port 1
Mach reset
2. Kit m r ng (B vi i u khi n s d ng b nh ngoi): C u trc m r ng (kit m r ng) l c u trc ch c s d ng thi t k h th ng i u khi n dng vi i u khi n 8051 khi dung l ng c a chng trnh (ho c d li u) v t qu kh nng ch a c a b nh chng trnh (b nh d li u) bn trong chip v ch s d ng c 1 port xu t nh p d li u.
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Ph l c 2: Thi t k kit vi i u khi n 8051 D ng 1:

8051 Mach dao ong XTAL1 XTAL2 AD0 ... AD7 IC giai a hp D0 ... ... Q0 D7 Q7 G OC
2x+1
Mach reset
ROM byte D0 ... D7 A0 ... A7
2x+1
RAM byte D0 ... D7 A0 ... A7
RST
ALE A8 ... A15
A8 ... Ax Port 1 OE CS
A8 ... Ax
EA
P1.0 ... P1.7 PSEN RD WR
OE WR CS
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Ph l c 2: Thi t k kit vi i u khi n 8051 D ng 2:
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Ph l c 2: Thi t k kit vi i u khi n 8051 II. PHN TCH S
NGUYN L KIT VI I U KHI N: (xem hnh v c trnh by)
III. PHNG PHP THI T K : B c 1: Cn c vo yu c u thi t k v dung l ng c a chng trnh i u khi n ch n l a c u trc n gi n (mini) hay c u trc m r ng. B c 2: - Xc nh s l ng b nh (ROM, RAM) v thi t b ngo i vi ch n l a vi c thi t k m ch gi i m a ch . - Xc nh t m a ch ho t ng c a cc b nh v thi t b ngo i vi. B c 3: Phc th o s kh i c a h th ng kit. B c 4: Thi t k m ch gi i m a ch cho kit. B c 5: Thi t k m ch gi i a h p (khi dng b nh ngoi), m ch reset, m ch dao ng v cc m ch h tr khc. B c 6: K t n i ton b m ch thi t k thnh 1 kit vi i u khi n hon ch nh theo s kh i. Lu : Tr ng h p c u trc n gi n (mini) th ch c n quan tm cc b c sau: 1, 3, 5, 6. IV. BI T P THI T K : 1. Bi t p 1: Thi t k m t kit vi i u khi n 8051 c cc ngo i vi sau: 1 x EPROM 4KB, 1 x SRAM 8KB. Gi i B1: Ch n l a c u trc m r ng thi t k kit. B2: S l ng vi m ch nh s d ng: Phn vng a ch : ROM 1 x EPROM 4 KB RAM 1 x SRAM 8 KB EPROM 4KB: 0000H 0FFFH SRAM 8KB: 0000H 1FFFH
B3: Phc th o s kh i c a h th ng:
Gio trnh Vi x l.
215
B4: Thi t k m ch gi i m a ch : khng c n dng m ch gi i m a ch B5: Thi t k m ch gi i a h p, m ch dao ng v m ch reset:

+5V U3 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE 2 5 6 9 12 15 16 19 1 3 4 7 8 13 14 17 18 11 C2 R1 100 SW1
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE
D0 D1 D2 D3 D4 D5 D6 D7 LE
A0 A1 A2 A3 A4 A5 A6 A7
XTAL1
+ C1 10uF 30p 12 MHz C3
RST
RESET SW R2 8K 2
XTAL2
30p
Ma ch gi a i a h p
Ma ch res et
Ma ch dao o ng
B6: S k t n i: (xem hnh v TKK1 c trnh by d i y)
Gio trnh Vi x l.
216
2. Bi t p 2: Thi t k m t kit vi i u khi n 8051 c cc ngo i vi sau: 1 x EPROM 27512, 3 x SRAM 6116. Gi i B1: Ch n l a c u trc m r ng thi t k kit. B2: S l ng vi m ch nh s d ng: Phn vng a ch : ROM 1 x EPROM 27512 (64KB) RAM 3 x SRAM 6116 (2KB) 27512: 0000H FFFFH 6116-1: 0000H 07FFH 6116-2: 0800H 0FFFH 6116-3: 1000H 17FFH

6116-3 OE WR CS Port 1 OE CS OE WR CS EA PSEN RD WR OE WR CS D0 ... D7 A0 ... A7 A8 ... A10 A8 ... A15 A8 ... A10 A8 ... A10
6116-2 6116-1 27512
IC giai a hp D0 ... ... Q0 D7 Q7
D0 ... D7 A0 ... A7
D0 ... D7 A0 ... A7
D0 ... D7 A0 ... A7
8051
XTAL1 XTAL2
Gio trnh Vi x l.
Mach dao ong
Mach reset
RST
217
A11..A15
ALE
AD0 ... AD7
A8 ... A15
P1.0 ... P1.7
Mach giai ma a ch
OC
Ph l c 2: Thi t k kit vi i u khi n 8051 B4: Thi t k m ch gi i m a ch :
B5: Thi t k m ch gi i a h p, m ch dao ng v m ch reset:

+5V U3 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE 2 5 6 9 12 15 16 19 1 3 4 7 8 13 14 17 18 11 C2 R1 100 SW1
D0 D1 D2 D3 D4 D5 D6 D7 LE
A0 A1 A2 A3 A4 A5 A6 A7
XTAL1
+ C1 10uF 30p 12 MHz C3
RST
R ESET SW R2 8K2
XTAL2
30p
Ma ch gia i a h p
Ma ch res et
Ma ch dao o ng
Gio trnh Vi x l.
218
3. Bi t p 3: Thi t k m t kit vi i u khi n 8051 c cc ngo i vi sau: 1 x EPROM 8KB (0000H 1FFFH), 1 x SRAM 8KB (2000H 3FFFH). Gi i B1: Ch n l a c u trc m r ng thi t k kit. B2: S l ng vi m ch nh s d ng: Phn vng a ch : ROM 1 x EPROM 8 KB RAM 1 x SRAM 8 KB EPROM 8KB: 0000H 1FFFH SRAM 8KB: 2000H 3FFFH
Gio trnh Vi x l.
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Ph l c 2: Thi t k kit vi i u khi n 8051 B4: Thi t k m ch gi i m a ch :
B5: Thi t k m ch gi i a h p, m ch dao ng v m ch reset:

+5V U3 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE 2 5 6 9 12 15 16 19 1
3 4 7 8 13 14 17 18 11
D0 D1 D2 D3 D4 D5 D6 D7 LE
A0 A1 A2 A3 A4 A5 A6 A7
C2 R1 100 SW1
XTAL1
+ C1 10uF 30p 12 MHz C3
RST
R ESET SW R2 8K2
XTAL2
30p
Ma ch gia i a h p
Ma ch res et
Ma ch dao o ng
Gio trnh Vi x l.
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+5V AR1 4K7 +5V P2.7 P2.6 P2.5 P2.4 U1 P2.3 P2.2 470 470 D6 LED R9 D8 1N4007 P2.1 R11 470 Q2 D468 470 D5 LED R8 +5V 8051 470 D4 LED R7 470 D3 LED R6 470 D2 LED R5 1 2 3 4 5 6 7 8 9 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 R4 D1 LED 1 2 3 4 5 6 7 8 9 AR3 4K7 +5V
CON1 PORT 0 1 2 3 4 5 6 7 8 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
C2
X1 12 MHz
30p
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 38 37 36 35 34 33 32 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 21 22 23 24 25 26 27 28 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
K2 RELAY 5V 5 3 4 1 2
C3
30p
+5V
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE PSEN +5V VCC GND 40 20 P2.0 +5V CON3 PORT 3 1 2 3 4 5 6 7 8 9 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 1 2 3 4 5 6 7 8 30 29 X1 X2 EA RST 10 11 12 13 14 15 16 17
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
+5V
R1 100 +5V 31 9
C1 10uF
19 18
D7 1N4007 R10 470 Q1 D468
K1 RELAY 5V 5 3 4 1 2
SW1 RESET SW +5V AR2 4K7 1 2 3 4 5 6 7 8 9 AR3 4K7
8K2 R2
CON2 PORT 1 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
Gio trnh Vi x l.
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BUS SYSTEM U1 8051 U2 74LS373 U5 2764 U6 6264
C2
X1 12 MHz
30p PSEN 11 1 LE OE
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 39 38 37 36 35 34 33 32 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE WR RAM Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 21 22 23 24 25 26 27 28 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 10 9 8 7 6 5 4 3 25 24 21 23 2
A8 A9 A10 A11 A12 A13 A14 A15 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A0 A1 A2 A3 A4 A5 A6 A7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE WR RD U3 A13 A14 A15 1 2 3 A B C 1 VPP +5V +5V U7 8255 G1 G2A G2B 6 4 5 ROM +5V ROM RAM 8255 74LS138 22 27 20 OE PGM CE 22 27 20 26 OE WE CS1 CS2
D0 D1 D2 D3 D4 D5 D6 D7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
C3
30p
+5V
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE PSEN +5V VCC GND PSEN 1 3 OE 2 U4A 7408 AR1 4K7 RD 40 20 30 29 ALE PSEN X1 X2 EA RST 10 11 12 13 14 15 16 17
R1 100 31 9
C1 10uF
19 18
SW1 RESET SW
8K2 R2
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
15 14 13 12 11 10 9 7
+5V
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A0 A1 RD WR 8255 9 8
34 33 32 31 30 29 28 27
D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 35 5 36 6 RESET RD WR CS
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
4 3 2 1 40 39 38 37
1 2 3 4 5 6 7 8
CON1 PORT A
CON1 PORT 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
18 19 20 21 22 23 24 25
1 2 3 4 5 6 7 8
CON2 PORT B
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
14 15 16 17 13 12 11 10
1 2 3 4 5 6 7 8
CON3 PORT C
Gio trnh Vi x l.
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BUS SYSTEM U1 8051 U2 74LS373 U5 2764 U6 6264
C2
X1 12 MHz
30p RXD TXD PSEN 11 1 LE OE
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 39 38 37 36 35 34 33 32 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 O0 O1 O2 O3 O4 O5 O6 O7 D0 D1 D2 D3 D4 D5 D6 D7 21 22 23 24 25 26 27 28 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 11 12 13 15 16 17 18 19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 10 9 8 7 6 5 4 3 25 24 21 23 2 10 9 8 7 6 5 4 3 25 24 21 23 2 OE U3 A13 A14 A15 1 2 3 A B C 1 VPP +5V +5V U7 8255 G1 G2A G2B 6 4 5 +5V ROM RAM 8255 ROM WR RD 74LS138 22 27 20 OE PGM CE OE WR RAM 22 27 20 26 OE WE CS1 CS2
A8 A9 A10 A11 A12 A13 A14 A15
A0 A1 A2 A3 A4 A5 A6 A7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
11 12 13 15 16 17 18 19
C3
30p
+5V
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 X1 X2 EA RST VCC GND PSEN 1 3 OE 2 U4A 7408 AR1 4K7 RD 40 20 +5V ALE PSEN 30 29 ALE PSEN P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD 19 18 31 9 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7 10 11 12 13 14 15 16 17
R1 100
C1 10uF
SW1 RESET SW
8K2 R2 34 33 32 31 30 29 28 27 A0 A1 RD WR 8255 U8 13 8 R1IN R2IN R1OUT R2OUT T1IN T2IN C1+ C1C2+ C21 3 4 5 C7 10u 11 10 T1OUT T2OUT GND VV+ VCC 14 7 15 C4 10u 6 2 16 C5 10u +5V 12 9 MAX232 RXD TXD 9 8 35 5 36 6
+5V
D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 RESET RD WR CS
4 3 2 1 40 39 38 37
1 2 3 4 5 6 7 8
CON1 PORT A
CON1 PORT 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
COM1
18 19 20 21 22 23 24 25
1 2 3 4 5 6 7 8
CON2 PORT B
1 6 2 7 3 8 4 9 5
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 C6 10u
14 15 16 17 13 12 11 10
1 2 3 4 5 6 7 8
CON3 PORT C
DB9
Gio trnh Vi x l.
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BUS SYSTEM 8051 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 ALE 11 1 LE OE PSEN 20 18 WR RD ALE PSEN +5V VCC GND 40 20 +5V OE/VPP CE 21 22 23 24 25 26 27 28 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 O0 O1 O2 O3 O4 O5 O6 O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 RD WR 22 27 20 26 10 11 12 13 14 15 16 17 30 29 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE WE CS1 CS2 A8 A9 A10 A11 A12 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 8 7 6 5 4 3 2 1 23 22 19 21 9 10 11 13 14 15 16 17 10 9 8 7 6 5 4 3 25 24 21 23 2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D0 D1 D2 D3 D4 D5 D6 D7 U2 74LS373 U3 2732 U4 6264 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19
U1
CON1 PORT 1 1 2 3 4 5 6 7 8 ALE PSEN
39 38 37 36 35 34 33 32
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7
D0 D1 D2 D3 D4 D5 D6 D7
1 2 3 4 5 6 7 8
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD
19 18
X1 X2
31 9
EA RST
+5V
Hnh ve TKK1
C2
30p + C1 10uF R1 100
X1 12 MHz SW1 RESET SW
Kit vi ieu khien 8051 co: Bo nh chng trnh 4KB (0000H-0FFFH) Bo nh d lieu 8KB (0000H-1FFFH)
C3
30p
R2 8K2
Gio trnh Vi x l.
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BUS SYSTEM U1 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 ALE 11 1 LE OE 21 22 23 24 25 26 27 28 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7 A8 A9 A10 A11 A12 A13 A14 A15 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 11 12 13 15 16 17 18 19 8 7 6 5 4 3 2 1 23 22 19 9 10 11 13 14 15 16 17 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 8051 U2 74LS373 U3 27512 U4 6116
39 38 37 36 35 34 33 32
CON1 PORT 1 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 WR RD ALE PSEN PSEN 22 20 OE/VPP CE RD WR 18 21 20 OE WE CS U5 6116 X1 X2 EA RST U7 VCC GND A B C 40 20 +5V 0000H-07FFH 0800H-0FFFH 1000H-17FFH A11 A12 A13 +5V 1 2 3 A14 A15 +5V RD WR + 30p SW1 RESET SW C1 10uF R1 100 18 21 20 OE WE CS U6 R2 8K2 6116 6 4 5 G1 G2A G2B Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7 74LS138 ALE PSEN 30 29 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD 10 11 12 13 14 15 16 17
1 2 3 4 5 6 7 8
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
19 18
31 9
D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
9 10 11 13 14 15 16 17
D0 D1 D2 D3 D4 D5 D6 D7 8 7 6 5 4 3 2 1 23 22 19
C2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
30p C3
X1 12 MHz
Hnh ve TKK2 Kit vi ieu khien 8051 co: Bo nh chng trnh 64KB (0000H-FFFFH) Bo nh d lieu 6KB (0000H-17FFH)
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
8 7 6 5 4 3 2 1 23 22 19
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
D0 D1 D2 D3 D4 D5 D6 D7
9 10 11 13 14 15 16 17
D0 D1 D2 D3 D4 D5 D6 D7
RD WR
18 21 20
OE WE CS
Gio trnh Vi x l.
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BUS SYSTEM 8051 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 ALE 11 1 LE OE 21 22 23 24 25 26 27 28 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 O0 O1 O2 O3 O4 O5 O6 O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE PGM CE VPP +5V RD WR 22 27 20 26 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE WE CS1 CS2 A8 A9 A10 A11 A12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 10 9 8 7 6 5 4 3 25 24 21 23 2 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 PSEN 22 27 +5V 20 U5 +5V A13 A14 A15 1 2 3 A B C G1 G2A G2B 6 4 5 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 +5V 15 14 13 12 11 10 9 7 74LS138 1 U2 74LS373 U3 2764 U4 6264 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19
U1
39 38 37 36 35 34 33 32
D0 D1 D2 D3 D4 D5 D6 D7
CON1 PORT 1 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 WR RD ALE PSEN +5V VCC GND 40 20 30 29 ALE PSEN
1 2 3 4 5 6 7 8
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
19 18
X1 X2
31 9
EA RST
+5V
C2
Hnh ve TKK3
+ C1 10uF R1 100
30p
X1 12 MHz
C3
Kit vi ieu khien 8051 co: Bo nh chng trnh 8KB (0000H-1FFFH) Bo nh d lieu 8KB (2000H-3FFFH)
30p R2 8K2
SW1 RESET SW
Gio trnh Vi x l.
226
GIO TRNH VI X
Ph l c 3: Thi t k ngo i vi.
PH L C 3 THI T K NGO I VI
I. T NG QUT: Cc thi t b ngo i vi hay cc thi t b xu t nh p c a b vi i u khi n cho ta ng truy n thng gi a b vi i u khi n v th gi i bn ngoi. Cc thi t b ngo i vi c k t n i tr c ti p ho c gin ti p v i b vi i u khi n thng qua cc c ng xu t-nh p (cc port) c a b vi i u khi n. Cc thi t b ngo i vi lun lun ch u s i u khi n (nh n d li u) v s ki m tra (cung c p d li u) c a b vi i u khi n. T t o nn kh nng giao ti p gi a vi i u khi n v i th gi i bn ngoi. Phn lo i ngo i vi: ngo i vi i u khi n logic v ngo i vi i u khi n cng su t. Ch : m t s thng s k thu t c n ch c a chip vi i u khi n 8051 khi thi t k ngo i vi: VOL (Output Low Voltage) = 0.45 V VOH (Output High Voltage) = 4.5 V VIL (Input Low Voltage) = 0 V 1 V VIH (Input High Voltage) = 2V ... 5 V VCC (Operating Voltage) = 5 V 6 V IO(MAX) (DC Output Current) = 25 mA (Port 0) IO(MAX) (DC Output Current) = 15 mA (Port 1, 2, 3) II. NGO I VI I U KHI N LOGIC: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx V d : cc vi m ch s (TTL, CMOS), LED, cc b chuy n i tn hi u (ADC, DAC), bn phm,
Gio trnh Vi x l.
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Ph l c 3: Thi t k ngo i vi. 1. Giao ti p v i LED:

+5V 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 40 20
P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15
ALE PSEN
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
39 38 37 36 35 34 33 32
19 18
R0 R1 R2 R3 R4 R5 R6 R7
D0 D1 D2 D3 D4 D5 D6 D7 R8 100 C2 30p +5V C3 30p X1 12 MHz C1 10uF + R9 8K2 SW1 RESET SW
+5V
Rx
2. Giao ti p v i LED 7 o n (ch hi n th tnh):

+5V 3 8 U1 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 +5V 40 20 VCC GND +5V P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE PSEN 8051 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 X1 X2 EA RST 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 +5V +5V U2 4 5 3 6 2 1 7 BI/RBO RBI LT D3 D2 D1 D0 7447 Ra 7 6 4 2 1 9 10 5 Rg A B C D E F G DP V+ V+
31 9
1 2 3 4 5 6 7 8
+5V
EA RST
X1 X2
VCC GND
U1 8051
Rx
A B C D E F G 13 12 11 10 9 15 14
C2 X1 12 MHz 30p C3
30p
C1 10uF
R8 100
R9 8K2
SW1 RESET SW
Gio trnh Vi x l.
228
Ph l c 3: Thi t k ngo i vi. -
u i m: c u trc v nguyn t c i u khi n n gi n. Nh c i m: S l ng Led 7 o n k t n i v i vi i u khi n khng nhi u v m i Led 7 o n ph i c m t vi m ch gi i m; tiu t n nng l ng r t nhi u (v mu n Led 7 o n sng ph i c dng i n lin t c i qua).
Gio trnh Vi x l.
229
R1
R2
R3
R4
R5
R6
R7
R8 +5V
Rx
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
DIGIT1 V+ V+ V+ V+ V+ V+ V+ V+ V+ V+
DIGIT2
DIGIT3
DIGIT4
DIGIT5
DIGIT6 V+ V+
DIGIT7 V+ V+
DIGIT8 V+ V+
A B C D E F G DP
A B C D E F G DP
A B C D E F G DP
A B C D E F G DP
A B C D E F G DP
A B C D E F G DP
A B C D E F G DP
A B C D E F G DP
U1
21 22 23 24 25 26 27 28 U2 7 1 2 6 D0 D1 D2 D3 A B C D E F G R16 +5V LT RBI BI/RBO 3 5 4 R9 7447
39 38 37 36 35 34 33 32
Ry
10 11 12 13 14 15 16 17
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
1 2 3 4 5 6 7 8
+5V
13 12 11 10 9 15 14
30 29 C2 X1 12 MHz C1 10uF + R17 100 30p C3 R18 8K2 SW1 RESET SW
ALE PSEN
X1 X2
19 18
+5V
40 20
EA RST
31 9
+5V
VCC GND
8051 30p
Gio trnh Vi x l.
230
Ph l c 3: Thi t k ngo i vi. 3. Giao ti p v i LED 7 o n (ch hi n th ng): (Xem hnh v ) -
Ch : -
u i m: Tiu t n nng l ng gim r t nhi u so v i ch tnh (v cc Led 7 o n khng c th p sng lin t c m lun phin sng theo 1 chu k); s l ng Led 7 o n k t n i v i vi i u khi n nhi u; ch c n 1 vi m ch gi i m cho t t c cc Led 7 o n. Nh c i m: c u trc v nguyn t c i u khi n ph c t p. T i m t th i i m ch c 1 Led sng, cc Led cn l i u t t. m t ng i th y c con s (8 digit) sng ln cng m t lc t i 1 th i i m: S l n hi n th h t 8 digit / 1 giy : 40 l n 200 l n TNUMBER = 5 ms 25 ms
Gio trnh Vi x l.
231
Ph l c 3: Thi t k ngo i vi. 4. Giao ti p v i vi m ch 8255:
Vi m ch 8255 l m t vi m ch giao ti p song song c l p trnh. c s d ng giao ti p song song gi a vi i u khi n v thi t b i u khi n bn ngoi. S chn v ch c nng cc chn c a vi m ch 8255 (xem hnh v ) vi m ch 8255 ho t ng c th tr c khi s d ng 8255 ta c n ph i xc nh c u hnh cho 8255 kh i ng 8255 n p cho CWR m t gi tr c th . C u trc t i u khi n c a 8255: (xem hnh v ) Mode 0: ch port xu t-nh p d li u c b n. Mode 1: ch port xu t-nh p d li u c ch t (Strobed I/O). Mode 2: ch port xu t-nh p d li u 2 chi u c ch t (Strobed Bi-directional I/O).
Gio trnh Vi x l.
232
Ph l c 3: Thi t k ngo i vi. IC 8255 giao ti p v i vi i u khi n thng qua 3 bus: - Bus d li u: D0 D7. - Bus a ch : A0 A7. - Bus i u khi n: RD\, WR\, CS\, RESET.
Ch c nng cc chn c a IC giao ti p ngo i vi 8255: - D0-D7: cc ng d li u truy n thng tin v m l nh, tr ng thi v d li u gi a vi i u khi n v IC 8255. - PA0-PA7, PB0-PB7, PC0-PC7: cc c ng xu t-nh p d li u gi a 8255 v i cc thi t b ngo i vi. Cc c ng ny c th l c ng xu t (Output) hay c ng nh p (Input) ty thu c vo l nh i u khi n t vi i u khi n a n 8255, l nh i u khi n c ch a trong thanh ghi t i u khi n (CWR: Control Word Register) nh c u hnh cho cc c ng xu t-nh p. - RESET: thi t l p l i tr ng thi ban u cho IC 8255. - CS\: dng l a ch n IC 8255 khi vi i u khi n giao ti p v i nhi u IC 8255. - A0, A1: dng ch n l a cc c ng xu t-nh p (PA, PB, PC) ho c thanh ghi t i u khi n (CWR) giao ti p v i vi i u khi n. A1 0 0 1 1 A0 0 1 0 1 D0 D7 PA0 PA7 PB0 PB7 PC0 PC7 CWR0 CWR7 Bus d li u Port A Port B Port C Thanh ghi t i u khi n
Gio trnh Vi x l.
233
V d : Xc nh gi tr n p cho CWR xc nh c u hnh ho t ng c a 8255 nh sau: Port A: xu t Port B: xu t Port C: xu t CWR = 80H Port A: nh p Port B: xu t Port C: nh p CWR = 99H Port A: xu t Port B: nh p Port CL: nh p, CH: xu t CWR = 83H Qui trnh kh i ng vi m ch 8255 (n p gi tr c u hnh 8255 cho CWR):
Gio trnh Vi x l.
234
Bi t p: Thi t k kit vi i u khi n c cc ngo i vi sau: 1 EPROM 4KB, 1 SRAM 8 KB, 2 PPI 8255. Bi t p: Thi t k kit vi i u khi n c cc ngo i vi sau: 1 EPROM 2764 (0000H-1FFFH), 1 SRAM 6264 (2000H-3FFFH), 2 PPI 8255 (A000H-BFFFH v E000H-FFFFH).
Gio trnh Vi x l.
235
Ph l c 3: Thi t k ngo i vi. Kit vi i u khi n 8051 c 1 EPROM 4KB, 1 SRAM 8 KB, 2 PPI 8255
BUS SYSTEM
8051 21 22 23 24 25 26 27 28 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 9 8 RD WR A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 LE OE PSEN 20 18 WR RD ALE PSEN +5V 40 20 +5V U7 +5V +5V + C1 10uF R1 100 G1 G2A G2B 6 4 5 A13 A14 A15 1 2 3 A B C 74LS138 OE/VPP CE RD WR 22 27 20 26 OE WE CS1 CS2 35 5 36 6 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 RESET RD WR CS PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 O0 O1 O2 O3 O4 O5 O6 O7 ALE 11 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A8 A9 A10 A11 A12 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 8 7 6 5 4 3 2 1 23 22 19 21 18 19 20 21 22 23 24 25 9 10 11 13 14 15 16 17 10 9 8 7 6 5 4 3 25 24 21 23 2 11 12 13 15 16 17 18 19 34 33 32 31 30 29 28 27 4 3 2 1 40 39 38 37 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A0 A1 A2 A3 A4 A5 A6 A7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 U2 74LS373 U3 2732 U4 6264 U5 8255
U1
39 38 37 36 35 34 33 32
1 2 3 4 5 6 7 8
CON1 PORT A
CON1 PORT 1 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 30 29
1 2 3 4 5 6 7 8
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
19 18
X1 X2
ALE PSEN
ROM 4KB 000H-FFFH RAM 8KB 0000H-1FFFH
1 2 3 4 5 6 7 8
CON2 PORT B
31 9
EA RST
VCC GND
14 15 16 17 13 12 11 10
1 2 3 4 5 6 7 8
CON3 PORT C
C2
I/O 1 2000H-3FFFH
U6 8255
30p
X1 12 MHz SW1 RESET SW
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
15 14 13 12 11 10 9 7
C3
30p
R2 8K2
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A0 A1 RD WR
34 33 32 31 30 29 28 27 9 8 35 5 36 6
D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 RESET RD WR CS
4 3 2 1 40 39 38 37
1 2 3 4 5 6 7 8
CON4 PORT A
18 19 20 21 22 23 24 25
1 2 3 4 5 6 7 8
CON5 PORT B
14 15 16 17 13 12 11 10
1 2 3 4 5 6 7 8
CON6 PORT C
I/O 2 4000H-5FFFH
Gio trnh Vi x l.
236
5. Giao ti p v i bn phm:
C
R4 10K
+5V
8
8051
B
R3 10K
U1
7
R2 10K
21 22 23 24 25 26 27 28 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7
39 38 37 36 35 34 33 32
3
R1 10K
10 11 12 13 14 15 16 17 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 X1 X2 C2 X1 12 MHz +5V 30p C3 C1 10uF + EA RST 31 9 19 18 +5V
1 2 3 4 5 6 7 8
30 29
ALE PSEN
+5V
40 20
VCC GND
R6 100
30p
R5 8K2
SW1 RESET SW
Gio trnh Vi x l.
237
Ph l c 3: Thi t k ngo i vi. III. NGO I VI I U KHI N CNG SU T:
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx V d : cc dy LED, bng n, cu n dy nam chm i n, relay, cu n dy ng c,
M t s ki u m ch giao ti p v thi t b i u khi n cng su t:

Vcc Vcc
Tai
1 2 1 2
Tai
PIN PORT
PIN PORT
em dung cong logic (cong logic s dung loai OC: Output Collector)
Vcc
Vcc
Ta i
Rx PIN PORT Q
Rx PIN POR T Q
Ta i
e m du ng transistor cong suat (transistor s du ng loai co dong Ic > 2 la n don g ta i)
+5V
VDC +5V
Rx U1 1 2 3
Tai DC
U1 1 2
PIN PORT
PIN PORT
Rx
Tai AC
VAC
Giao tiep tai DC cach ly
Giao tiep tai AC cach ly
Gio trnh Vi x l.
238
VAC

Vcc
Ry
Vcc
COM
5 3 LED1 LEDx 1 2 Rx Rx PIN PORT Q PIN PORT Q 4
NC NO
RELAY Vcc (V)
Giao tiep day Led
Giao tiep vi relay
MOTOR STEPPER Rx PIN PORT Q 1 2 3 Rx PIN PORT 4 5 +5V Rx PIN PORT Q

4
Rx PIN PORT
Giao tiep vi ong c bc (dung transistor)
U1 PIN PORT PIN PORT PIN PORT PIN PORT 1 2 3 4 5 6 7 8 +5V 10 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 COM 5 +5V 6 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 18 17 16 15 14 13 12 11 MOTOR STEPPER 1 2 3
ULN2801 - ULN2804
Giao tiep vi ong c bc (dung vi mach)
Gio trnh Vi x l.
239

Giao Trinh VI Xu Ly 8051

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Giao Trinh VI Xu Ly 8051

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KHOA CNG NGH I NT MN I N T CNG NGHI P

KHOA CNG NGH I NT B MN I N T CNG NGHI P

Chng 1: Gi i thi u chung v b vi x l.

Tr ng H Cng nghi p Tp.HCM.

CHNG 1 GI I THI U CHUNG V B

Chng 1: Gi i thi u chung v b vi x l. Kh nng lu tr v ph c h i d li u.

Tr ng H Cng nghi p Tp.HCM.

T ng qut, h vi x l g m: Ph n c ng (Hardware): cc thi t b ngo i vi giao ti p v i con ng i. Ph n m m (Software): chng trnh x l d li u.

Giao trnh Vi x ly.

Bien soan: Pham Quang Tr

Chng 1: Gi i thi u chung v b vi x l.

Tr ng H Cng nghi p Tp.HCM.

Chng 1: Gi i thi u chung v b vi x l.

Tr ng H Cng nghi p Tp.HCM.

Giao trnh Vi x ly.

Bien soan: Pham Quang Tr

Chng 1: Gi i thi u chung v b vi x l. D a vo m s c a b nh : M s : XX YYYY

Tr ng H Cng nghi p Tp.HCM.

Giao trnh Vi x ly.

Bien soan: Pham Quang Tr

Chng 1: Gi i thi u chung v b vi x l. VII. VI X L VI I U KHI N:

Tr ng H Cng nghi p Tp.HCM.

C u trc ph n c ng (Hardware architecture)

Cc ngd ng (Applications) Cc c trng c a t p l nh (Instruction set feature)

VIII. MINH H A KI N TRC C A M T H VI I U KHI N:

Tr ng H Cng nghi p Tp.HCM.

Giao trnh Vi x ly.

Bien soan: Pham Quang Tr

KHOA CNG NGH I NT B MN I N T CNG NGHI P

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

CHNG 2 PH N C NG CHIP VI I U KHI N 8051

Tr ng H Cng nghi p Tp.HCM. 8051 4 128 2 32 1 5 8052 8 256 3 32 1 6

B vi i u khi n DS5000 c a Dallas Semiconductor:

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

Chng 2: Ph n c ng chip vi i u khi n 8051. 2.1. -

Tr ng H Cng nghi p Tp.HCM.

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

Qu trnh c chn port (nh p d li u t chn port).

Qu trnh c b ch t (ki m tra d li u t i chn port).

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

Chng 2: Ph n c ng chip vi i u khi n 8051.

Tr ng H Cng nghi p Tp.HCM.

Cc dy thanh ghi: cho php truy xu t d li u nhanh, l nh truy xu t n gi n v ng n g n.

B ng s li u d i y minh h a a ch c a cc nh trong m t dy v cc k hi u thanh ghi R0 R7 c gn cho t ng nh trong dy tch c c.

Chng 2: Ph n c ng chip vi i u khi n 8051. 1.3. Thanh ghi ch c nng c bi t (SFR):

Tr ng H Cng nghi p Tp.HCM.