ENEL 111

A NAND gate:

Y = A.B = A + B

is the same as an OR gate with two NOT gates

Similarly a NOR gate is the same as an AND gate with two inverters Y = A + B = A.B

not the individual terms change the sign not the lot

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NAND gates and Duality Adders Multiplexers
not the individual inputs change the gate not the output

It is possible to implement any boolean expression using only NAND gates

A + B = A.B

AND

A B

A.B A.B

OR
A A+B

De Morgan can also be represented visually:

B

Dual the gates, remember two nots together can be removed.

A B A.B A.B A+B B

AND feeding OR

x2 x4

x3

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b @Q W U & b

NAND Gate Representation

NOT

NAND Gate representation

Implement the following circuit using only NAND gates
x2

x4

x3

Implement NOT, AND and OR using NOR gates

Example

AND gate

7 E E1 7 I1 4G1"@F"C46 FC b 4H1

7C I F'Q b A8 C

E DX U
 

7 E E1 7 I1 4G1"@F"C46 FC b 4H1

7C I F'Q b A8 C

7 E I1 4G1"@DX 4&

E DX U


dual circuit:

Similar pattern to using NAND gates (not surprising)

X X

NOT

NOR Gate representation

A.B

A.B

AND
B X4 X3 X2 A+B A.B A+B

X3 X2

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X4

Two NOR gates in sequence acting as NOTs can be eliminated:

The half adder

The half adder is a circuit for adding two single bit numbers Develop a truth table and Boolean expressions for the half adder

Q b AFC I 3

 

A B

OR

A B

A.B

It is also possible to implement any boolean expression using only NOR gates Implement the following circuit using only NOR gates

7 E E1 7 I1 4G1"@F"C46 FC b 4H1
S and C are the Sum and Carry

7C I F'Q b A8 C

E DX U `

g 7 E I1 4G1"@DX 4& g 7 E I1 4G1"@DX 4&

 

A 0 0 1 1

B S C 0 1 0 1

The sum is XOR operation and the carry an AND: A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 C 0 0 0 1

A B C S

The full adder

Exercise:

Sum 1 when odd number of inputs is 1 = XOR gate

Carry out - simplifies to 3 pairs

Cin 0 0 0 0 1 1 1 1

A 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

Cout 0 0 0 1 0 1 1 1

Complete the Karnaugh maps for the Sum and the Carry out columns

AB Cin 0 1

00 01 1 1

11

10 1

AB Cin 0 1

1
Cout = A.B + A.Cin + B.Cin

Sum = Cin xor A xor B

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U FC 9 FC HX T ' 53 U W 7 3 Q U1 Q C

Q b AFC I 3
Develop a truth table and Boolean expressions for the full adder, this circuit also includes a carry in.
Cin 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 S C

 

U b 4VIHX 4 b A8 "C9 DX U C I U1 I E E

U b C FC I

A B Cin

Sum full adder

Cout

00 01

11 1

10

Sum

Cout

Cin

Sum = Cin xor A xor B

Cout = A.B + A.Cin + B.Cin

sel 0 0 0 0 1 1 1 1

a 0 0 1 1 0 0 1 1

b 0 1 0 1 0 1 0 1

out 0 0 1 1 0 1 0 1

sel 0 0 1 1

a 0 1 ? ?

b ? ? 0 1

out 0 1 0 1

AB sel 00 01 0 1 1

11 1 1

if a is selected, dont care about b.

Principal can be extended to 4:1 2 select lines and 4 data lines 8:1 3 select lines and 8 data lines out

AB sel 00 01 0 1 1

and so on

11 1 1

10 1

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b I I U p b A @ BEDX d

10 1

U1 C 4 53

The Multiplexer
Selects one of 2n inputs and copies it to a single output The selected line is determined from the bit combination (address) on the n selection lines e.g. 1 from 2 mutiplexer a

sel 0 0 0 0 1 1 1 1 a 0 0 1 1 0 0 1 1 b 0 1 0 1 0 1 0 1
sel ab

Q b AFC I 3

 

BEDX W BU@ W U b &VIHX @ C I b I I U p b A "@BEDX d



n=1
0 1

out

out

sel
00 01 11 10

0 1
out =

output = sel.a + sel.b

data

sel

Change circuits using one set of gates (eg AND, OR, NOT) to their equivalent using NAND or NOR gates only (and vice versa).

Be familiar with half-, full- adders and multiplexer circuits.

Be able to construct and interpret Karnaugh maps with up to 4 input variables.

(if you need practice, come to the tutorial)

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